f57f8b901912dba2829ebd3ced20ec754c61a813
[linux-2.6.git] / arch / x86_64 / kernel / io_apic.c
1 /*
2  *      Intel IO-APIC support for multi-Pentium hosts.
3  *
4  *      Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5  *
6  *      Many thanks to Stig Venaas for trying out countless experimental
7  *      patches and reporting/debugging problems patiently!
8  *
9  *      (c) 1999, Multiple IO-APIC support, developed by
10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
13  *      and Ingo Molnar <mingo@redhat.com>
14  *
15  *      Fixes
16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
17  *                                      thanks to Eric Gilmore
18  *                                      and Rolf G. Tews
19  *                                      for testing these extensively
20  *      Paul Diefenbaugh        :       Added full ACPI support
21  */
22
23 #include <linux/mm.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/acpi.h>
31 #include <linux/sysdev.h>
32 #include <linux/msi.h>
33 #include <linux/htirq.h>
34 #ifdef CONFIG_ACPI
35 #include <acpi/acpi_bus.h>
36 #endif
37
38 #include <asm/idle.h>
39 #include <asm/io.h>
40 #include <asm/smp.h>
41 #include <asm/desc.h>
42 #include <asm/proto.h>
43 #include <asm/mach_apic.h>
44 #include <asm/acpi.h>
45 #include <asm/dma.h>
46 #include <asm/nmi.h>
47 #include <asm/msidef.h>
48 #include <asm/hypertransport.h>
49
50 struct irq_cfg {
51         cpumask_t domain;
52         cpumask_t old_domain;
53         unsigned move_cleanup_count;
54         u8 vector;
55         u8 move_in_progress : 1;
56 };
57
58 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
59 struct irq_cfg irq_cfg[NR_IRQS] __read_mostly = {
60         [0]  = { .domain = CPU_MASK_ALL, .vector = IRQ0_VECTOR,  },
61         [1]  = { .domain = CPU_MASK_ALL, .vector = IRQ1_VECTOR,  },
62         [2]  = { .domain = CPU_MASK_ALL, .vector = IRQ2_VECTOR,  },
63         [3]  = { .domain = CPU_MASK_ALL, .vector = IRQ3_VECTOR,  },
64         [4]  = { .domain = CPU_MASK_ALL, .vector = IRQ4_VECTOR,  },
65         [5]  = { .domain = CPU_MASK_ALL, .vector = IRQ5_VECTOR,  },
66         [6]  = { .domain = CPU_MASK_ALL, .vector = IRQ6_VECTOR,  },
67         [7]  = { .domain = CPU_MASK_ALL, .vector = IRQ7_VECTOR,  },
68         [8]  = { .domain = CPU_MASK_ALL, .vector = IRQ8_VECTOR,  },
69         [9]  = { .domain = CPU_MASK_ALL, .vector = IRQ9_VECTOR,  },
70         [10] = { .domain = CPU_MASK_ALL, .vector = IRQ10_VECTOR, },
71         [11] = { .domain = CPU_MASK_ALL, .vector = IRQ11_VECTOR, },
72         [12] = { .domain = CPU_MASK_ALL, .vector = IRQ12_VECTOR, },
73         [13] = { .domain = CPU_MASK_ALL, .vector = IRQ13_VECTOR, },
74         [14] = { .domain = CPU_MASK_ALL, .vector = IRQ14_VECTOR, },
75         [15] = { .domain = CPU_MASK_ALL, .vector = IRQ15_VECTOR, },
76 };
77
78 static int assign_irq_vector(int irq, cpumask_t mask);
79
80 #define __apicdebuginit  __init
81
82 int sis_apic_bug; /* not actually supported, dummy for compile */
83
84 static int no_timer_check;
85
86 static int disable_timer_pin_1 __initdata;
87
88 int timer_over_8254 __initdata = 1;
89
90 /* Where if anywhere is the i8259 connect in external int mode */
91 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
92
93 static DEFINE_SPINLOCK(ioapic_lock);
94 DEFINE_SPINLOCK(vector_lock);
95
96 /*
97  * # of IRQ routing registers
98  */
99 int nr_ioapic_registers[MAX_IO_APICS];
100
101 /*
102  * Rough estimation of how many shared IRQs there are, can
103  * be changed anytime.
104  */
105 #define MAX_PLUS_SHARED_IRQS NR_IRQS
106 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
107
108 /*
109  * This is performance-critical, we want to do it O(1)
110  *
111  * the indexing order of this array favors 1:1 mappings
112  * between pins and IRQs.
113  */
114
115 static struct irq_pin_list {
116         short apic, pin, next;
117 } irq_2_pin[PIN_MAP_SIZE];
118
119 struct io_apic {
120         unsigned int index;
121         unsigned int unused[3];
122         unsigned int data;
123 };
124
125 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
126 {
127         return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
128                 + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK);
129 }
130
131 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
132 {
133         struct io_apic __iomem *io_apic = io_apic_base(apic);
134         writel(reg, &io_apic->index);
135         return readl(&io_apic->data);
136 }
137
138 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
139 {
140         struct io_apic __iomem *io_apic = io_apic_base(apic);
141         writel(reg, &io_apic->index);
142         writel(value, &io_apic->data);
143 }
144
145 /*
146  * Re-write a value: to be used for read-modify-write
147  * cycles where the read already set up the index register.
148  */
149 static inline void io_apic_modify(unsigned int apic, unsigned int value)
150 {
151         struct io_apic __iomem *io_apic = io_apic_base(apic);
152         writel(value, &io_apic->data);
153 }
154
155 static int io_apic_level_ack_pending(unsigned int irq)
156 {
157         struct irq_pin_list *entry;
158         unsigned long flags;
159         int pending = 0;
160
161         spin_lock_irqsave(&ioapic_lock, flags);
162         entry = irq_2_pin + irq;
163         for (;;) {
164                 unsigned int reg;
165                 int pin;
166
167                 pin = entry->pin;
168                 if (pin == -1)
169                         break;
170                 reg = io_apic_read(entry->apic, 0x10 + pin*2);
171                 /* Is the remote IRR bit set? */
172                 pending |= (reg >> 14) & 1;
173                 if (!entry->next)
174                         break;
175                 entry = irq_2_pin + entry->next;
176         }
177         spin_unlock_irqrestore(&ioapic_lock, flags);
178         return pending;
179 }
180
181 /*
182  * Synchronize the IO-APIC and the CPU by doing
183  * a dummy read from the IO-APIC
184  */
185 static inline void io_apic_sync(unsigned int apic)
186 {
187         struct io_apic __iomem *io_apic = io_apic_base(apic);
188         readl(&io_apic->data);
189 }
190
191 #define __DO_ACTION(R, ACTION, FINAL)                                   \
192                                                                         \
193 {                                                                       \
194         int pin;                                                        \
195         struct irq_pin_list *entry = irq_2_pin + irq;                   \
196                                                                         \
197         BUG_ON(irq >= NR_IRQS);                                         \
198         for (;;) {                                                      \
199                 unsigned int reg;                                       \
200                 pin = entry->pin;                                       \
201                 if (pin == -1)                                          \
202                         break;                                          \
203                 reg = io_apic_read(entry->apic, 0x10 + R + pin*2);      \
204                 reg ACTION;                                             \
205                 io_apic_modify(entry->apic, reg);                       \
206                 FINAL;                                                  \
207                 if (!entry->next)                                       \
208                         break;                                          \
209                 entry = irq_2_pin + entry->next;                        \
210         }                                                               \
211 }
212
213 union entry_union {
214         struct { u32 w1, w2; };
215         struct IO_APIC_route_entry entry;
216 };
217
218 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
219 {
220         union entry_union eu;
221         unsigned long flags;
222         spin_lock_irqsave(&ioapic_lock, flags);
223         eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
224         eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
225         spin_unlock_irqrestore(&ioapic_lock, flags);
226         return eu.entry;
227 }
228
229 /*
230  * When we write a new IO APIC routing entry, we need to write the high
231  * word first! If the mask bit in the low word is clear, we will enable
232  * the interrupt, and we need to make sure the entry is fully populated
233  * before that happens.
234  */
235 static void
236 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
237 {
238         union entry_union eu;
239         eu.entry = e;
240         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
241         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
242 }
243
244 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
245 {
246         unsigned long flags;
247         spin_lock_irqsave(&ioapic_lock, flags);
248         __ioapic_write_entry(apic, pin, e);
249         spin_unlock_irqrestore(&ioapic_lock, flags);
250 }
251
252 /*
253  * When we mask an IO APIC routing entry, we need to write the low
254  * word first, in order to set the mask bit before we change the
255  * high bits!
256  */
257 static void ioapic_mask_entry(int apic, int pin)
258 {
259         unsigned long flags;
260         union entry_union eu = { .entry.mask = 1 };
261
262         spin_lock_irqsave(&ioapic_lock, flags);
263         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
264         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
265         spin_unlock_irqrestore(&ioapic_lock, flags);
266 }
267
268 #ifdef CONFIG_SMP
269 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector)
270 {
271         int apic, pin;
272         struct irq_pin_list *entry = irq_2_pin + irq;
273
274         BUG_ON(irq >= NR_IRQS);
275         for (;;) {
276                 unsigned int reg;
277                 apic = entry->apic;
278                 pin = entry->pin;
279                 if (pin == -1)
280                         break;
281                 io_apic_write(apic, 0x11 + pin*2, dest);
282                 reg = io_apic_read(apic, 0x10 + pin*2);
283                 reg &= ~0x000000ff;
284                 reg |= vector;
285                 io_apic_modify(apic, reg);
286                 if (!entry->next)
287                         break;
288                 entry = irq_2_pin + entry->next;
289         }
290 }
291
292 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
293 {
294         struct irq_cfg *cfg = irq_cfg + irq;
295         unsigned long flags;
296         unsigned int dest;
297         cpumask_t tmp;
298
299         cpus_and(tmp, mask, cpu_online_map);
300         if (cpus_empty(tmp))
301                 return;
302
303         if (assign_irq_vector(irq, mask))
304                 return;
305
306         cpus_and(tmp, cfg->domain, mask);
307         dest = cpu_mask_to_apicid(tmp);
308
309         /*
310          * Only the high 8 bits are valid.
311          */
312         dest = SET_APIC_LOGICAL_ID(dest);
313
314         spin_lock_irqsave(&ioapic_lock, flags);
315         __target_IO_APIC_irq(irq, dest, cfg->vector);
316         irq_desc[irq].affinity = mask;
317         spin_unlock_irqrestore(&ioapic_lock, flags);
318 }
319 #endif
320
321 /*
322  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
323  * shared ISA-space IRQs, so we have to support them. We are super
324  * fast in the common case, and fast for shared ISA-space IRQs.
325  */
326 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
327 {
328         static int first_free_entry = NR_IRQS;
329         struct irq_pin_list *entry = irq_2_pin + irq;
330
331         BUG_ON(irq >= NR_IRQS);
332         while (entry->next)
333                 entry = irq_2_pin + entry->next;
334
335         if (entry->pin != -1) {
336                 entry->next = first_free_entry;
337                 entry = irq_2_pin + entry->next;
338                 if (++first_free_entry >= PIN_MAP_SIZE)
339                         panic("io_apic.c: ran out of irq_2_pin entries!");
340         }
341         entry->apic = apic;
342         entry->pin = pin;
343 }
344
345
346 #define DO_ACTION(name,R,ACTION, FINAL)                                 \
347                                                                         \
348         static void name##_IO_APIC_irq (unsigned int irq)               \
349         __DO_ACTION(R, ACTION, FINAL)
350
351 DO_ACTION( __mask,             0, |= 0x00010000, io_apic_sync(entry->apic) )
352                                                 /* mask = 1 */
353 DO_ACTION( __unmask,           0, &= 0xfffeffff, )
354                                                 /* mask = 0 */
355
356 static void mask_IO_APIC_irq (unsigned int irq)
357 {
358         unsigned long flags;
359
360         spin_lock_irqsave(&ioapic_lock, flags);
361         __mask_IO_APIC_irq(irq);
362         spin_unlock_irqrestore(&ioapic_lock, flags);
363 }
364
365 static void unmask_IO_APIC_irq (unsigned int irq)
366 {
367         unsigned long flags;
368
369         spin_lock_irqsave(&ioapic_lock, flags);
370         __unmask_IO_APIC_irq(irq);
371         spin_unlock_irqrestore(&ioapic_lock, flags);
372 }
373
374 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
375 {
376         struct IO_APIC_route_entry entry;
377
378         /* Check delivery_mode to be sure we're not clearing an SMI pin */
379         entry = ioapic_read_entry(apic, pin);
380         if (entry.delivery_mode == dest_SMI)
381                 return;
382         /*
383          * Disable it in the IO-APIC irq-routing table:
384          */
385         ioapic_mask_entry(apic, pin);
386 }
387
388 static void clear_IO_APIC (void)
389 {
390         int apic, pin;
391
392         for (apic = 0; apic < nr_ioapics; apic++)
393                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
394                         clear_IO_APIC_pin(apic, pin);
395 }
396
397 int skip_ioapic_setup;
398 int ioapic_force;
399
400 /* dummy parsing: see setup.c */
401
402 static int __init disable_ioapic_setup(char *str)
403 {
404         skip_ioapic_setup = 1;
405         return 0;
406 }
407 early_param("noapic", disable_ioapic_setup);
408
409 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
410 static int __init disable_timer_pin_setup(char *arg)
411 {
412         disable_timer_pin_1 = 1;
413         return 1;
414 }
415 __setup("disable_timer_pin_1", disable_timer_pin_setup);
416
417 static int __init setup_disable_8254_timer(char *s)
418 {
419         timer_over_8254 = -1;
420         return 1;
421 }
422 static int __init setup_enable_8254_timer(char *s)
423 {
424         timer_over_8254 = 2;
425         return 1;
426 }
427
428 __setup("disable_8254_timer", setup_disable_8254_timer);
429 __setup("enable_8254_timer", setup_enable_8254_timer);
430
431
432 /*
433  * Find the IRQ entry number of a certain pin.
434  */
435 static int find_irq_entry(int apic, int pin, int type)
436 {
437         int i;
438
439         for (i = 0; i < mp_irq_entries; i++)
440                 if (mp_irqs[i].mpc_irqtype == type &&
441                     (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
442                      mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
443                     mp_irqs[i].mpc_dstirq == pin)
444                         return i;
445
446         return -1;
447 }
448
449 /*
450  * Find the pin to which IRQ[irq] (ISA) is connected
451  */
452 static int __init find_isa_irq_pin(int irq, int type)
453 {
454         int i;
455
456         for (i = 0; i < mp_irq_entries; i++) {
457                 int lbus = mp_irqs[i].mpc_srcbus;
458
459                 if (test_bit(lbus, mp_bus_not_pci) &&
460                     (mp_irqs[i].mpc_irqtype == type) &&
461                     (mp_irqs[i].mpc_srcbusirq == irq))
462
463                         return mp_irqs[i].mpc_dstirq;
464         }
465         return -1;
466 }
467
468 static int __init find_isa_irq_apic(int irq, int type)
469 {
470         int i;
471
472         for (i = 0; i < mp_irq_entries; i++) {
473                 int lbus = mp_irqs[i].mpc_srcbus;
474
475                 if (test_bit(lbus, mp_bus_not_pci) &&
476                     (mp_irqs[i].mpc_irqtype == type) &&
477                     (mp_irqs[i].mpc_srcbusirq == irq))
478                         break;
479         }
480         if (i < mp_irq_entries) {
481                 int apic;
482                 for(apic = 0; apic < nr_ioapics; apic++) {
483                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
484                                 return apic;
485                 }
486         }
487
488         return -1;
489 }
490
491 /*
492  * Find a specific PCI IRQ entry.
493  * Not an __init, possibly needed by modules
494  */
495 static int pin_2_irq(int idx, int apic, int pin);
496
497 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
498 {
499         int apic, i, best_guess = -1;
500
501         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
502                 bus, slot, pin);
503         if (mp_bus_id_to_pci_bus[bus] == -1) {
504                 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
505                 return -1;
506         }
507         for (i = 0; i < mp_irq_entries; i++) {
508                 int lbus = mp_irqs[i].mpc_srcbus;
509
510                 for (apic = 0; apic < nr_ioapics; apic++)
511                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
512                             mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
513                                 break;
514
515                 if (!test_bit(lbus, mp_bus_not_pci) &&
516                     !mp_irqs[i].mpc_irqtype &&
517                     (bus == lbus) &&
518                     (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
519                         int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
520
521                         if (!(apic || IO_APIC_IRQ(irq)))
522                                 continue;
523
524                         if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
525                                 return irq;
526                         /*
527                          * Use the first all-but-pin matching entry as a
528                          * best-guess fuzzy result for broken mptables.
529                          */
530                         if (best_guess < 0)
531                                 best_guess = irq;
532                 }
533         }
534         BUG_ON(best_guess >= NR_IRQS);
535         return best_guess;
536 }
537
538 /* ISA interrupts are always polarity zero edge triggered,
539  * when listed as conforming in the MP table. */
540
541 #define default_ISA_trigger(idx)        (0)
542 #define default_ISA_polarity(idx)       (0)
543
544 /* PCI interrupts are always polarity one level triggered,
545  * when listed as conforming in the MP table. */
546
547 #define default_PCI_trigger(idx)        (1)
548 #define default_PCI_polarity(idx)       (1)
549
550 static int __init MPBIOS_polarity(int idx)
551 {
552         int bus = mp_irqs[idx].mpc_srcbus;
553         int polarity;
554
555         /*
556          * Determine IRQ line polarity (high active or low active):
557          */
558         switch (mp_irqs[idx].mpc_irqflag & 3)
559         {
560                 case 0: /* conforms, ie. bus-type dependent polarity */
561                         if (test_bit(bus, mp_bus_not_pci))
562                                 polarity = default_ISA_polarity(idx);
563                         else
564                                 polarity = default_PCI_polarity(idx);
565                         break;
566                 case 1: /* high active */
567                 {
568                         polarity = 0;
569                         break;
570                 }
571                 case 2: /* reserved */
572                 {
573                         printk(KERN_WARNING "broken BIOS!!\n");
574                         polarity = 1;
575                         break;
576                 }
577                 case 3: /* low active */
578                 {
579                         polarity = 1;
580                         break;
581                 }
582                 default: /* invalid */
583                 {
584                         printk(KERN_WARNING "broken BIOS!!\n");
585                         polarity = 1;
586                         break;
587                 }
588         }
589         return polarity;
590 }
591
592 static int MPBIOS_trigger(int idx)
593 {
594         int bus = mp_irqs[idx].mpc_srcbus;
595         int trigger;
596
597         /*
598          * Determine IRQ trigger mode (edge or level sensitive):
599          */
600         switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
601         {
602                 case 0: /* conforms, ie. bus-type dependent */
603                         if (test_bit(bus, mp_bus_not_pci))
604                                 trigger = default_ISA_trigger(idx);
605                         else
606                                 trigger = default_PCI_trigger(idx);
607                         break;
608                 case 1: /* edge */
609                 {
610                         trigger = 0;
611                         break;
612                 }
613                 case 2: /* reserved */
614                 {
615                         printk(KERN_WARNING "broken BIOS!!\n");
616                         trigger = 1;
617                         break;
618                 }
619                 case 3: /* level */
620                 {
621                         trigger = 1;
622                         break;
623                 }
624                 default: /* invalid */
625                 {
626                         printk(KERN_WARNING "broken BIOS!!\n");
627                         trigger = 0;
628                         break;
629                 }
630         }
631         return trigger;
632 }
633
634 static inline int irq_polarity(int idx)
635 {
636         return MPBIOS_polarity(idx);
637 }
638
639 static inline int irq_trigger(int idx)
640 {
641         return MPBIOS_trigger(idx);
642 }
643
644 static int pin_2_irq(int idx, int apic, int pin)
645 {
646         int irq, i;
647         int bus = mp_irqs[idx].mpc_srcbus;
648
649         /*
650          * Debugging check, we are in big trouble if this message pops up!
651          */
652         if (mp_irqs[idx].mpc_dstirq != pin)
653                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
654
655         if (test_bit(bus, mp_bus_not_pci)) {
656                 irq = mp_irqs[idx].mpc_srcbusirq;
657         } else {
658                 /*
659                  * PCI IRQs are mapped in order
660                  */
661                 i = irq = 0;
662                 while (i < apic)
663                         irq += nr_ioapic_registers[i++];
664                 irq += pin;
665         }
666         BUG_ON(irq >= NR_IRQS);
667         return irq;
668 }
669
670 static int __assign_irq_vector(int irq, cpumask_t mask)
671 {
672         /*
673          * NOTE! The local APIC isn't very good at handling
674          * multiple interrupts at the same interrupt level.
675          * As the interrupt level is determined by taking the
676          * vector number and shifting that right by 4, we
677          * want to spread these out a bit so that they don't
678          * all fall in the same interrupt level.
679          *
680          * Also, we've got to be careful not to trash gate
681          * 0x80, because int 0x80 is hm, kind of importantish. ;)
682          */
683         static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
684         unsigned int old_vector;
685         int cpu;
686         struct irq_cfg *cfg;
687
688         BUG_ON((unsigned)irq >= NR_IRQS);
689         cfg = &irq_cfg[irq];
690
691         /* Only try and allocate irqs on cpus that are present */
692         cpus_and(mask, mask, cpu_online_map);
693
694         if ((cfg->move_in_progress) || cfg->move_cleanup_count)
695                 return -EBUSY;
696
697         old_vector = cfg->vector;
698         if (old_vector) {
699                 cpumask_t tmp;
700                 cpus_and(tmp, cfg->domain, mask);
701                 if (!cpus_empty(tmp))
702                         return 0;
703         }
704
705         for_each_cpu_mask(cpu, mask) {
706                 cpumask_t domain, new_mask;
707                 int new_cpu;
708                 int vector, offset;
709
710                 domain = vector_allocation_domain(cpu);
711                 cpus_and(new_mask, domain, cpu_online_map);
712
713                 vector = current_vector;
714                 offset = current_offset;
715 next:
716                 vector += 8;
717                 if (vector >= FIRST_SYSTEM_VECTOR) {
718                         /* If we run out of vectors on large boxen, must share them. */
719                         offset = (offset + 1) % 8;
720                         vector = FIRST_DEVICE_VECTOR + offset;
721                 }
722                 if (unlikely(current_vector == vector))
723                         continue;
724                 if (vector == IA32_SYSCALL_VECTOR)
725                         goto next;
726                 for_each_cpu_mask(new_cpu, new_mask)
727                         if (per_cpu(vector_irq, new_cpu)[vector] != -1)
728                                 goto next;
729                 /* Found one! */
730                 current_vector = vector;
731                 current_offset = offset;
732                 if (old_vector) {
733                         cfg->move_in_progress = 1;
734                         cfg->old_domain = cfg->domain;
735                 }
736                 for_each_cpu_mask(new_cpu, new_mask)
737                         per_cpu(vector_irq, new_cpu)[vector] = irq;
738                 cfg->vector = vector;
739                 cfg->domain = domain;
740                 return 0;
741         }
742         return -ENOSPC;
743 }
744
745 static int assign_irq_vector(int irq, cpumask_t mask)
746 {
747         int err;
748         unsigned long flags;
749
750         spin_lock_irqsave(&vector_lock, flags);
751         err = __assign_irq_vector(irq, mask);
752         spin_unlock_irqrestore(&vector_lock, flags);
753         return err;
754 }
755
756 static void __clear_irq_vector(int irq)
757 {
758         struct irq_cfg *cfg;
759         cpumask_t mask;
760         int cpu, vector;
761
762         BUG_ON((unsigned)irq >= NR_IRQS);
763         cfg = &irq_cfg[irq];
764         BUG_ON(!cfg->vector);
765
766         vector = cfg->vector;
767         cpus_and(mask, cfg->domain, cpu_online_map);
768         for_each_cpu_mask(cpu, mask)
769                 per_cpu(vector_irq, cpu)[vector] = -1;
770
771         cfg->vector = 0;
772         cfg->domain = CPU_MASK_NONE;
773 }
774
775 void __setup_vector_irq(int cpu)
776 {
777         /* Initialize vector_irq on a new cpu */
778         /* This function must be called with vector_lock held */
779         int irq, vector;
780
781         /* Mark the inuse vectors */
782         for (irq = 0; irq < NR_IRQS; ++irq) {
783                 if (!cpu_isset(cpu, irq_cfg[irq].domain))
784                         continue;
785                 vector = irq_cfg[irq].vector;
786                 per_cpu(vector_irq, cpu)[vector] = irq;
787         }
788         /* Mark the free vectors */
789         for (vector = 0; vector < NR_VECTORS; ++vector) {
790                 irq = per_cpu(vector_irq, cpu)[vector];
791                 if (irq < 0)
792                         continue;
793                 if (!cpu_isset(cpu, irq_cfg[irq].domain))
794                         per_cpu(vector_irq, cpu)[vector] = -1;
795         }
796 }
797
798
799 static struct irq_chip ioapic_chip;
800
801 static void ioapic_register_intr(int irq, unsigned long trigger)
802 {
803         if (trigger) {
804                 irq_desc[irq].status |= IRQ_LEVEL;
805                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
806                                               handle_fasteoi_irq, "fasteoi");
807         } else {
808                 irq_desc[irq].status &= ~IRQ_LEVEL;
809                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
810                                               handle_edge_irq, "edge");
811         }
812 }
813
814 static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq,
815                               int trigger, int polarity)
816 {
817         struct irq_cfg *cfg = irq_cfg + irq;
818         struct IO_APIC_route_entry entry;
819         cpumask_t mask;
820
821         if (!IO_APIC_IRQ(irq))
822                 return;
823
824         mask = TARGET_CPUS;
825         if (assign_irq_vector(irq, mask))
826                 return;
827
828         cpus_and(mask, cfg->domain, mask);
829
830         apic_printk(APIC_VERBOSE,KERN_DEBUG
831                     "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
832                     "IRQ %d Mode:%i Active:%i)\n",
833                     apic, mp_ioapics[apic].mpc_apicid, pin, cfg->vector,
834                     irq, trigger, polarity);
835
836         /*
837          * add it to the IO-APIC irq-routing table:
838          */
839         memset(&entry,0,sizeof(entry));
840
841         entry.delivery_mode = INT_DELIVERY_MODE;
842         entry.dest_mode = INT_DEST_MODE;
843         entry.dest = cpu_mask_to_apicid(mask);
844         entry.mask = 0;                         /* enable IRQ */
845         entry.trigger = trigger;
846         entry.polarity = polarity;
847         entry.vector = cfg->vector;
848
849         /* Mask level triggered irqs.
850          * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
851          */
852         if (trigger)
853                 entry.mask = 1;
854
855         ioapic_register_intr(irq, trigger);
856         if (irq < 16)
857                 disable_8259A_irq(irq);
858
859         ioapic_write_entry(apic, pin, entry);
860 }
861
862 static void __init setup_IO_APIC_irqs(void)
863 {
864         int apic, pin, idx, irq, first_notcon = 1;
865
866         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
867
868         for (apic = 0; apic < nr_ioapics; apic++) {
869         for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
870
871                 idx = find_irq_entry(apic,pin,mp_INT);
872                 if (idx == -1) {
873                         if (first_notcon) {
874                                 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
875                                 first_notcon = 0;
876                         } else
877                                 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
878                         continue;
879                 }
880
881                 irq = pin_2_irq(idx, apic, pin);
882                 add_pin_to_irq(irq, apic, pin);
883
884                 setup_IO_APIC_irq(apic, pin, irq,
885                                   irq_trigger(idx), irq_polarity(idx));
886         }
887         }
888
889         if (!first_notcon)
890                 apic_printk(APIC_VERBOSE," not connected.\n");
891 }
892
893 /*
894  * Set up the 8259A-master output pin as broadcast to all
895  * CPUs.
896  */
897 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
898 {
899         struct IO_APIC_route_entry entry;
900         unsigned long flags;
901
902         memset(&entry,0,sizeof(entry));
903
904         disable_8259A_irq(0);
905
906         /* mask LVT0 */
907         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
908
909         /*
910          * We use logical delivery to get the timer IRQ
911          * to the first CPU.
912          */
913         entry.dest_mode = INT_DEST_MODE;
914         entry.mask = 0;                                 /* unmask IRQ now */
915         entry.dest = cpu_mask_to_apicid(TARGET_CPUS);
916         entry.delivery_mode = INT_DELIVERY_MODE;
917         entry.polarity = 0;
918         entry.trigger = 0;
919         entry.vector = vector;
920
921         /*
922          * The timer IRQ doesn't have to know that behind the
923          * scene we have a 8259A-master in AEOI mode ...
924          */
925         set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
926
927         /*
928          * Add it to the IO-APIC irq-routing table:
929          */
930         spin_lock_irqsave(&ioapic_lock, flags);
931         io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
932         io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
933         spin_unlock_irqrestore(&ioapic_lock, flags);
934
935         enable_8259A_irq(0);
936 }
937
938 void __apicdebuginit print_IO_APIC(void)
939 {
940         int apic, i;
941         union IO_APIC_reg_00 reg_00;
942         union IO_APIC_reg_01 reg_01;
943         union IO_APIC_reg_02 reg_02;
944         unsigned long flags;
945
946         if (apic_verbosity == APIC_QUIET)
947                 return;
948
949         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
950         for (i = 0; i < nr_ioapics; i++)
951                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
952                        mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
953
954         /*
955          * We are a bit conservative about what we expect.  We have to
956          * know about every hardware change ASAP.
957          */
958         printk(KERN_INFO "testing the IO APIC.......................\n");
959
960         for (apic = 0; apic < nr_ioapics; apic++) {
961
962         spin_lock_irqsave(&ioapic_lock, flags);
963         reg_00.raw = io_apic_read(apic, 0);
964         reg_01.raw = io_apic_read(apic, 1);
965         if (reg_01.bits.version >= 0x10)
966                 reg_02.raw = io_apic_read(apic, 2);
967         spin_unlock_irqrestore(&ioapic_lock, flags);
968
969         printk("\n");
970         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
971         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
972         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
973
974         printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
975         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
976
977         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
978         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
979
980         if (reg_01.bits.version >= 0x10) {
981                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
982                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
983         }
984
985         printk(KERN_DEBUG ".... IRQ redirection table:\n");
986
987         printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
988                           " Stat Dmod Deli Vect:   \n");
989
990         for (i = 0; i <= reg_01.bits.entries; i++) {
991                 struct IO_APIC_route_entry entry;
992
993                 entry = ioapic_read_entry(apic, i);
994
995                 printk(KERN_DEBUG " %02x %03X ",
996                         i,
997                         entry.dest
998                 );
999
1000                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
1001                         entry.mask,
1002                         entry.trigger,
1003                         entry.irr,
1004                         entry.polarity,
1005                         entry.delivery_status,
1006                         entry.dest_mode,
1007                         entry.delivery_mode,
1008                         entry.vector
1009                 );
1010         }
1011         }
1012         printk(KERN_DEBUG "IRQ to pin mappings:\n");
1013         for (i = 0; i < NR_IRQS; i++) {
1014                 struct irq_pin_list *entry = irq_2_pin + i;
1015                 if (entry->pin < 0)
1016                         continue;
1017                 printk(KERN_DEBUG "IRQ%d ", i);
1018                 for (;;) {
1019                         printk("-> %d:%d", entry->apic, entry->pin);
1020                         if (!entry->next)
1021                                 break;
1022                         entry = irq_2_pin + entry->next;
1023                 }
1024                 printk("\n");
1025         }
1026
1027         printk(KERN_INFO ".................................... done.\n");
1028
1029         return;
1030 }
1031
1032 #if 0
1033
1034 static __apicdebuginit void print_APIC_bitfield (int base)
1035 {
1036         unsigned int v;
1037         int i, j;
1038
1039         if (apic_verbosity == APIC_QUIET)
1040                 return;
1041
1042         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1043         for (i = 0; i < 8; i++) {
1044                 v = apic_read(base + i*0x10);
1045                 for (j = 0; j < 32; j++) {
1046                         if (v & (1<<j))
1047                                 printk("1");
1048                         else
1049                                 printk("0");
1050                 }
1051                 printk("\n");
1052         }
1053 }
1054
1055 void __apicdebuginit print_local_APIC(void * dummy)
1056 {
1057         unsigned int v, ver, maxlvt;
1058
1059         if (apic_verbosity == APIC_QUIET)
1060                 return;
1061
1062         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1063                 smp_processor_id(), hard_smp_processor_id());
1064         v = apic_read(APIC_ID);
1065         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, GET_APIC_ID(v));
1066         v = apic_read(APIC_LVR);
1067         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1068         ver = GET_APIC_VERSION(v);
1069         maxlvt = get_maxlvt();
1070
1071         v = apic_read(APIC_TASKPRI);
1072         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1073
1074         v = apic_read(APIC_ARBPRI);
1075         printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1076                 v & APIC_ARBPRI_MASK);
1077         v = apic_read(APIC_PROCPRI);
1078         printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1079
1080         v = apic_read(APIC_EOI);
1081         printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1082         v = apic_read(APIC_RRR);
1083         printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1084         v = apic_read(APIC_LDR);
1085         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1086         v = apic_read(APIC_DFR);
1087         printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1088         v = apic_read(APIC_SPIV);
1089         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1090
1091         printk(KERN_DEBUG "... APIC ISR field:\n");
1092         print_APIC_bitfield(APIC_ISR);
1093         printk(KERN_DEBUG "... APIC TMR field:\n");
1094         print_APIC_bitfield(APIC_TMR);
1095         printk(KERN_DEBUG "... APIC IRR field:\n");
1096         print_APIC_bitfield(APIC_IRR);
1097
1098         v = apic_read(APIC_ESR);
1099         printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1100
1101         v = apic_read(APIC_ICR);
1102         printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1103         v = apic_read(APIC_ICR2);
1104         printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1105
1106         v = apic_read(APIC_LVTT);
1107         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1108
1109         if (maxlvt > 3) {                       /* PC is LVT#4. */
1110                 v = apic_read(APIC_LVTPC);
1111                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1112         }
1113         v = apic_read(APIC_LVT0);
1114         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1115         v = apic_read(APIC_LVT1);
1116         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1117
1118         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1119                 v = apic_read(APIC_LVTERR);
1120                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1121         }
1122
1123         v = apic_read(APIC_TMICT);
1124         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1125         v = apic_read(APIC_TMCCT);
1126         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1127         v = apic_read(APIC_TDCR);
1128         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1129         printk("\n");
1130 }
1131
1132 void print_all_local_APICs (void)
1133 {
1134         on_each_cpu(print_local_APIC, NULL, 1, 1);
1135 }
1136
1137 void __apicdebuginit print_PIC(void)
1138 {
1139         unsigned int v;
1140         unsigned long flags;
1141
1142         if (apic_verbosity == APIC_QUIET)
1143                 return;
1144
1145         printk(KERN_DEBUG "\nprinting PIC contents\n");
1146
1147         spin_lock_irqsave(&i8259A_lock, flags);
1148
1149         v = inb(0xa1) << 8 | inb(0x21);
1150         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1151
1152         v = inb(0xa0) << 8 | inb(0x20);
1153         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1154
1155         outb(0x0b,0xa0);
1156         outb(0x0b,0x20);
1157         v = inb(0xa0) << 8 | inb(0x20);
1158         outb(0x0a,0xa0);
1159         outb(0x0a,0x20);
1160
1161         spin_unlock_irqrestore(&i8259A_lock, flags);
1162
1163         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1164
1165         v = inb(0x4d1) << 8 | inb(0x4d0);
1166         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1167 }
1168
1169 #endif  /*  0  */
1170
1171 static void __init enable_IO_APIC(void)
1172 {
1173         union IO_APIC_reg_01 reg_01;
1174         int i8259_apic, i8259_pin;
1175         int i, apic;
1176         unsigned long flags;
1177
1178         for (i = 0; i < PIN_MAP_SIZE; i++) {
1179                 irq_2_pin[i].pin = -1;
1180                 irq_2_pin[i].next = 0;
1181         }
1182
1183         /*
1184          * The number of IO-APIC IRQ registers (== #pins):
1185          */
1186         for (apic = 0; apic < nr_ioapics; apic++) {
1187                 spin_lock_irqsave(&ioapic_lock, flags);
1188                 reg_01.raw = io_apic_read(apic, 1);
1189                 spin_unlock_irqrestore(&ioapic_lock, flags);
1190                 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1191         }
1192         for(apic = 0; apic < nr_ioapics; apic++) {
1193                 int pin;
1194                 /* See if any of the pins is in ExtINT mode */
1195                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1196                         struct IO_APIC_route_entry entry;
1197                         entry = ioapic_read_entry(apic, pin);
1198
1199                         /* If the interrupt line is enabled and in ExtInt mode
1200                          * I have found the pin where the i8259 is connected.
1201                          */
1202                         if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1203                                 ioapic_i8259.apic = apic;
1204                                 ioapic_i8259.pin  = pin;
1205                                 goto found_i8259;
1206                         }
1207                 }
1208         }
1209  found_i8259:
1210         /* Look to see what if the MP table has reported the ExtINT */
1211         i8259_pin  = find_isa_irq_pin(0, mp_ExtINT);
1212         i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1213         /* Trust the MP table if nothing is setup in the hardware */
1214         if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1215                 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1216                 ioapic_i8259.pin  = i8259_pin;
1217                 ioapic_i8259.apic = i8259_apic;
1218         }
1219         /* Complain if the MP table and the hardware disagree */
1220         if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1221                 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1222         {
1223                 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1224         }
1225
1226         /*
1227          * Do not trust the IO-APIC being empty at bootup
1228          */
1229         clear_IO_APIC();
1230 }
1231
1232 /*
1233  * Not an __init, needed by the reboot code
1234  */
1235 void disable_IO_APIC(void)
1236 {
1237         /*
1238          * Clear the IO-APIC before rebooting:
1239          */
1240         clear_IO_APIC();
1241
1242         /*
1243          * If the i8259 is routed through an IOAPIC
1244          * Put that IOAPIC in virtual wire mode
1245          * so legacy interrupts can be delivered.
1246          */
1247         if (ioapic_i8259.pin != -1) {
1248                 struct IO_APIC_route_entry entry;
1249
1250                 memset(&entry, 0, sizeof(entry));
1251                 entry.mask            = 0; /* Enabled */
1252                 entry.trigger         = 0; /* Edge */
1253                 entry.irr             = 0;
1254                 entry.polarity        = 0; /* High */
1255                 entry.delivery_status = 0;
1256                 entry.dest_mode       = 0; /* Physical */
1257                 entry.delivery_mode   = dest_ExtINT; /* ExtInt */
1258                 entry.vector          = 0;
1259                 entry.dest          = GET_APIC_ID(apic_read(APIC_ID));
1260
1261                 /*
1262                  * Add it to the IO-APIC irq-routing table:
1263                  */
1264                 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1265         }
1266
1267         disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1268 }
1269
1270 /*
1271  * There is a nasty bug in some older SMP boards, their mptable lies
1272  * about the timer IRQ. We do the following to work around the situation:
1273  *
1274  *      - timer IRQ defaults to IO-APIC IRQ
1275  *      - if this function detects that timer IRQs are defunct, then we fall
1276  *        back to ISA timer IRQs
1277  */
1278 static int __init timer_irq_works(void)
1279 {
1280         unsigned long t1 = jiffies;
1281
1282         local_irq_enable();
1283         /* Let ten ticks pass... */
1284         mdelay((10 * 1000) / HZ);
1285
1286         /*
1287          * Expect a few ticks at least, to be sure some possible
1288          * glue logic does not lock up after one or two first
1289          * ticks in a non-ExtINT mode.  Also the local APIC
1290          * might have cached one ExtINT interrupt.  Finally, at
1291          * least one tick may be lost due to delays.
1292          */
1293
1294         /* jiffies wrap? */
1295         if (jiffies - t1 > 4)
1296                 return 1;
1297         return 0;
1298 }
1299
1300 /*
1301  * In the SMP+IOAPIC case it might happen that there are an unspecified
1302  * number of pending IRQ events unhandled. These cases are very rare,
1303  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1304  * better to do it this way as thus we do not have to be aware of
1305  * 'pending' interrupts in the IRQ path, except at this point.
1306  */
1307 /*
1308  * Edge triggered needs to resend any interrupt
1309  * that was delayed but this is now handled in the device
1310  * independent code.
1311  */
1312
1313 /*
1314  * Starting up a edge-triggered IO-APIC interrupt is
1315  * nasty - we need to make sure that we get the edge.
1316  * If it is already asserted for some reason, we need
1317  * return 1 to indicate that is was pending.
1318  *
1319  * This is not complete - we should be able to fake
1320  * an edge even if it isn't on the 8259A...
1321  */
1322
1323 static unsigned int startup_ioapic_irq(unsigned int irq)
1324 {
1325         int was_pending = 0;
1326         unsigned long flags;
1327
1328         spin_lock_irqsave(&ioapic_lock, flags);
1329         if (irq < 16) {
1330                 disable_8259A_irq(irq);
1331                 if (i8259A_irq_pending(irq))
1332                         was_pending = 1;
1333         }
1334         __unmask_IO_APIC_irq(irq);
1335         spin_unlock_irqrestore(&ioapic_lock, flags);
1336
1337         return was_pending;
1338 }
1339
1340 static int ioapic_retrigger_irq(unsigned int irq)
1341 {
1342         struct irq_cfg *cfg = &irq_cfg[irq];
1343         cpumask_t mask;
1344         unsigned long flags;
1345
1346         spin_lock_irqsave(&vector_lock, flags);
1347         cpus_clear(mask);
1348         cpu_set(first_cpu(cfg->domain), mask);
1349
1350         send_IPI_mask(mask, cfg->vector);
1351         spin_unlock_irqrestore(&vector_lock, flags);
1352
1353         return 1;
1354 }
1355
1356 /*
1357  * Level and edge triggered IO-APIC interrupts need different handling,
1358  * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1359  * handled with the level-triggered descriptor, but that one has slightly
1360  * more overhead. Level-triggered interrupts cannot be handled with the
1361  * edge-triggered handler, without risking IRQ storms and other ugly
1362  * races.
1363  */
1364
1365 #ifdef CONFIG_SMP
1366 asmlinkage void smp_irq_move_cleanup_interrupt(void)
1367 {
1368         unsigned vector, me;
1369         ack_APIC_irq();
1370         exit_idle();
1371         irq_enter();
1372
1373         me = smp_processor_id();
1374         for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
1375                 unsigned int irq;
1376                 struct irq_desc *desc;
1377                 struct irq_cfg *cfg;
1378                 irq = __get_cpu_var(vector_irq)[vector];
1379                 if (irq >= NR_IRQS)
1380                         continue;
1381
1382                 desc = irq_desc + irq;
1383                 cfg = irq_cfg + irq;
1384                 spin_lock(&desc->lock);
1385                 if (!cfg->move_cleanup_count)
1386                         goto unlock;
1387
1388                 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain))
1389                         goto unlock;
1390
1391                 __get_cpu_var(vector_irq)[vector] = -1;
1392                 cfg->move_cleanup_count--;
1393 unlock:
1394                 spin_unlock(&desc->lock);
1395         }
1396
1397         irq_exit();
1398 }
1399
1400 static void irq_complete_move(unsigned int irq)
1401 {
1402         struct irq_cfg *cfg = irq_cfg + irq;
1403         unsigned vector, me;
1404
1405         if (likely(!cfg->move_in_progress))
1406                 return;
1407
1408         vector = ~get_irq_regs()->orig_rax;
1409         me = smp_processor_id();
1410         if ((vector == cfg->vector) && cpu_isset(me, cfg->domain)) {
1411                 cpumask_t cleanup_mask;
1412
1413                 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
1414                 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
1415                 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
1416                 cfg->move_in_progress = 0;
1417         }
1418 }
1419 #else
1420 static inline void irq_complete_move(unsigned int irq) {}
1421 #endif
1422
1423 static void ack_apic_edge(unsigned int irq)
1424 {
1425         irq_complete_move(irq);
1426         move_native_irq(irq);
1427         ack_APIC_irq();
1428 }
1429
1430 static void ack_apic_level(unsigned int irq)
1431 {
1432         int do_unmask_irq = 0;
1433
1434         irq_complete_move(irq);
1435 #if defined(CONFIG_GENERIC_PENDING_IRQ) || defined(CONFIG_IRQBALANCE)
1436         /* If we are moving the irq we need to mask it */
1437         if (unlikely(irq_desc[irq].status & IRQ_MOVE_PENDING)) {
1438                 do_unmask_irq = 1;
1439                 mask_IO_APIC_irq(irq);
1440         }
1441 #endif
1442
1443         /*
1444          * We must acknowledge the irq before we move it or the acknowledge will
1445          * not propagate properly.
1446          */
1447         ack_APIC_irq();
1448
1449         /* Now we can move and renable the irq */
1450         if (unlikely(do_unmask_irq)) {
1451                 /* Only migrate the irq if the ack has been received.
1452                  *
1453                  * On rare occasions the broadcast level triggered ack gets
1454                  * delayed going to ioapics, and if we reprogram the
1455                  * vector while Remote IRR is still set the irq will never
1456                  * fire again.
1457                  *
1458                  * To prevent this scenario we read the Remote IRR bit
1459                  * of the ioapic.  This has two effects.
1460                  * - On any sane system the read of the ioapic will
1461                  *   flush writes (and acks) going to the ioapic from
1462                  *   this cpu.
1463                  * - We get to see if the ACK has actually been delivered.
1464                  *
1465                  * Based on failed experiments of reprogramming the
1466                  * ioapic entry from outside of irq context starting
1467                  * with masking the ioapic entry and then polling until
1468                  * Remote IRR was clear before reprogramming the
1469                  * ioapic I don't trust the Remote IRR bit to be
1470                  * completey accurate.
1471                  *
1472                  * However there appears to be no other way to plug
1473                  * this race, so if the Remote IRR bit is not
1474                  * accurate and is causing problems then it is a hardware bug
1475                  * and you can go talk to the chipset vendor about it.
1476                  */
1477                 if (!io_apic_level_ack_pending(irq))
1478                         move_masked_irq(irq);
1479                 unmask_IO_APIC_irq(irq);
1480         }
1481 }
1482
1483 static struct irq_chip ioapic_chip __read_mostly = {
1484         .name           = "IO-APIC",
1485         .startup        = startup_ioapic_irq,
1486         .mask           = mask_IO_APIC_irq,
1487         .unmask         = unmask_IO_APIC_irq,
1488         .ack            = ack_apic_edge,
1489         .eoi            = ack_apic_level,
1490 #ifdef CONFIG_SMP
1491         .set_affinity   = set_ioapic_affinity_irq,
1492 #endif
1493         .retrigger      = ioapic_retrigger_irq,
1494 };
1495
1496 static inline void init_IO_APIC_traps(void)
1497 {
1498         int irq;
1499
1500         /*
1501          * NOTE! The local APIC isn't very good at handling
1502          * multiple interrupts at the same interrupt level.
1503          * As the interrupt level is determined by taking the
1504          * vector number and shifting that right by 4, we
1505          * want to spread these out a bit so that they don't
1506          * all fall in the same interrupt level.
1507          *
1508          * Also, we've got to be careful not to trash gate
1509          * 0x80, because int 0x80 is hm, kind of importantish. ;)
1510          */
1511         for (irq = 0; irq < NR_IRQS ; irq++) {
1512                 int tmp = irq;
1513                 if (IO_APIC_IRQ(tmp) && !irq_cfg[tmp].vector) {
1514                         /*
1515                          * Hmm.. We don't have an entry for this,
1516                          * so default to an old-fashioned 8259
1517                          * interrupt if we can..
1518                          */
1519                         if (irq < 16)
1520                                 make_8259A_irq(irq);
1521                         else
1522                                 /* Strange. Oh, well.. */
1523                                 irq_desc[irq].chip = &no_irq_chip;
1524                 }
1525         }
1526 }
1527
1528 static void enable_lapic_irq (unsigned int irq)
1529 {
1530         unsigned long v;
1531
1532         v = apic_read(APIC_LVT0);
1533         apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1534 }
1535
1536 static void disable_lapic_irq (unsigned int irq)
1537 {
1538         unsigned long v;
1539
1540         v = apic_read(APIC_LVT0);
1541         apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1542 }
1543
1544 static void ack_lapic_irq (unsigned int irq)
1545 {
1546         ack_APIC_irq();
1547 }
1548
1549 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1550
1551 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
1552         .name = "local-APIC",
1553         .typename = "local-APIC-edge",
1554         .startup = NULL, /* startup_irq() not used for IRQ0 */
1555         .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1556         .enable = enable_lapic_irq,
1557         .disable = disable_lapic_irq,
1558         .ack = ack_lapic_irq,
1559         .end = end_lapic_irq,
1560 };
1561
1562 static void setup_nmi (void)
1563 {
1564         /*
1565          * Dirty trick to enable the NMI watchdog ...
1566          * We put the 8259A master into AEOI mode and
1567          * unmask on all local APICs LVT0 as NMI.
1568          *
1569          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1570          * is from Maciej W. Rozycki - so we do not have to EOI from
1571          * the NMI handler or the timer interrupt.
1572          */ 
1573         printk(KERN_INFO "activating NMI Watchdog ...");
1574
1575         enable_NMI_through_LVT0(NULL);
1576
1577         printk(" done.\n");
1578 }
1579
1580 /*
1581  * This looks a bit hackish but it's about the only one way of sending
1582  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
1583  * not support the ExtINT mode, unfortunately.  We need to send these
1584  * cycles as some i82489DX-based boards have glue logic that keeps the
1585  * 8259A interrupt line asserted until INTA.  --macro
1586  */
1587 static inline void unlock_ExtINT_logic(void)
1588 {
1589         int apic, pin, i;
1590         struct IO_APIC_route_entry entry0, entry1;
1591         unsigned char save_control, save_freq_select;
1592         unsigned long flags;
1593
1594         pin  = find_isa_irq_pin(8, mp_INT);
1595         apic = find_isa_irq_apic(8, mp_INT);
1596         if (pin == -1)
1597                 return;
1598
1599         spin_lock_irqsave(&ioapic_lock, flags);
1600         *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1601         *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1602         spin_unlock_irqrestore(&ioapic_lock, flags);
1603         clear_IO_APIC_pin(apic, pin);
1604
1605         memset(&entry1, 0, sizeof(entry1));
1606
1607         entry1.dest_mode = 0;                   /* physical delivery */
1608         entry1.mask = 0;                        /* unmask IRQ now */
1609         entry1.dest = hard_smp_processor_id();
1610         entry1.delivery_mode = dest_ExtINT;
1611         entry1.polarity = entry0.polarity;
1612         entry1.trigger = 0;
1613         entry1.vector = 0;
1614
1615         spin_lock_irqsave(&ioapic_lock, flags);
1616         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1617         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1618         spin_unlock_irqrestore(&ioapic_lock, flags);
1619
1620         save_control = CMOS_READ(RTC_CONTROL);
1621         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1622         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1623                    RTC_FREQ_SELECT);
1624         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1625
1626         i = 100;
1627         while (i-- > 0) {
1628                 mdelay(10);
1629                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1630                         i -= 10;
1631         }
1632
1633         CMOS_WRITE(save_control, RTC_CONTROL);
1634         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1635         clear_IO_APIC_pin(apic, pin);
1636
1637         spin_lock_irqsave(&ioapic_lock, flags);
1638         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1639         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1640         spin_unlock_irqrestore(&ioapic_lock, flags);
1641 }
1642
1643 /*
1644  * This code may look a bit paranoid, but it's supposed to cooperate with
1645  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
1646  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
1647  * fanatically on his truly buggy board.
1648  *
1649  * FIXME: really need to revamp this for modern platforms only.
1650  */
1651 static inline void check_timer(void)
1652 {
1653         struct irq_cfg *cfg = irq_cfg + 0;
1654         int apic1, pin1, apic2, pin2;
1655
1656         /*
1657          * get/set the timer IRQ vector:
1658          */
1659         disable_8259A_irq(0);
1660         assign_irq_vector(0, TARGET_CPUS);
1661
1662         /*
1663          * Subtle, code in do_timer_interrupt() expects an AEOI
1664          * mode for the 8259A whenever interrupts are routed
1665          * through I/O APICs.  Also IRQ0 has to be enabled in
1666          * the 8259A which implies the virtual wire has to be
1667          * disabled in the local APIC.
1668          */
1669         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1670         init_8259A(1);
1671         if (timer_over_8254 > 0)
1672                 enable_8259A_irq(0);
1673
1674         pin1  = find_isa_irq_pin(0, mp_INT);
1675         apic1 = find_isa_irq_apic(0, mp_INT);
1676         pin2  = ioapic_i8259.pin;
1677         apic2 = ioapic_i8259.apic;
1678
1679         apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
1680                 cfg->vector, apic1, pin1, apic2, pin2);
1681
1682         if (pin1 != -1) {
1683                 /*
1684                  * Ok, does IRQ0 through the IOAPIC work?
1685                  */
1686                 unmask_IO_APIC_irq(0);
1687                 if (!no_timer_check && timer_irq_works()) {
1688                         nmi_watchdog_default();
1689                         if (nmi_watchdog == NMI_IO_APIC) {
1690                                 disable_8259A_irq(0);
1691                                 setup_nmi();
1692                                 enable_8259A_irq(0);
1693                         }
1694                         if (disable_timer_pin_1 > 0)
1695                                 clear_IO_APIC_pin(0, pin1);
1696                         return;
1697                 }
1698                 clear_IO_APIC_pin(apic1, pin1);
1699                 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not "
1700                                 "connected to IO-APIC\n");
1701         }
1702
1703         apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) "
1704                                 "through the 8259A ... ");
1705         if (pin2 != -1) {
1706                 apic_printk(APIC_VERBOSE,"\n..... (found apic %d pin %d) ...",
1707                         apic2, pin2);
1708                 /*
1709                  * legacy devices should be connected to IO APIC #0
1710                  */
1711                 setup_ExtINT_IRQ0_pin(apic2, pin2, cfg->vector);
1712                 if (timer_irq_works()) {
1713                         apic_printk(APIC_VERBOSE," works.\n");
1714                         nmi_watchdog_default();
1715                         if (nmi_watchdog == NMI_IO_APIC) {
1716                                 setup_nmi();
1717                         }
1718                         return;
1719                 }
1720                 /*
1721                  * Cleanup, just in case ...
1722                  */
1723                 clear_IO_APIC_pin(apic2, pin2);
1724         }
1725         apic_printk(APIC_VERBOSE," failed.\n");
1726
1727         if (nmi_watchdog == NMI_IO_APIC) {
1728                 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1729                 nmi_watchdog = 0;
1730         }
1731
1732         apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1733
1734         disable_8259A_irq(0);
1735         irq_desc[0].chip = &lapic_irq_type;
1736         apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector);     /* Fixed mode */
1737         enable_8259A_irq(0);
1738
1739         if (timer_irq_works()) {
1740                 apic_printk(APIC_VERBOSE," works.\n");
1741                 return;
1742         }
1743         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
1744         apic_printk(APIC_VERBOSE," failed.\n");
1745
1746         apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1747
1748         init_8259A(0);
1749         make_8259A_irq(0);
1750         apic_write(APIC_LVT0, APIC_DM_EXTINT);
1751
1752         unlock_ExtINT_logic();
1753
1754         if (timer_irq_works()) {
1755                 apic_printk(APIC_VERBOSE," works.\n");
1756                 return;
1757         }
1758         apic_printk(APIC_VERBOSE," failed :(.\n");
1759         panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1760 }
1761
1762 static int __init notimercheck(char *s)
1763 {
1764         no_timer_check = 1;
1765         return 1;
1766 }
1767 __setup("no_timer_check", notimercheck);
1768
1769 /*
1770  *
1771  * IRQ's that are handled by the PIC in the MPS IOAPIC case.
1772  * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1773  *   Linux doesn't really care, as it's not actually used
1774  *   for any interrupt handling anyway.
1775  */
1776 #define PIC_IRQS        (1<<2)
1777
1778 void __init setup_IO_APIC(void)
1779 {
1780         enable_IO_APIC();
1781
1782         if (acpi_ioapic)
1783                 io_apic_irqs = ~0;      /* all IRQs go through IOAPIC */
1784         else
1785                 io_apic_irqs = ~PIC_IRQS;
1786
1787         apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
1788
1789         sync_Arb_IDs();
1790         setup_IO_APIC_irqs();
1791         init_IO_APIC_traps();
1792         check_timer();
1793         if (!acpi_ioapic)
1794                 print_IO_APIC();
1795 }
1796
1797 struct sysfs_ioapic_data {
1798         struct sys_device dev;
1799         struct IO_APIC_route_entry entry[0];
1800 };
1801 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1802
1803 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1804 {
1805         struct IO_APIC_route_entry *entry;
1806         struct sysfs_ioapic_data *data;
1807         int i;
1808
1809         data = container_of(dev, struct sysfs_ioapic_data, dev);
1810         entry = data->entry;
1811         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
1812                 *entry = ioapic_read_entry(dev->id, i);
1813
1814         return 0;
1815 }
1816
1817 static int ioapic_resume(struct sys_device *dev)
1818 {
1819         struct IO_APIC_route_entry *entry;
1820         struct sysfs_ioapic_data *data;
1821         unsigned long flags;
1822         union IO_APIC_reg_00 reg_00;
1823         int i;
1824
1825         data = container_of(dev, struct sysfs_ioapic_data, dev);
1826         entry = data->entry;
1827
1828         spin_lock_irqsave(&ioapic_lock, flags);
1829         reg_00.raw = io_apic_read(dev->id, 0);
1830         if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
1831                 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
1832                 io_apic_write(dev->id, 0, reg_00.raw);
1833         }
1834         spin_unlock_irqrestore(&ioapic_lock, flags);
1835         for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
1836                 ioapic_write_entry(dev->id, i, entry[i]);
1837
1838         return 0;
1839 }
1840
1841 static struct sysdev_class ioapic_sysdev_class = {
1842         set_kset_name("ioapic"),
1843         .suspend = ioapic_suspend,
1844         .resume = ioapic_resume,
1845 };
1846
1847 static int __init ioapic_init_sysfs(void)
1848 {
1849         struct sys_device * dev;
1850         int i, size, error = 0;
1851
1852         error = sysdev_class_register(&ioapic_sysdev_class);
1853         if (error)
1854                 return error;
1855
1856         for (i = 0; i < nr_ioapics; i++ ) {
1857                 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
1858                         * sizeof(struct IO_APIC_route_entry);
1859                 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
1860                 if (!mp_ioapic_data[i]) {
1861                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1862                         continue;
1863                 }
1864                 memset(mp_ioapic_data[i], 0, size);
1865                 dev = &mp_ioapic_data[i]->dev;
1866                 dev->id = i;
1867                 dev->cls = &ioapic_sysdev_class;
1868                 error = sysdev_register(dev);
1869                 if (error) {
1870                         kfree(mp_ioapic_data[i]);
1871                         mp_ioapic_data[i] = NULL;
1872                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1873                         continue;
1874                 }
1875         }
1876
1877         return 0;
1878 }
1879
1880 device_initcall(ioapic_init_sysfs);
1881
1882 /*
1883  * Dynamic irq allocate and deallocation
1884  */
1885 int create_irq(void)
1886 {
1887         /* Allocate an unused irq */
1888         int irq;
1889         int new;
1890         unsigned long flags;
1891
1892         irq = -ENOSPC;
1893         spin_lock_irqsave(&vector_lock, flags);
1894         for (new = (NR_IRQS - 1); new >= 0; new--) {
1895                 if (platform_legacy_irq(new))
1896                         continue;
1897                 if (irq_cfg[new].vector != 0)
1898                         continue;
1899                 if (__assign_irq_vector(new, TARGET_CPUS) == 0)
1900                         irq = new;
1901                 break;
1902         }
1903         spin_unlock_irqrestore(&vector_lock, flags);
1904
1905         if (irq >= 0) {
1906                 dynamic_irq_init(irq);
1907         }
1908         return irq;
1909 }
1910
1911 void destroy_irq(unsigned int irq)
1912 {
1913         unsigned long flags;
1914
1915         dynamic_irq_cleanup(irq);
1916
1917         spin_lock_irqsave(&vector_lock, flags);
1918         __clear_irq_vector(irq);
1919         spin_unlock_irqrestore(&vector_lock, flags);
1920 }
1921
1922 /*
1923  * MSI mesage composition
1924  */
1925 #ifdef CONFIG_PCI_MSI
1926 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
1927 {
1928         struct irq_cfg *cfg = irq_cfg + irq;
1929         int err;
1930         unsigned dest;
1931         cpumask_t tmp;
1932
1933         tmp = TARGET_CPUS;
1934         err = assign_irq_vector(irq, tmp);
1935         if (!err) {
1936                 cpus_and(tmp, cfg->domain, tmp);
1937                 dest = cpu_mask_to_apicid(tmp);
1938
1939                 msg->address_hi = MSI_ADDR_BASE_HI;
1940                 msg->address_lo =
1941                         MSI_ADDR_BASE_LO |
1942                         ((INT_DEST_MODE == 0) ?
1943                                 MSI_ADDR_DEST_MODE_PHYSICAL:
1944                                 MSI_ADDR_DEST_MODE_LOGICAL) |
1945                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1946                                 MSI_ADDR_REDIRECTION_CPU:
1947                                 MSI_ADDR_REDIRECTION_LOWPRI) |
1948                         MSI_ADDR_DEST_ID(dest);
1949
1950                 msg->data =
1951                         MSI_DATA_TRIGGER_EDGE |
1952                         MSI_DATA_LEVEL_ASSERT |
1953                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1954                                 MSI_DATA_DELIVERY_FIXED:
1955                                 MSI_DATA_DELIVERY_LOWPRI) |
1956                         MSI_DATA_VECTOR(cfg->vector);
1957         }
1958         return err;
1959 }
1960
1961 #ifdef CONFIG_SMP
1962 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
1963 {
1964         struct irq_cfg *cfg = irq_cfg + irq;
1965         struct msi_msg msg;
1966         unsigned int dest;
1967         cpumask_t tmp;
1968
1969         cpus_and(tmp, mask, cpu_online_map);
1970         if (cpus_empty(tmp))
1971                 return;
1972
1973         if (assign_irq_vector(irq, mask))
1974                 return;
1975
1976         cpus_and(tmp, cfg->domain, mask);
1977         dest = cpu_mask_to_apicid(tmp);
1978
1979         read_msi_msg(irq, &msg);
1980
1981         msg.data &= ~MSI_DATA_VECTOR_MASK;
1982         msg.data |= MSI_DATA_VECTOR(cfg->vector);
1983         msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
1984         msg.address_lo |= MSI_ADDR_DEST_ID(dest);
1985
1986         write_msi_msg(irq, &msg);
1987         irq_desc[irq].affinity = mask;
1988 }
1989 #endif /* CONFIG_SMP */
1990
1991 /*
1992  * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
1993  * which implement the MSI or MSI-X Capability Structure.
1994  */
1995 static struct irq_chip msi_chip = {
1996         .name           = "PCI-MSI",
1997         .unmask         = unmask_msi_irq,
1998         .mask           = mask_msi_irq,
1999         .ack            = ack_apic_edge,
2000 #ifdef CONFIG_SMP
2001         .set_affinity   = set_msi_irq_affinity,
2002 #endif
2003         .retrigger      = ioapic_retrigger_irq,
2004 };
2005
2006 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
2007 {
2008         struct msi_msg msg;
2009         int irq, ret;
2010         irq = create_irq();
2011         if (irq < 0)
2012                 return irq;
2013
2014         ret = msi_compose_msg(dev, irq, &msg);
2015         if (ret < 0) {
2016                 destroy_irq(irq);
2017                 return ret;
2018         }
2019
2020         set_irq_msi(irq, desc);
2021         write_msi_msg(irq, &msg);
2022
2023         set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
2024
2025         return 0;
2026 }
2027
2028 void arch_teardown_msi_irq(unsigned int irq)
2029 {
2030         destroy_irq(irq);
2031 }
2032
2033 #endif /* CONFIG_PCI_MSI */
2034
2035 /*
2036  * Hypertransport interrupt support
2037  */
2038 #ifdef CONFIG_HT_IRQ
2039
2040 #ifdef CONFIG_SMP
2041
2042 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
2043 {
2044         struct ht_irq_msg msg;
2045         fetch_ht_irq_msg(irq, &msg);
2046
2047         msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
2048         msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
2049
2050         msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
2051         msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
2052
2053         write_ht_irq_msg(irq, &msg);
2054 }
2055
2056 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
2057 {
2058         struct irq_cfg *cfg = irq_cfg + irq;
2059         unsigned int dest;
2060         cpumask_t tmp;
2061
2062         cpus_and(tmp, mask, cpu_online_map);
2063         if (cpus_empty(tmp))
2064                 return;
2065
2066         if (assign_irq_vector(irq, mask))
2067                 return;
2068
2069         cpus_and(tmp, cfg->domain, mask);
2070         dest = cpu_mask_to_apicid(tmp);
2071
2072         target_ht_irq(irq, dest, cfg->vector);
2073         irq_desc[irq].affinity = mask;
2074 }
2075 #endif
2076
2077 static struct irq_chip ht_irq_chip = {
2078         .name           = "PCI-HT",
2079         .mask           = mask_ht_irq,
2080         .unmask         = unmask_ht_irq,
2081         .ack            = ack_apic_edge,
2082 #ifdef CONFIG_SMP
2083         .set_affinity   = set_ht_irq_affinity,
2084 #endif
2085         .retrigger      = ioapic_retrigger_irq,
2086 };
2087
2088 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2089 {
2090         struct irq_cfg *cfg = irq_cfg + irq;
2091         int err;
2092         cpumask_t tmp;
2093
2094         tmp = TARGET_CPUS;
2095         err = assign_irq_vector(irq, tmp);
2096         if (!err) {
2097                 struct ht_irq_msg msg;
2098                 unsigned dest;
2099
2100                 cpus_and(tmp, cfg->domain, tmp);
2101                 dest = cpu_mask_to_apicid(tmp);
2102
2103                 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
2104
2105                 msg.address_lo =
2106                         HT_IRQ_LOW_BASE |
2107                         HT_IRQ_LOW_DEST_ID(dest) |
2108                         HT_IRQ_LOW_VECTOR(cfg->vector) |
2109                         ((INT_DEST_MODE == 0) ?
2110                                 HT_IRQ_LOW_DM_PHYSICAL :
2111                                 HT_IRQ_LOW_DM_LOGICAL) |
2112                         HT_IRQ_LOW_RQEOI_EDGE |
2113                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2114                                 HT_IRQ_LOW_MT_FIXED :
2115                                 HT_IRQ_LOW_MT_ARBITRATED) |
2116                         HT_IRQ_LOW_IRQ_MASKED;
2117
2118                 write_ht_irq_msg(irq, &msg);
2119
2120                 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2121                                               handle_edge_irq, "edge");
2122         }
2123         return err;
2124 }
2125 #endif /* CONFIG_HT_IRQ */
2126
2127 /* --------------------------------------------------------------------------
2128                           ACPI-based IOAPIC Configuration
2129    -------------------------------------------------------------------------- */
2130
2131 #ifdef CONFIG_ACPI
2132
2133 #define IO_APIC_MAX_ID          0xFE
2134
2135 int __init io_apic_get_redir_entries (int ioapic)
2136 {
2137         union IO_APIC_reg_01    reg_01;
2138         unsigned long flags;
2139
2140         spin_lock_irqsave(&ioapic_lock, flags);
2141         reg_01.raw = io_apic_read(ioapic, 1);
2142         spin_unlock_irqrestore(&ioapic_lock, flags);
2143
2144         return reg_01.bits.entries;
2145 }
2146
2147
2148 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
2149 {
2150         if (!IO_APIC_IRQ(irq)) {
2151                 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2152                         ioapic);
2153                 return -EINVAL;
2154         }
2155
2156         /*
2157          * IRQs < 16 are already in the irq_2_pin[] map
2158          */
2159         if (irq >= 16)
2160                 add_pin_to_irq(irq, ioapic, pin);
2161
2162         setup_IO_APIC_irq(ioapic, pin, irq, triggering, polarity);
2163
2164         return 0;
2165 }
2166
2167 #endif /* CONFIG_ACPI */
2168
2169
2170 /*
2171  * This function currently is only a helper for the i386 smp boot process where
2172  * we need to reprogram the ioredtbls to cater for the cpus which have come online
2173  * so mask in all cases should simply be TARGET_CPUS
2174  */
2175 #ifdef CONFIG_SMP
2176 void __init setup_ioapic_dest(void)
2177 {
2178         int pin, ioapic, irq, irq_entry;
2179
2180         if (skip_ioapic_setup == 1)
2181                 return;
2182
2183         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
2184                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
2185                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2186                         if (irq_entry == -1)
2187                                 continue;
2188                         irq = pin_2_irq(irq_entry, ioapic, pin);
2189
2190                         /* setup_IO_APIC_irqs could fail to get vector for some device
2191                          * when you have too many devices, because at that time only boot
2192                          * cpu is online.
2193                          */
2194                         if (!irq_cfg[irq].vector)
2195                                 setup_IO_APIC_irq(ioapic, pin, irq,
2196                                                   irq_trigger(irq_entry),
2197                                                   irq_polarity(irq_entry));
2198                         else
2199                                 set_ioapic_affinity_irq(irq, TARGET_CPUS);
2200                 }
2201
2202         }
2203 }
2204 #endif