afc59b2e7e0281ed0fea7c47cf4f99c108e96d54
[linux-2.6.git] / arch / x86 / kvm / lapic.c
1
2 /*
3  * Local APIC virtualization
4  *
5  * Copyright (C) 2006 Qumranet, Inc.
6  * Copyright (C) 2007 Novell
7  * Copyright (C) 2007 Intel
8  *
9  * Authors:
10  *   Dor Laor <dor.laor@qumranet.com>
11  *   Gregory Haskins <ghaskins@novell.com>
12  *   Yaozu (Eddie) Dong <eddie.dong@intel.com>
13  *
14  * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
15  *
16  * This work is licensed under the terms of the GNU GPL, version 2.  See
17  * the COPYING file in the top-level directory.
18  */
19
20 #include <linux/kvm_host.h>
21 #include <linux/kvm.h>
22 #include <linux/mm.h>
23 #include <linux/highmem.h>
24 #include <linux/smp.h>
25 #include <linux/hrtimer.h>
26 #include <linux/io.h>
27 #include <linux/module.h>
28 #include <linux/math64.h>
29 #include <asm/processor.h>
30 #include <asm/msr.h>
31 #include <asm/page.h>
32 #include <asm/current.h>
33 #include <asm/apicdef.h>
34 #include <asm/atomic.h>
35 #include "kvm_cache_regs.h"
36 #include "irq.h"
37
38 #ifndef CONFIG_X86_64
39 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
40 #else
41 #define mod_64(x, y) ((x) % (y))
42 #endif
43
44 #define PRId64 "d"
45 #define PRIx64 "llx"
46 #define PRIu64 "u"
47 #define PRIo64 "o"
48
49 #define APIC_BUS_CYCLE_NS 1
50
51 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
52 #define apic_debug(fmt, arg...)
53
54 #define APIC_LVT_NUM                    6
55 /* 14 is the version for Xeon and Pentium 8.4.8*/
56 #define APIC_VERSION                    (0x14UL | ((APIC_LVT_NUM - 1) << 16))
57 #define LAPIC_MMIO_LENGTH               (1 << 12)
58 /* followed define is not in apicdef.h */
59 #define APIC_SHORT_MASK                 0xc0000
60 #define APIC_DEST_NOSHORT               0x0
61 #define APIC_DEST_MASK                  0x800
62 #define MAX_APIC_VECTOR                 256
63
64 #define VEC_POS(v) ((v) & (32 - 1))
65 #define REG_POS(v) (((v) >> 5) << 4)
66
67 static inline u32 apic_get_reg(struct kvm_lapic *apic, int reg_off)
68 {
69         return *((u32 *) (apic->regs + reg_off));
70 }
71
72 static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
73 {
74         *((u32 *) (apic->regs + reg_off)) = val;
75 }
76
77 static inline int apic_test_and_set_vector(int vec, void *bitmap)
78 {
79         return test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
80 }
81
82 static inline int apic_test_and_clear_vector(int vec, void *bitmap)
83 {
84         return test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
85 }
86
87 static inline void apic_set_vector(int vec, void *bitmap)
88 {
89         set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
90 }
91
92 static inline void apic_clear_vector(int vec, void *bitmap)
93 {
94         clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
95 }
96
97 static inline int apic_hw_enabled(struct kvm_lapic *apic)
98 {
99         return (apic)->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;
100 }
101
102 static inline int  apic_sw_enabled(struct kvm_lapic *apic)
103 {
104         return apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_APIC_ENABLED;
105 }
106
107 static inline int apic_enabled(struct kvm_lapic *apic)
108 {
109         return apic_sw_enabled(apic) && apic_hw_enabled(apic);
110 }
111
112 #define LVT_MASK        \
113         (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
114
115 #define LINT_MASK       \
116         (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
117          APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
118
119 static inline int kvm_apic_id(struct kvm_lapic *apic)
120 {
121         return (apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
122 }
123
124 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
125 {
126         return !(apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
127 }
128
129 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
130 {
131         return apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
132 }
133
134 static inline int apic_lvtt_period(struct kvm_lapic *apic)
135 {
136         return apic_get_reg(apic, APIC_LVTT) & APIC_LVT_TIMER_PERIODIC;
137 }
138
139 static inline int apic_lvt_nmi_mode(u32 lvt_val)
140 {
141         return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
142 }
143
144 static unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
145         LVT_MASK | APIC_LVT_TIMER_PERIODIC,     /* LVTT */
146         LVT_MASK | APIC_MODE_MASK,      /* LVTTHMR */
147         LVT_MASK | APIC_MODE_MASK,      /* LVTPC */
148         LINT_MASK, LINT_MASK,   /* LVT0-1 */
149         LVT_MASK                /* LVTERR */
150 };
151
152 static int find_highest_vector(void *bitmap)
153 {
154         u32 *word = bitmap;
155         int word_offset = MAX_APIC_VECTOR >> 5;
156
157         while ((word_offset != 0) && (word[(--word_offset) << 2] == 0))
158                 continue;
159
160         if (likely(!word_offset && !word[0]))
161                 return -1;
162         else
163                 return fls(word[word_offset << 2]) - 1 + (word_offset << 5);
164 }
165
166 static inline int apic_test_and_set_irr(int vec, struct kvm_lapic *apic)
167 {
168         return apic_test_and_set_vector(vec, apic->regs + APIC_IRR);
169 }
170
171 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
172 {
173         apic_clear_vector(vec, apic->regs + APIC_IRR);
174 }
175
176 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
177 {
178         int result;
179
180         result = find_highest_vector(apic->regs + APIC_IRR);
181         ASSERT(result == -1 || result >= 16);
182
183         return result;
184 }
185
186 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
187 {
188         struct kvm_lapic *apic = vcpu->arch.apic;
189         int highest_irr;
190
191         if (!apic)
192                 return 0;
193         highest_irr = apic_find_highest_irr(apic);
194
195         return highest_irr;
196 }
197 EXPORT_SYMBOL_GPL(kvm_lapic_find_highest_irr);
198
199 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, u8 vec, u8 trig)
200 {
201         struct kvm_lapic *apic = vcpu->arch.apic;
202
203         if (!apic_test_and_set_irr(vec, apic)) {
204                 /* a new pending irq is set in IRR */
205                 if (trig)
206                         apic_set_vector(vec, apic->regs + APIC_TMR);
207                 else
208                         apic_clear_vector(vec, apic->regs + APIC_TMR);
209                 kvm_vcpu_kick(apic->vcpu);
210                 return 1;
211         }
212         return 0;
213 }
214
215 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
216 {
217         int result;
218
219         result = find_highest_vector(apic->regs + APIC_ISR);
220         ASSERT(result == -1 || result >= 16);
221
222         return result;
223 }
224
225 static void apic_update_ppr(struct kvm_lapic *apic)
226 {
227         u32 tpr, isrv, ppr;
228         int isr;
229
230         tpr = apic_get_reg(apic, APIC_TASKPRI);
231         isr = apic_find_highest_isr(apic);
232         isrv = (isr != -1) ? isr : 0;
233
234         if ((tpr & 0xf0) >= (isrv & 0xf0))
235                 ppr = tpr & 0xff;
236         else
237                 ppr = isrv & 0xf0;
238
239         apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
240                    apic, ppr, isr, isrv);
241
242         apic_set_reg(apic, APIC_PROCPRI, ppr);
243 }
244
245 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
246 {
247         apic_set_reg(apic, APIC_TASKPRI, tpr);
248         apic_update_ppr(apic);
249 }
250
251 int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest)
252 {
253         return kvm_apic_id(apic) == dest;
254 }
255
256 int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda)
257 {
258         int result = 0;
259         u8 logical_id;
260
261         logical_id = GET_APIC_LOGICAL_ID(apic_get_reg(apic, APIC_LDR));
262
263         switch (apic_get_reg(apic, APIC_DFR)) {
264         case APIC_DFR_FLAT:
265                 if (logical_id & mda)
266                         result = 1;
267                 break;
268         case APIC_DFR_CLUSTER:
269                 if (((logical_id >> 4) == (mda >> 0x4))
270                     && (logical_id & mda & 0xf))
271                         result = 1;
272                 break;
273         default:
274                 printk(KERN_WARNING "Bad DFR vcpu %d: %08x\n",
275                        apic->vcpu->vcpu_id, apic_get_reg(apic, APIC_DFR));
276                 break;
277         }
278
279         return result;
280 }
281
282 static int apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
283                            int short_hand, int dest, int dest_mode)
284 {
285         int result = 0;
286         struct kvm_lapic *target = vcpu->arch.apic;
287
288         apic_debug("target %p, source %p, dest 0x%x, "
289                    "dest_mode 0x%x, short_hand 0x%x",
290                    target, source, dest, dest_mode, short_hand);
291
292         ASSERT(!target);
293         switch (short_hand) {
294         case APIC_DEST_NOSHORT:
295                 if (dest_mode == 0) {
296                         /* Physical mode. */
297                         if ((dest == 0xFF) || (dest == kvm_apic_id(target)))
298                                 result = 1;
299                 } else
300                         /* Logical mode. */
301                         result = kvm_apic_match_logical_addr(target, dest);
302                 break;
303         case APIC_DEST_SELF:
304                 if (target == source)
305                         result = 1;
306                 break;
307         case APIC_DEST_ALLINC:
308                 result = 1;
309                 break;
310         case APIC_DEST_ALLBUT:
311                 if (target != source)
312                         result = 1;
313                 break;
314         default:
315                 printk(KERN_WARNING "Bad dest shorthand value %x\n",
316                        short_hand);
317                 break;
318         }
319
320         return result;
321 }
322
323 /*
324  * Add a pending IRQ into lapic.
325  * Return 1 if successfully added and 0 if discarded.
326  */
327 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
328                              int vector, int level, int trig_mode)
329 {
330         int orig_irr, result = 0;
331         struct kvm_vcpu *vcpu = apic->vcpu;
332
333         switch (delivery_mode) {
334         case APIC_DM_FIXED:
335         case APIC_DM_LOWEST:
336                 /* FIXME add logic for vcpu on reset */
337                 if (unlikely(!apic_enabled(apic)))
338                         break;
339
340                 orig_irr = apic_test_and_set_irr(vector, apic);
341                 if (orig_irr && trig_mode) {
342                         apic_debug("level trig mode repeatedly for vector %d",
343                                    vector);
344                         break;
345                 }
346
347                 if (trig_mode) {
348                         apic_debug("level trig mode for vector %d", vector);
349                         apic_set_vector(vector, apic->regs + APIC_TMR);
350                 } else
351                         apic_clear_vector(vector, apic->regs + APIC_TMR);
352
353                 kvm_vcpu_kick(vcpu);
354
355                 result = (orig_irr == 0);
356                 break;
357
358         case APIC_DM_REMRD:
359                 printk(KERN_DEBUG "Ignoring delivery mode 3\n");
360                 break;
361
362         case APIC_DM_SMI:
363                 printk(KERN_DEBUG "Ignoring guest SMI\n");
364                 break;
365
366         case APIC_DM_NMI:
367                 kvm_inject_nmi(vcpu);
368                 kvm_vcpu_kick(vcpu);
369                 break;
370
371         case APIC_DM_INIT:
372                 if (level) {
373                         if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
374                                 printk(KERN_DEBUG
375                                        "INIT on a runnable vcpu %d\n",
376                                        vcpu->vcpu_id);
377                         vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
378                         kvm_vcpu_kick(vcpu);
379                 } else {
380                         apic_debug("Ignoring de-assert INIT to vcpu %d\n",
381                                    vcpu->vcpu_id);
382                 }
383                 break;
384
385         case APIC_DM_STARTUP:
386                 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
387                            vcpu->vcpu_id, vector);
388                 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
389                         vcpu->arch.sipi_vector = vector;
390                         vcpu->arch.mp_state = KVM_MP_STATE_SIPI_RECEIVED;
391                         kvm_vcpu_kick(vcpu);
392                 }
393                 break;
394
395         case APIC_DM_EXTINT:
396                 /*
397                  * Should only be called by kvm_apic_local_deliver() with LVT0,
398                  * before NMI watchdog was enabled. Already handled by
399                  * kvm_apic_accept_pic_intr().
400                  */
401                 break;
402
403         default:
404                 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
405                        delivery_mode);
406                 break;
407         }
408         return result;
409 }
410
411 static struct kvm_lapic *kvm_apic_round_robin(struct kvm *kvm, u8 vector,
412                                        unsigned long *bitmap)
413 {
414         int last;
415         int next;
416         struct kvm_lapic *apic = NULL;
417
418         last = kvm->arch.round_robin_prev_vcpu;
419         next = last;
420
421         do {
422                 if (++next == KVM_MAX_VCPUS)
423                         next = 0;
424                 if (kvm->vcpus[next] == NULL || !test_bit(next, bitmap))
425                         continue;
426                 apic = kvm->vcpus[next]->arch.apic;
427                 if (apic && apic_enabled(apic))
428                         break;
429                 apic = NULL;
430         } while (next != last);
431         kvm->arch.round_robin_prev_vcpu = next;
432
433         if (!apic)
434                 printk(KERN_DEBUG "vcpu not ready for apic_round_robin\n");
435
436         return apic;
437 }
438
439 struct kvm_vcpu *kvm_get_lowest_prio_vcpu(struct kvm *kvm, u8 vector,
440                 unsigned long *bitmap)
441 {
442         struct kvm_lapic *apic;
443
444         apic = kvm_apic_round_robin(kvm, vector, bitmap);
445         if (apic)
446                 return apic->vcpu;
447         return NULL;
448 }
449
450 static void apic_set_eoi(struct kvm_lapic *apic)
451 {
452         int vector = apic_find_highest_isr(apic);
453         int trigger_mode;
454         /*
455          * Not every write EOI will has corresponding ISR,
456          * one example is when Kernel check timer on setup_IO_APIC
457          */
458         if (vector == -1)
459                 return;
460
461         apic_clear_vector(vector, apic->regs + APIC_ISR);
462         apic_update_ppr(apic);
463
464         if (apic_test_and_clear_vector(vector, apic->regs + APIC_TMR))
465                 trigger_mode = IOAPIC_LEVEL_TRIG;
466         else
467                 trigger_mode = IOAPIC_EDGE_TRIG;
468         kvm_ioapic_update_eoi(apic->vcpu->kvm, vector, trigger_mode);
469 }
470
471 static void apic_send_ipi(struct kvm_lapic *apic)
472 {
473         u32 icr_low = apic_get_reg(apic, APIC_ICR);
474         u32 icr_high = apic_get_reg(apic, APIC_ICR2);
475
476         unsigned int dest = GET_APIC_DEST_FIELD(icr_high);
477         unsigned int short_hand = icr_low & APIC_SHORT_MASK;
478         unsigned int trig_mode = icr_low & APIC_INT_LEVELTRIG;
479         unsigned int level = icr_low & APIC_INT_ASSERT;
480         unsigned int dest_mode = icr_low & APIC_DEST_MASK;
481         unsigned int delivery_mode = icr_low & APIC_MODE_MASK;
482         unsigned int vector = icr_low & APIC_VECTOR_MASK;
483
484         struct kvm_vcpu *target;
485         struct kvm_vcpu *vcpu;
486         DECLARE_BITMAP(lpr_map, KVM_MAX_VCPUS);
487         int i;
488
489         bitmap_zero(lpr_map, KVM_MAX_VCPUS);
490         apic_debug("icr_high 0x%x, icr_low 0x%x, "
491                    "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
492                    "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
493                    icr_high, icr_low, short_hand, dest,
494                    trig_mode, level, dest_mode, delivery_mode, vector);
495
496         for (i = 0; i < KVM_MAX_VCPUS; i++) {
497                 vcpu = apic->vcpu->kvm->vcpus[i];
498                 if (!vcpu)
499                         continue;
500
501                 if (vcpu->arch.apic &&
502                     apic_match_dest(vcpu, apic, short_hand, dest, dest_mode)) {
503                         if (delivery_mode == APIC_DM_LOWEST)
504                                 __set_bit(vcpu->vcpu_id, lpr_map);
505                         else
506                                 __apic_accept_irq(vcpu->arch.apic, delivery_mode,
507                                                   vector, level, trig_mode);
508                 }
509         }
510
511         if (delivery_mode == APIC_DM_LOWEST) {
512                 target = kvm_get_lowest_prio_vcpu(vcpu->kvm, vector, lpr_map);
513                 if (target != NULL)
514                         __apic_accept_irq(target->arch.apic, delivery_mode,
515                                           vector, level, trig_mode);
516         }
517 }
518
519 static u32 apic_get_tmcct(struct kvm_lapic *apic)
520 {
521         ktime_t remaining;
522         s64 ns;
523         u32 tmcct;
524
525         ASSERT(apic != NULL);
526
527         /* if initial count is 0, current count should also be 0 */
528         if (apic_get_reg(apic, APIC_TMICT) == 0)
529                 return 0;
530
531         remaining = hrtimer_expires_remaining(&apic->timer.dev);
532         if (ktime_to_ns(remaining) < 0)
533                 remaining = ktime_set(0, 0);
534
535         ns = mod_64(ktime_to_ns(remaining), apic->timer.period);
536         tmcct = div64_u64(ns, (APIC_BUS_CYCLE_NS * apic->timer.divide_count));
537
538         return tmcct;
539 }
540
541 static void __report_tpr_access(struct kvm_lapic *apic, bool write)
542 {
543         struct kvm_vcpu *vcpu = apic->vcpu;
544         struct kvm_run *run = vcpu->run;
545
546         set_bit(KVM_REQ_REPORT_TPR_ACCESS, &vcpu->requests);
547         run->tpr_access.rip = kvm_rip_read(vcpu);
548         run->tpr_access.is_write = write;
549 }
550
551 static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
552 {
553         if (apic->vcpu->arch.tpr_access_reporting)
554                 __report_tpr_access(apic, write);
555 }
556
557 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
558 {
559         u32 val = 0;
560
561         KVMTRACE_1D(APIC_ACCESS, apic->vcpu, (u32)offset, handler);
562
563         if (offset >= LAPIC_MMIO_LENGTH)
564                 return 0;
565
566         switch (offset) {
567         case APIC_ARBPRI:
568                 printk(KERN_WARNING "Access APIC ARBPRI register "
569                        "which is for P6\n");
570                 break;
571
572         case APIC_TMCCT:        /* Timer CCR */
573                 val = apic_get_tmcct(apic);
574                 break;
575
576         case APIC_TASKPRI:
577                 report_tpr_access(apic, false);
578                 /* fall thru */
579         default:
580                 apic_update_ppr(apic);
581                 val = apic_get_reg(apic, offset);
582                 break;
583         }
584
585         return val;
586 }
587
588 static void apic_mmio_read(struct kvm_io_device *this,
589                            gpa_t address, int len, void *data)
590 {
591         struct kvm_lapic *apic = (struct kvm_lapic *)this->private;
592         unsigned int offset = address - apic->base_address;
593         unsigned char alignment = offset & 0xf;
594         u32 result;
595
596         if ((alignment + len) > 4) {
597                 printk(KERN_ERR "KVM_APIC_READ: alignment error %lx %d",
598                        (unsigned long)address, len);
599                 return;
600         }
601         result = __apic_read(apic, offset & ~0xf);
602
603         switch (len) {
604         case 1:
605         case 2:
606         case 4:
607                 memcpy(data, (char *)&result + alignment, len);
608                 break;
609         default:
610                 printk(KERN_ERR "Local APIC read with len = %x, "
611                        "should be 1,2, or 4 instead\n", len);
612                 break;
613         }
614 }
615
616 static void update_divide_count(struct kvm_lapic *apic)
617 {
618         u32 tmp1, tmp2, tdcr;
619
620         tdcr = apic_get_reg(apic, APIC_TDCR);
621         tmp1 = tdcr & 0xf;
622         tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
623         apic->timer.divide_count = 0x1 << (tmp2 & 0x7);
624
625         apic_debug("timer divide count is 0x%x\n",
626                                    apic->timer.divide_count);
627 }
628
629 static void start_apic_timer(struct kvm_lapic *apic)
630 {
631         ktime_t now = apic->timer.dev.base->get_time();
632
633         apic->timer.period = apic_get_reg(apic, APIC_TMICT) *
634                     APIC_BUS_CYCLE_NS * apic->timer.divide_count;
635         atomic_set(&apic->timer.pending, 0);
636
637         if (!apic->timer.period)
638                 return;
639
640         hrtimer_start(&apic->timer.dev,
641                       ktime_add_ns(now, apic->timer.period),
642                       HRTIMER_MODE_ABS);
643
644         apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
645                            PRIx64 ", "
646                            "timer initial count 0x%x, period %lldns, "
647                            "expire @ 0x%016" PRIx64 ".\n", __func__,
648                            APIC_BUS_CYCLE_NS, ktime_to_ns(now),
649                            apic_get_reg(apic, APIC_TMICT),
650                            apic->timer.period,
651                            ktime_to_ns(ktime_add_ns(now,
652                                         apic->timer.period)));
653 }
654
655 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
656 {
657         int nmi_wd_enabled = apic_lvt_nmi_mode(apic_get_reg(apic, APIC_LVT0));
658
659         if (apic_lvt_nmi_mode(lvt0_val)) {
660                 if (!nmi_wd_enabled) {
661                         apic_debug("Receive NMI setting on APIC_LVT0 "
662                                    "for cpu %d\n", apic->vcpu->vcpu_id);
663                         apic->vcpu->kvm->arch.vapics_in_nmi_mode++;
664                 }
665         } else if (nmi_wd_enabled)
666                 apic->vcpu->kvm->arch.vapics_in_nmi_mode--;
667 }
668
669 static void apic_mmio_write(struct kvm_io_device *this,
670                             gpa_t address, int len, const void *data)
671 {
672         struct kvm_lapic *apic = (struct kvm_lapic *)this->private;
673         unsigned int offset = address - apic->base_address;
674         unsigned char alignment = offset & 0xf;
675         u32 val;
676
677         /*
678          * APIC register must be aligned on 128-bits boundary.
679          * 32/64/128 bits registers must be accessed thru 32 bits.
680          * Refer SDM 8.4.1
681          */
682         if (len != 4 || alignment) {
683                 /* Don't shout loud, $infamous_os would cause only noise. */
684                 apic_debug("apic write: bad size=%d %lx\n",
685                            len, (long)address);
686                 return;
687         }
688
689         val = *(u32 *) data;
690
691         /* too common printing */
692         if (offset != APIC_EOI)
693                 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
694                            "0x%x\n", __func__, offset, len, val);
695
696         offset &= 0xff0;
697
698         KVMTRACE_1D(APIC_ACCESS, apic->vcpu, (u32)offset, handler);
699
700         switch (offset) {
701         case APIC_ID:           /* Local APIC ID */
702                 apic_set_reg(apic, APIC_ID, val);
703                 break;
704
705         case APIC_TASKPRI:
706                 report_tpr_access(apic, true);
707                 apic_set_tpr(apic, val & 0xff);
708                 break;
709
710         case APIC_EOI:
711                 apic_set_eoi(apic);
712                 break;
713
714         case APIC_LDR:
715                 apic_set_reg(apic, APIC_LDR, val & APIC_LDR_MASK);
716                 break;
717
718         case APIC_DFR:
719                 apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
720                 break;
721
722         case APIC_SPIV:
723                 apic_set_reg(apic, APIC_SPIV, val & 0x3ff);
724                 if (!(val & APIC_SPIV_APIC_ENABLED)) {
725                         int i;
726                         u32 lvt_val;
727
728                         for (i = 0; i < APIC_LVT_NUM; i++) {
729                                 lvt_val = apic_get_reg(apic,
730                                                        APIC_LVTT + 0x10 * i);
731                                 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
732                                              lvt_val | APIC_LVT_MASKED);
733                         }
734                         atomic_set(&apic->timer.pending, 0);
735
736                 }
737                 break;
738
739         case APIC_ICR:
740                 /* No delay here, so we always clear the pending bit */
741                 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
742                 apic_send_ipi(apic);
743                 break;
744
745         case APIC_ICR2:
746                 apic_set_reg(apic, APIC_ICR2, val & 0xff000000);
747                 break;
748
749         case APIC_LVT0:
750                 apic_manage_nmi_watchdog(apic, val);
751         case APIC_LVTT:
752         case APIC_LVTTHMR:
753         case APIC_LVTPC:
754         case APIC_LVT1:
755         case APIC_LVTERR:
756                 /* TODO: Check vector */
757                 if (!apic_sw_enabled(apic))
758                         val |= APIC_LVT_MASKED;
759
760                 val &= apic_lvt_mask[(offset - APIC_LVTT) >> 4];
761                 apic_set_reg(apic, offset, val);
762
763                 break;
764
765         case APIC_TMICT:
766                 hrtimer_cancel(&apic->timer.dev);
767                 apic_set_reg(apic, APIC_TMICT, val);
768                 start_apic_timer(apic);
769                 return;
770
771         case APIC_TDCR:
772                 if (val & 4)
773                         printk(KERN_ERR "KVM_WRITE:TDCR %x\n", val);
774                 apic_set_reg(apic, APIC_TDCR, val);
775                 update_divide_count(apic);
776                 break;
777
778         default:
779                 apic_debug("Local APIC Write to read-only register %x\n",
780                            offset);
781                 break;
782         }
783
784 }
785
786 static int apic_mmio_range(struct kvm_io_device *this, gpa_t addr,
787                            int len, int size)
788 {
789         struct kvm_lapic *apic = (struct kvm_lapic *)this->private;
790         int ret = 0;
791
792
793         if (apic_hw_enabled(apic) &&
794             (addr >= apic->base_address) &&
795             (addr < (apic->base_address + LAPIC_MMIO_LENGTH)))
796                 ret = 1;
797
798         return ret;
799 }
800
801 void kvm_free_lapic(struct kvm_vcpu *vcpu)
802 {
803         if (!vcpu->arch.apic)
804                 return;
805
806         hrtimer_cancel(&vcpu->arch.apic->timer.dev);
807
808         if (vcpu->arch.apic->regs_page)
809                 __free_page(vcpu->arch.apic->regs_page);
810
811         kfree(vcpu->arch.apic);
812 }
813
814 /*
815  *----------------------------------------------------------------------
816  * LAPIC interface
817  *----------------------------------------------------------------------
818  */
819
820 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
821 {
822         struct kvm_lapic *apic = vcpu->arch.apic;
823
824         if (!apic)
825                 return;
826         apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
827                      | (apic_get_reg(apic, APIC_TASKPRI) & 4));
828 }
829 EXPORT_SYMBOL_GPL(kvm_lapic_set_tpr);
830
831 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
832 {
833         struct kvm_lapic *apic = vcpu->arch.apic;
834         u64 tpr;
835
836         if (!apic)
837                 return 0;
838         tpr = (u64) apic_get_reg(apic, APIC_TASKPRI);
839
840         return (tpr & 0xf0) >> 4;
841 }
842 EXPORT_SYMBOL_GPL(kvm_lapic_get_cr8);
843
844 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
845 {
846         struct kvm_lapic *apic = vcpu->arch.apic;
847
848         if (!apic) {
849                 value |= MSR_IA32_APICBASE_BSP;
850                 vcpu->arch.apic_base = value;
851                 return;
852         }
853         if (apic->vcpu->vcpu_id)
854                 value &= ~MSR_IA32_APICBASE_BSP;
855
856         vcpu->arch.apic_base = value;
857         apic->base_address = apic->vcpu->arch.apic_base &
858                              MSR_IA32_APICBASE_BASE;
859
860         /* with FSB delivery interrupt, we can restart APIC functionality */
861         apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
862                    "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
863
864 }
865
866 u64 kvm_lapic_get_base(struct kvm_vcpu *vcpu)
867 {
868         return vcpu->arch.apic_base;
869 }
870 EXPORT_SYMBOL_GPL(kvm_lapic_get_base);
871
872 void kvm_lapic_reset(struct kvm_vcpu *vcpu)
873 {
874         struct kvm_lapic *apic;
875         int i;
876
877         apic_debug("%s\n", __func__);
878
879         ASSERT(vcpu);
880         apic = vcpu->arch.apic;
881         ASSERT(apic != NULL);
882
883         /* Stop the timer in case it's a reset to an active apic */
884         hrtimer_cancel(&apic->timer.dev);
885
886         apic_set_reg(apic, APIC_ID, vcpu->vcpu_id << 24);
887         apic_set_reg(apic, APIC_LVR, APIC_VERSION);
888
889         for (i = 0; i < APIC_LVT_NUM; i++)
890                 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
891         apic_set_reg(apic, APIC_LVT0,
892                      SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
893
894         apic_set_reg(apic, APIC_DFR, 0xffffffffU);
895         apic_set_reg(apic, APIC_SPIV, 0xff);
896         apic_set_reg(apic, APIC_TASKPRI, 0);
897         apic_set_reg(apic, APIC_LDR, 0);
898         apic_set_reg(apic, APIC_ESR, 0);
899         apic_set_reg(apic, APIC_ICR, 0);
900         apic_set_reg(apic, APIC_ICR2, 0);
901         apic_set_reg(apic, APIC_TDCR, 0);
902         apic_set_reg(apic, APIC_TMICT, 0);
903         for (i = 0; i < 8; i++) {
904                 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
905                 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
906                 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
907         }
908         update_divide_count(apic);
909         atomic_set(&apic->timer.pending, 0);
910         if (vcpu->vcpu_id == 0)
911                 vcpu->arch.apic_base |= MSR_IA32_APICBASE_BSP;
912         apic_update_ppr(apic);
913
914         apic_debug(KERN_INFO "%s: vcpu=%p, id=%d, base_msr="
915                    "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
916                    vcpu, kvm_apic_id(apic),
917                    vcpu->arch.apic_base, apic->base_address);
918 }
919 EXPORT_SYMBOL_GPL(kvm_lapic_reset);
920
921 int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
922 {
923         struct kvm_lapic *apic = vcpu->arch.apic;
924         int ret = 0;
925
926         if (!apic)
927                 return 0;
928         ret = apic_enabled(apic);
929
930         return ret;
931 }
932 EXPORT_SYMBOL_GPL(kvm_lapic_enabled);
933
934 /*
935  *----------------------------------------------------------------------
936  * timer interface
937  *----------------------------------------------------------------------
938  */
939
940 /* TODO: make sure __apic_timer_fn runs in current pCPU */
941 static int __apic_timer_fn(struct kvm_lapic *apic)
942 {
943         int result = 0;
944         wait_queue_head_t *q = &apic->vcpu->wq;
945
946         if(!atomic_inc_and_test(&apic->timer.pending))
947                 set_bit(KVM_REQ_PENDING_TIMER, &apic->vcpu->requests);
948         if (waitqueue_active(q))
949                 wake_up_interruptible(q);
950
951         if (apic_lvtt_period(apic)) {
952                 result = 1;
953                 hrtimer_add_expires_ns(&apic->timer.dev, apic->timer.period);
954         }
955         return result;
956 }
957
958 int apic_has_pending_timer(struct kvm_vcpu *vcpu)
959 {
960         struct kvm_lapic *lapic = vcpu->arch.apic;
961
962         if (lapic && apic_enabled(lapic) && apic_lvt_enabled(lapic, APIC_LVTT))
963                 return atomic_read(&lapic->timer.pending);
964
965         return 0;
966 }
967
968 static int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
969 {
970         u32 reg = apic_get_reg(apic, lvt_type);
971         int vector, mode, trig_mode;
972
973         if (apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
974                 vector = reg & APIC_VECTOR_MASK;
975                 mode = reg & APIC_MODE_MASK;
976                 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
977                 return __apic_accept_irq(apic, mode, vector, 1, trig_mode);
978         }
979         return 0;
980 }
981
982 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
983 {
984         struct kvm_lapic *apic = vcpu->arch.apic;
985
986         if (apic)
987                 kvm_apic_local_deliver(apic, APIC_LVT0);
988 }
989
990 static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
991 {
992         struct kvm_lapic *apic;
993         int restart_timer = 0;
994
995         apic = container_of(data, struct kvm_lapic, timer.dev);
996
997         restart_timer = __apic_timer_fn(apic);
998
999         if (restart_timer)
1000                 return HRTIMER_RESTART;
1001         else
1002                 return HRTIMER_NORESTART;
1003 }
1004
1005 int kvm_create_lapic(struct kvm_vcpu *vcpu)
1006 {
1007         struct kvm_lapic *apic;
1008
1009         ASSERT(vcpu != NULL);
1010         apic_debug("apic_init %d\n", vcpu->vcpu_id);
1011
1012         apic = kzalloc(sizeof(*apic), GFP_KERNEL);
1013         if (!apic)
1014                 goto nomem;
1015
1016         vcpu->arch.apic = apic;
1017
1018         apic->regs_page = alloc_page(GFP_KERNEL);
1019         if (apic->regs_page == NULL) {
1020                 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
1021                        vcpu->vcpu_id);
1022                 goto nomem_free_apic;
1023         }
1024         apic->regs = page_address(apic->regs_page);
1025         memset(apic->regs, 0, PAGE_SIZE);
1026         apic->vcpu = vcpu;
1027
1028         hrtimer_init(&apic->timer.dev, CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
1029         apic->timer.dev.function = apic_timer_fn;
1030         apic->base_address = APIC_DEFAULT_PHYS_BASE;
1031         vcpu->arch.apic_base = APIC_DEFAULT_PHYS_BASE;
1032
1033         kvm_lapic_reset(vcpu);
1034         apic->dev.read = apic_mmio_read;
1035         apic->dev.write = apic_mmio_write;
1036         apic->dev.in_range = apic_mmio_range;
1037         apic->dev.private = apic;
1038
1039         return 0;
1040 nomem_free_apic:
1041         kfree(apic);
1042 nomem:
1043         return -ENOMEM;
1044 }
1045 EXPORT_SYMBOL_GPL(kvm_create_lapic);
1046
1047 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
1048 {
1049         struct kvm_lapic *apic = vcpu->arch.apic;
1050         int highest_irr;
1051
1052         if (!apic || !apic_enabled(apic))
1053                 return -1;
1054
1055         apic_update_ppr(apic);
1056         highest_irr = apic_find_highest_irr(apic);
1057         if ((highest_irr == -1) ||
1058             ((highest_irr & 0xF0) <= apic_get_reg(apic, APIC_PROCPRI)))
1059                 return -1;
1060         return highest_irr;
1061 }
1062
1063 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1064 {
1065         u32 lvt0 = apic_get_reg(vcpu->arch.apic, APIC_LVT0);
1066         int r = 0;
1067
1068         if (vcpu->vcpu_id == 0) {
1069                 if (!apic_hw_enabled(vcpu->arch.apic))
1070                         r = 1;
1071                 if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1072                     GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1073                         r = 1;
1074         }
1075         return r;
1076 }
1077
1078 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1079 {
1080         struct kvm_lapic *apic = vcpu->arch.apic;
1081
1082         if (apic && atomic_read(&apic->timer.pending) > 0) {
1083                 if (kvm_apic_local_deliver(apic, APIC_LVTT))
1084                         atomic_dec(&apic->timer.pending);
1085         }
1086 }
1087
1088 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1089 {
1090         int vector = kvm_apic_has_interrupt(vcpu);
1091         struct kvm_lapic *apic = vcpu->arch.apic;
1092
1093         if (vector == -1)
1094                 return -1;
1095
1096         apic_set_vector(vector, apic->regs + APIC_ISR);
1097         apic_update_ppr(apic);
1098         apic_clear_irr(vector, apic);
1099         return vector;
1100 }
1101
1102 void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu)
1103 {
1104         struct kvm_lapic *apic = vcpu->arch.apic;
1105
1106         apic->base_address = vcpu->arch.apic_base &
1107                              MSR_IA32_APICBASE_BASE;
1108         apic_set_reg(apic, APIC_LVR, APIC_VERSION);
1109         apic_update_ppr(apic);
1110         hrtimer_cancel(&apic->timer.dev);
1111         update_divide_count(apic);
1112         start_apic_timer(apic);
1113 }
1114
1115 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
1116 {
1117         struct kvm_lapic *apic = vcpu->arch.apic;
1118         struct hrtimer *timer;
1119
1120         if (!apic)
1121                 return;
1122
1123         timer = &apic->timer.dev;
1124         if (hrtimer_cancel(timer))
1125                 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
1126 }
1127
1128 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
1129 {
1130         u32 data;
1131         void *vapic;
1132
1133         if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr)
1134                 return;
1135
1136         vapic = kmap_atomic(vcpu->arch.apic->vapic_page, KM_USER0);
1137         data = *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr));
1138         kunmap_atomic(vapic, KM_USER0);
1139
1140         apic_set_tpr(vcpu->arch.apic, data & 0xff);
1141 }
1142
1143 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
1144 {
1145         u32 data, tpr;
1146         int max_irr, max_isr;
1147         struct kvm_lapic *apic;
1148         void *vapic;
1149
1150         if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr)
1151                 return;
1152
1153         apic = vcpu->arch.apic;
1154         tpr = apic_get_reg(apic, APIC_TASKPRI) & 0xff;
1155         max_irr = apic_find_highest_irr(apic);
1156         if (max_irr < 0)
1157                 max_irr = 0;
1158         max_isr = apic_find_highest_isr(apic);
1159         if (max_isr < 0)
1160                 max_isr = 0;
1161         data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
1162
1163         vapic = kmap_atomic(vcpu->arch.apic->vapic_page, KM_USER0);
1164         *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr)) = data;
1165         kunmap_atomic(vapic, KM_USER0);
1166 }
1167
1168 void kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
1169 {
1170         if (!irqchip_in_kernel(vcpu->kvm))
1171                 return;
1172
1173         vcpu->arch.apic->vapic_addr = vapic_addr;
1174 }