Merge branch 'x86/apic' into x86/core
[linux-2.6.git] / arch / x86 / kernel / io_apic_32.c
1 /*
2  *      Intel IO-APIC support for multi-Pentium hosts.
3  *
4  *      Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5  *
6  *      Many thanks to Stig Venaas for trying out countless experimental
7  *      patches and reporting/debugging problems patiently!
8  *
9  *      (c) 1999, Multiple IO-APIC support, developed by
10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
13  *      and Ingo Molnar <mingo@redhat.com>
14  *
15  *      Fixes
16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
17  *                                      thanks to Eric Gilmore
18  *                                      and Rolf G. Tews
19  *                                      for testing these extensively
20  *      Paul Diefenbaugh        :       Added full ACPI support
21  */
22
23 #include <linux/mm.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/bootmem.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/pci.h>
35 #include <linux/msi.h>
36 #include <linux/htirq.h>
37 #include <linux/freezer.h>
38 #include <linux/kthread.h>
39 #include <linux/jiffies.h>      /* time_after() */
40
41 #include <asm/io.h>
42 #include <asm/smp.h>
43 #include <asm/desc.h>
44 #include <asm/timer.h>
45 #include <asm/i8259.h>
46 #include <asm/nmi.h>
47 #include <asm/msidef.h>
48 #include <asm/hypertransport.h>
49 #include <asm/setup.h>
50
51 #include <mach_apic.h>
52 #include <mach_apicdef.h>
53
54 #define __apicdebuginit(type) static type __init
55
56 int (*ioapic_renumber_irq)(int ioapic, int irq);
57 atomic_t irq_mis_count;
58
59 /* Where if anywhere is the i8259 connect in external int mode */
60 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
61
62 static DEFINE_SPINLOCK(ioapic_lock);
63 DEFINE_SPINLOCK(vector_lock);
64
65 int timer_through_8259 __initdata;
66
67 /*
68  *      Is the SiS APIC rmw bug present ?
69  *      -1 = don't know, 0 = no, 1 = yes
70  */
71 int sis_apic_bug = -1;
72
73 /*
74  * # of IRQ routing registers
75  */
76 int nr_ioapic_registers[MAX_IO_APICS];
77
78 /* I/O APIC entries */
79 struct mp_config_ioapic mp_ioapics[MAX_IO_APICS];
80 int nr_ioapics;
81
82 /* MP IRQ source entries */
83 struct mp_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
84
85 /* # of MP IRQ source entries */
86 int mp_irq_entries;
87
88 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
89 int mp_bus_id_to_type[MAX_MP_BUSSES];
90 #endif
91
92 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
93
94 static int disable_timer_pin_1 __initdata;
95
96 /*
97  * Rough estimation of how many shared IRQs there are, can
98  * be changed anytime.
99  */
100 #define MAX_PLUS_SHARED_IRQS NR_IRQS
101 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
102
103 /*
104  * This is performance-critical, we want to do it O(1)
105  *
106  * the indexing order of this array favors 1:1 mappings
107  * between pins and IRQs.
108  */
109
110 static struct irq_pin_list {
111         int apic, pin, next;
112 } irq_2_pin[PIN_MAP_SIZE];
113
114 struct io_apic {
115         unsigned int index;
116         unsigned int unused[3];
117         unsigned int data;
118 };
119
120 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
121 {
122         return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
123                 + (mp_ioapics[idx].mp_apicaddr & ~PAGE_MASK);
124 }
125
126 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
127 {
128         struct io_apic __iomem *io_apic = io_apic_base(apic);
129         writel(reg, &io_apic->index);
130         return readl(&io_apic->data);
131 }
132
133 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
134 {
135         struct io_apic __iomem *io_apic = io_apic_base(apic);
136         writel(reg, &io_apic->index);
137         writel(value, &io_apic->data);
138 }
139
140 /*
141  * Re-write a value: to be used for read-modify-write
142  * cycles where the read already set up the index register.
143  *
144  * Older SiS APIC requires we rewrite the index register
145  */
146 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
147 {
148         volatile struct io_apic __iomem *io_apic = io_apic_base(apic);
149         if (sis_apic_bug)
150                 writel(reg, &io_apic->index);
151         writel(value, &io_apic->data);
152 }
153
154 union entry_union {
155         struct { u32 w1, w2; };
156         struct IO_APIC_route_entry entry;
157 };
158
159 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
160 {
161         union entry_union eu;
162         unsigned long flags;
163         spin_lock_irqsave(&ioapic_lock, flags);
164         eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
165         eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
166         spin_unlock_irqrestore(&ioapic_lock, flags);
167         return eu.entry;
168 }
169
170 /*
171  * When we write a new IO APIC routing entry, we need to write the high
172  * word first! If the mask bit in the low word is clear, we will enable
173  * the interrupt, and we need to make sure the entry is fully populated
174  * before that happens.
175  */
176 static void
177 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
178 {
179         union entry_union eu;
180         eu.entry = e;
181         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
182         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
183 }
184
185 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
186 {
187         unsigned long flags;
188         spin_lock_irqsave(&ioapic_lock, flags);
189         __ioapic_write_entry(apic, pin, e);
190         spin_unlock_irqrestore(&ioapic_lock, flags);
191 }
192
193 /*
194  * When we mask an IO APIC routing entry, we need to write the low
195  * word first, in order to set the mask bit before we change the
196  * high bits!
197  */
198 static void ioapic_mask_entry(int apic, int pin)
199 {
200         unsigned long flags;
201         union entry_union eu = { .entry.mask = 1 };
202
203         spin_lock_irqsave(&ioapic_lock, flags);
204         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
205         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
206         spin_unlock_irqrestore(&ioapic_lock, flags);
207 }
208
209 /*
210  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
211  * shared ISA-space IRQs, so we have to support them. We are super
212  * fast in the common case, and fast for shared ISA-space IRQs.
213  */
214 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
215 {
216         static int first_free_entry = NR_IRQS;
217         struct irq_pin_list *entry = irq_2_pin + irq;
218
219         while (entry->next)
220                 entry = irq_2_pin + entry->next;
221
222         if (entry->pin != -1) {
223                 entry->next = first_free_entry;
224                 entry = irq_2_pin + entry->next;
225                 if (++first_free_entry >= PIN_MAP_SIZE)
226                         panic("io_apic.c: whoops");
227         }
228         entry->apic = apic;
229         entry->pin = pin;
230 }
231
232 /*
233  * Reroute an IRQ to a different pin.
234  */
235 static void __init replace_pin_at_irq(unsigned int irq,
236                                       int oldapic, int oldpin,
237                                       int newapic, int newpin)
238 {
239         struct irq_pin_list *entry = irq_2_pin + irq;
240
241         while (1) {
242                 if (entry->apic == oldapic && entry->pin == oldpin) {
243                         entry->apic = newapic;
244                         entry->pin = newpin;
245                 }
246                 if (!entry->next)
247                         break;
248                 entry = irq_2_pin + entry->next;
249         }
250 }
251
252 static void __modify_IO_APIC_irq(unsigned int irq, unsigned long enable, unsigned long disable)
253 {
254         struct irq_pin_list *entry = irq_2_pin + irq;
255         unsigned int pin, reg;
256
257         for (;;) {
258                 pin = entry->pin;
259                 if (pin == -1)
260                         break;
261                 reg = io_apic_read(entry->apic, 0x10 + pin*2);
262                 reg &= ~disable;
263                 reg |= enable;
264                 io_apic_modify(entry->apic, 0x10 + pin*2, reg);
265                 if (!entry->next)
266                         break;
267                 entry = irq_2_pin + entry->next;
268         }
269 }
270
271 /* mask = 1 */
272 static void __mask_IO_APIC_irq(unsigned int irq)
273 {
274         __modify_IO_APIC_irq(irq, IO_APIC_REDIR_MASKED, 0);
275 }
276
277 /* mask = 0 */
278 static void __unmask_IO_APIC_irq(unsigned int irq)
279 {
280         __modify_IO_APIC_irq(irq, 0, IO_APIC_REDIR_MASKED);
281 }
282
283 /* mask = 1, trigger = 0 */
284 static void __mask_and_edge_IO_APIC_irq(unsigned int irq)
285 {
286         __modify_IO_APIC_irq(irq, IO_APIC_REDIR_MASKED,
287                                 IO_APIC_REDIR_LEVEL_TRIGGER);
288 }
289
290 /* mask = 0, trigger = 1 */
291 static void __unmask_and_level_IO_APIC_irq(unsigned int irq)
292 {
293         __modify_IO_APIC_irq(irq, IO_APIC_REDIR_LEVEL_TRIGGER,
294                                 IO_APIC_REDIR_MASKED);
295 }
296
297 static void mask_IO_APIC_irq(unsigned int irq)
298 {
299         unsigned long flags;
300
301         spin_lock_irqsave(&ioapic_lock, flags);
302         __mask_IO_APIC_irq(irq);
303         spin_unlock_irqrestore(&ioapic_lock, flags);
304 }
305
306 static void unmask_IO_APIC_irq(unsigned int irq)
307 {
308         unsigned long flags;
309
310         spin_lock_irqsave(&ioapic_lock, flags);
311         __unmask_IO_APIC_irq(irq);
312         spin_unlock_irqrestore(&ioapic_lock, flags);
313 }
314
315 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
316 {
317         struct IO_APIC_route_entry entry;
318
319         /* Check delivery_mode to be sure we're not clearing an SMI pin */
320         entry = ioapic_read_entry(apic, pin);
321         if (entry.delivery_mode == dest_SMI)
322                 return;
323
324         /*
325          * Disable it in the IO-APIC irq-routing table:
326          */
327         ioapic_mask_entry(apic, pin);
328 }
329
330 static void clear_IO_APIC(void)
331 {
332         int apic, pin;
333
334         for (apic = 0; apic < nr_ioapics; apic++)
335                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
336                         clear_IO_APIC_pin(apic, pin);
337 }
338
339 #ifdef CONFIG_SMP
340 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
341 {
342         unsigned long flags;
343         int pin;
344         struct irq_pin_list *entry = irq_2_pin + irq;
345         unsigned int apicid_value;
346         cpumask_t tmp;
347
348         cpus_and(tmp, cpumask, cpu_online_map);
349         if (cpus_empty(tmp))
350                 tmp = TARGET_CPUS;
351
352         cpus_and(cpumask, tmp, CPU_MASK_ALL);
353
354         apicid_value = cpu_mask_to_apicid(cpumask);
355         /* Prepare to do the io_apic_write */
356         apicid_value = apicid_value << 24;
357         spin_lock_irqsave(&ioapic_lock, flags);
358         for (;;) {
359                 pin = entry->pin;
360                 if (pin == -1)
361                         break;
362                 io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
363                 if (!entry->next)
364                         break;
365                 entry = irq_2_pin + entry->next;
366         }
367         irq_desc[irq].affinity = cpumask;
368         spin_unlock_irqrestore(&ioapic_lock, flags);
369 }
370
371 #if defined(CONFIG_IRQBALANCE)
372 # include <asm/processor.h>     /* kernel_thread() */
373 # include <linux/kernel_stat.h> /* kstat */
374 # include <linux/slab.h>                /* kmalloc() */
375 # include <linux/timer.h>
376
377 #define IRQBALANCE_CHECK_ARCH -999
378 #define MAX_BALANCED_IRQ_INTERVAL       (5*HZ)
379 #define MIN_BALANCED_IRQ_INTERVAL       (HZ/2)
380 #define BALANCED_IRQ_MORE_DELTA         (HZ/10)
381 #define BALANCED_IRQ_LESS_DELTA         (HZ)
382
383 static int irqbalance_disabled __read_mostly = IRQBALANCE_CHECK_ARCH;
384 static int physical_balance __read_mostly;
385 static long balanced_irq_interval __read_mostly = MAX_BALANCED_IRQ_INTERVAL;
386
387 static struct irq_cpu_info {
388         unsigned long *last_irq;
389         unsigned long *irq_delta;
390         unsigned long irq;
391 } irq_cpu_data[NR_CPUS];
392
393 #define CPU_IRQ(cpu)            (irq_cpu_data[cpu].irq)
394 #define LAST_CPU_IRQ(cpu, irq)   (irq_cpu_data[cpu].last_irq[irq])
395 #define IRQ_DELTA(cpu, irq)     (irq_cpu_data[cpu].irq_delta[irq])
396
397 #define IDLE_ENOUGH(cpu,now) \
398         (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
399
400 #define IRQ_ALLOWED(cpu, allowed_mask)  cpu_isset(cpu, allowed_mask)
401
402 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(per_cpu(cpu_sibling_map, i)))
403
404 static cpumask_t balance_irq_affinity[NR_IRQS] = {
405         [0 ... NR_IRQS-1] = CPU_MASK_ALL
406 };
407
408 void set_balance_irq_affinity(unsigned int irq, cpumask_t mask)
409 {
410         balance_irq_affinity[irq] = mask;
411 }
412
413 static unsigned long move(int curr_cpu, cpumask_t allowed_mask,
414                         unsigned long now, int direction)
415 {
416         int search_idle = 1;
417         int cpu = curr_cpu;
418
419         goto inside;
420
421         do {
422                 if (unlikely(cpu == curr_cpu))
423                         search_idle = 0;
424 inside:
425                 if (direction == 1) {
426                         cpu++;
427                         if (cpu >= NR_CPUS)
428                                 cpu = 0;
429                 } else {
430                         cpu--;
431                         if (cpu == -1)
432                                 cpu = NR_CPUS-1;
433                 }
434         } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu, allowed_mask) ||
435                         (search_idle && !IDLE_ENOUGH(cpu, now)));
436
437         return cpu;
438 }
439
440 static inline void balance_irq(int cpu, int irq)
441 {
442         unsigned long now = jiffies;
443         cpumask_t allowed_mask;
444         unsigned int new_cpu;
445
446         if (irqbalance_disabled)
447                 return;
448
449         cpus_and(allowed_mask, cpu_online_map, balance_irq_affinity[irq]);
450         new_cpu = move(cpu, allowed_mask, now, 1);
451         if (cpu != new_cpu)
452                 set_pending_irq(irq, cpumask_of_cpu(new_cpu));
453 }
454
455 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold)
456 {
457         int i, j;
458
459         for_each_online_cpu(i) {
460                 for (j = 0; j < NR_IRQS; j++) {
461                         if (!irq_desc[j].action)
462                                 continue;
463                         /* Is it a significant load ?  */
464                         if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i), j) <
465                                                 useful_load_threshold)
466                                 continue;
467                         balance_irq(i, j);
468                 }
469         }
470         balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
471                 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
472         return;
473 }
474
475 static void do_irq_balance(void)
476 {
477         int i, j;
478         unsigned long max_cpu_irq = 0, min_cpu_irq = (~0);
479         unsigned long move_this_load = 0;
480         int max_loaded = 0, min_loaded = 0;
481         int load;
482         unsigned long useful_load_threshold = balanced_irq_interval + 10;
483         int selected_irq;
484         int tmp_loaded, first_attempt = 1;
485         unsigned long tmp_cpu_irq;
486         unsigned long imbalance = 0;
487         cpumask_t allowed_mask, target_cpu_mask, tmp;
488
489         for_each_possible_cpu(i) {
490                 int package_index;
491                 CPU_IRQ(i) = 0;
492                 if (!cpu_online(i))
493                         continue;
494                 package_index = CPU_TO_PACKAGEINDEX(i);
495                 for (j = 0; j < NR_IRQS; j++) {
496                         unsigned long value_now, delta;
497                         /* Is this an active IRQ or balancing disabled ? */
498                         if (!irq_desc[j].action || irq_balancing_disabled(j))
499                                 continue;
500                         if (package_index == i)
501                                 IRQ_DELTA(package_index, j) = 0;
502                         /* Determine the total count per processor per IRQ */
503                         value_now = (unsigned long) kstat_cpu(i).irqs[j];
504
505                         /* Determine the activity per processor per IRQ */
506                         delta = value_now - LAST_CPU_IRQ(i, j);
507
508                         /* Update last_cpu_irq[][] for the next time */
509                         LAST_CPU_IRQ(i, j) = value_now;
510
511                         /* Ignore IRQs whose rate is less than the clock */
512                         if (delta < useful_load_threshold)
513                                 continue;
514                         /* update the load for the processor or package total */
515                         IRQ_DELTA(package_index, j) += delta;
516
517                         /* Keep track of the higher numbered sibling as well */
518                         if (i != package_index)
519                                 CPU_IRQ(i) += delta;
520                         /*
521                          * We have sibling A and sibling B in the package
522                          *
523                          * cpu_irq[A] = load for cpu A + load for cpu B
524                          * cpu_irq[B] = load for cpu B
525                          */
526                         CPU_IRQ(package_index) += delta;
527                 }
528         }
529         /* Find the least loaded processor package */
530         for_each_online_cpu(i) {
531                 if (i != CPU_TO_PACKAGEINDEX(i))
532                         continue;
533                 if (min_cpu_irq > CPU_IRQ(i)) {
534                         min_cpu_irq = CPU_IRQ(i);
535                         min_loaded = i;
536                 }
537         }
538         max_cpu_irq = ULONG_MAX;
539
540 tryanothercpu:
541         /*
542          * Look for heaviest loaded processor.
543          * We may come back to get the next heaviest loaded processor.
544          * Skip processors with trivial loads.
545          */
546         tmp_cpu_irq = 0;
547         tmp_loaded = -1;
548         for_each_online_cpu(i) {
549                 if (i != CPU_TO_PACKAGEINDEX(i))
550                         continue;
551                 if (max_cpu_irq <= CPU_IRQ(i))
552                         continue;
553                 if (tmp_cpu_irq < CPU_IRQ(i)) {
554                         tmp_cpu_irq = CPU_IRQ(i);
555                         tmp_loaded = i;
556                 }
557         }
558
559         if (tmp_loaded == -1) {
560          /*
561           * In the case of small number of heavy interrupt sources,
562           * loading some of the cpus too much. We use Ingo's original
563           * approach to rotate them around.
564           */
565                 if (!first_attempt && imbalance >= useful_load_threshold) {
566                         rotate_irqs_among_cpus(useful_load_threshold);
567                         return;
568                 }
569                 goto not_worth_the_effort;
570         }
571
572         first_attempt = 0;              /* heaviest search */
573         max_cpu_irq = tmp_cpu_irq;      /* load */
574         max_loaded = tmp_loaded;        /* processor */
575         imbalance = (max_cpu_irq - min_cpu_irq) / 2;
576
577         /*
578          * if imbalance is less than approx 10% of max load, then
579          * observe diminishing returns action. - quit
580          */
581         if (imbalance < (max_cpu_irq >> 3))
582                 goto not_worth_the_effort;
583
584 tryanotherirq:
585         /* if we select an IRQ to move that can't go where we want, then
586          * see if there is another one to try.
587          */
588         move_this_load = 0;
589         selected_irq = -1;
590         for (j = 0; j < NR_IRQS; j++) {
591                 /* Is this an active IRQ? */
592                 if (!irq_desc[j].action)
593                         continue;
594                 if (imbalance <= IRQ_DELTA(max_loaded, j))
595                         continue;
596                 /* Try to find the IRQ that is closest to the imbalance
597                  * without going over.
598                  */
599                 if (move_this_load < IRQ_DELTA(max_loaded, j)) {
600                         move_this_load = IRQ_DELTA(max_loaded, j);
601                         selected_irq = j;
602                 }
603         }
604         if (selected_irq == -1)
605                 goto tryanothercpu;
606
607         imbalance = move_this_load;
608
609         /* For physical_balance case, we accumulated both load
610          * values in the one of the siblings cpu_irq[],
611          * to use the same code for physical and logical processors
612          * as much as possible.
613          *
614          * NOTE: the cpu_irq[] array holds the sum of the load for
615          * sibling A and sibling B in the slot for the lowest numbered
616          * sibling (A), _AND_ the load for sibling B in the slot for
617          * the higher numbered sibling.
618          *
619          * We seek the least loaded sibling by making the comparison
620          * (A+B)/2 vs B
621          */
622         load = CPU_IRQ(min_loaded) >> 1;
623         for_each_cpu_mask(j, per_cpu(cpu_sibling_map, min_loaded)) {
624                 if (load > CPU_IRQ(j)) {
625                         /* This won't change cpu_sibling_map[min_loaded] */
626                         load = CPU_IRQ(j);
627                         min_loaded = j;
628                 }
629         }
630
631         cpus_and(allowed_mask,
632                 cpu_online_map,
633                 balance_irq_affinity[selected_irq]);
634         target_cpu_mask = cpumask_of_cpu(min_loaded);
635         cpus_and(tmp, target_cpu_mask, allowed_mask);
636
637         if (!cpus_empty(tmp)) {
638                 /* mark for change destination */
639                 set_pending_irq(selected_irq, cpumask_of_cpu(min_loaded));
640
641                 /* Since we made a change, come back sooner to
642                  * check for more variation.
643                  */
644                 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
645                         balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
646                 return;
647         }
648         goto tryanotherirq;
649
650 not_worth_the_effort:
651         /*
652          * if we did not find an IRQ to move, then adjust the time interval
653          * upward
654          */
655         balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL,
656                 balanced_irq_interval + BALANCED_IRQ_MORE_DELTA);
657         return;
658 }
659
660 static int balanced_irq(void *unused)
661 {
662         int i;
663         unsigned long prev_balance_time = jiffies;
664         long time_remaining = balanced_irq_interval;
665
666         /* push everything to CPU 0 to give us a starting point.  */
667         for (i = 0 ; i < NR_IRQS ; i++) {
668                 irq_desc[i].pending_mask = cpumask_of_cpu(0);
669                 set_pending_irq(i, cpumask_of_cpu(0));
670         }
671
672         set_freezable();
673         for ( ; ; ) {
674                 time_remaining = schedule_timeout_interruptible(time_remaining);
675                 try_to_freeze();
676                 if (time_after(jiffies,
677                                 prev_balance_time+balanced_irq_interval)) {
678                         preempt_disable();
679                         do_irq_balance();
680                         prev_balance_time = jiffies;
681                         time_remaining = balanced_irq_interval;
682                         preempt_enable();
683                 }
684         }
685         return 0;
686 }
687
688 static int __init balanced_irq_init(void)
689 {
690         int i;
691         struct cpuinfo_x86 *c;
692         cpumask_t tmp;
693
694         cpus_shift_right(tmp, cpu_online_map, 2);
695         c = &boot_cpu_data;
696         /* When not overwritten by the command line ask subarchitecture. */
697         if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH)
698                 irqbalance_disabled = NO_BALANCE_IRQ;
699         if (irqbalance_disabled)
700                 return 0;
701
702          /* disable irqbalance completely if there is only one processor online */
703         if (num_online_cpus() < 2) {
704                 irqbalance_disabled = 1;
705                 return 0;
706         }
707         /*
708          * Enable physical balance only if more than 1 physical processor
709          * is present
710          */
711         if (smp_num_siblings > 1 && !cpus_empty(tmp))
712                 physical_balance = 1;
713
714         for_each_online_cpu(i) {
715                 irq_cpu_data[i].irq_delta = kzalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
716                 irq_cpu_data[i].last_irq = kzalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
717                 if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) {
718                         printk(KERN_ERR "balanced_irq_init: out of memory");
719                         goto failed;
720                 }
721         }
722
723         printk(KERN_INFO "Starting balanced_irq\n");
724         if (!IS_ERR(kthread_run(balanced_irq, NULL, "kirqd")))
725                 return 0;
726         printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq");
727 failed:
728         for_each_possible_cpu(i) {
729                 kfree(irq_cpu_data[i].irq_delta);
730                 irq_cpu_data[i].irq_delta = NULL;
731                 kfree(irq_cpu_data[i].last_irq);
732                 irq_cpu_data[i].last_irq = NULL;
733         }
734         return 0;
735 }
736
737 int __devinit irqbalance_disable(char *str)
738 {
739         irqbalance_disabled = 1;
740         return 1;
741 }
742
743 __setup("noirqbalance", irqbalance_disable);
744
745 late_initcall(balanced_irq_init);
746 #endif /* CONFIG_IRQBALANCE */
747 #endif /* CONFIG_SMP */
748
749 #ifndef CONFIG_SMP
750 void send_IPI_self(int vector)
751 {
752         unsigned int cfg;
753
754         /*
755          * Wait for idle.
756          */
757         apic_wait_icr_idle();
758         cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
759         /*
760          * Send the IPI. The write to APIC_ICR fires this off.
761          */
762         apic_write(APIC_ICR, cfg);
763 }
764 #endif /* !CONFIG_SMP */
765
766
767 /*
768  * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
769  * specific CPU-side IRQs.
770  */
771
772 #define MAX_PIRQS 8
773 static int pirq_entries [MAX_PIRQS];
774 static int pirqs_enabled;
775 int skip_ioapic_setup;
776
777 static int __init ioapic_pirq_setup(char *str)
778 {
779         int i, max;
780         int ints[MAX_PIRQS+1];
781
782         get_options(str, ARRAY_SIZE(ints), ints);
783
784         for (i = 0; i < MAX_PIRQS; i++)
785                 pirq_entries[i] = -1;
786
787         pirqs_enabled = 1;
788         apic_printk(APIC_VERBOSE, KERN_INFO
789                         "PIRQ redirection, working around broken MP-BIOS.\n");
790         max = MAX_PIRQS;
791         if (ints[0] < MAX_PIRQS)
792                 max = ints[0];
793
794         for (i = 0; i < max; i++) {
795                 apic_printk(APIC_VERBOSE, KERN_DEBUG
796                                 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
797                 /*
798                  * PIRQs are mapped upside down, usually.
799                  */
800                 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
801         }
802         return 1;
803 }
804
805 __setup("pirq=", ioapic_pirq_setup);
806
807 /*
808  * Find the IRQ entry number of a certain pin.
809  */
810 static int find_irq_entry(int apic, int pin, int type)
811 {
812         int i;
813
814         for (i = 0; i < mp_irq_entries; i++)
815                 if (mp_irqs[i].mp_irqtype == type &&
816                     (mp_irqs[i].mp_dstapic == mp_ioapics[apic].mp_apicid ||
817                      mp_irqs[i].mp_dstapic == MP_APIC_ALL) &&
818                     mp_irqs[i].mp_dstirq == pin)
819                         return i;
820
821         return -1;
822 }
823
824 /*
825  * Find the pin to which IRQ[irq] (ISA) is connected
826  */
827 static int __init find_isa_irq_pin(int irq, int type)
828 {
829         int i;
830
831         for (i = 0; i < mp_irq_entries; i++) {
832                 int lbus = mp_irqs[i].mp_srcbus;
833
834                 if (test_bit(lbus, mp_bus_not_pci) &&
835                     (mp_irqs[i].mp_irqtype == type) &&
836                     (mp_irqs[i].mp_srcbusirq == irq))
837
838                         return mp_irqs[i].mp_dstirq;
839         }
840         return -1;
841 }
842
843 static int __init find_isa_irq_apic(int irq, int type)
844 {
845         int i;
846
847         for (i = 0; i < mp_irq_entries; i++) {
848                 int lbus = mp_irqs[i].mp_srcbus;
849
850                 if (test_bit(lbus, mp_bus_not_pci) &&
851                     (mp_irqs[i].mp_irqtype == type) &&
852                     (mp_irqs[i].mp_srcbusirq == irq))
853                         break;
854         }
855         if (i < mp_irq_entries) {
856                 int apic;
857                 for (apic = 0; apic < nr_ioapics; apic++) {
858                         if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic)
859                                 return apic;
860                 }
861         }
862
863         return -1;
864 }
865
866 /*
867  * Find a specific PCI IRQ entry.
868  * Not an __init, possibly needed by modules
869  */
870 static int pin_2_irq(int idx, int apic, int pin);
871
872 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
873 {
874         int apic, i, best_guess = -1;
875
876         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, "
877                 "slot:%d, pin:%d.\n", bus, slot, pin);
878         if (test_bit(bus, mp_bus_not_pci)) {
879                 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
880                 return -1;
881         }
882         for (i = 0; i < mp_irq_entries; i++) {
883                 int lbus = mp_irqs[i].mp_srcbus;
884
885                 for (apic = 0; apic < nr_ioapics; apic++)
886                         if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic ||
887                             mp_irqs[i].mp_dstapic == MP_APIC_ALL)
888                                 break;
889
890                 if (!test_bit(lbus, mp_bus_not_pci) &&
891                     !mp_irqs[i].mp_irqtype &&
892                     (bus == lbus) &&
893                     (slot == ((mp_irqs[i].mp_srcbusirq >> 2) & 0x1f))) {
894                         int irq = pin_2_irq(i, apic, mp_irqs[i].mp_dstirq);
895
896                         if (!(apic || IO_APIC_IRQ(irq)))
897                                 continue;
898
899                         if (pin == (mp_irqs[i].mp_srcbusirq & 3))
900                                 return irq;
901                         /*
902                          * Use the first all-but-pin matching entry as a
903                          * best-guess fuzzy result for broken mptables.
904                          */
905                         if (best_guess < 0)
906                                 best_guess = irq;
907                 }
908         }
909         return best_guess;
910 }
911 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
912
913 /*
914  * This function currently is only a helper for the i386 smp boot process where
915  * we need to reprogram the ioredtbls to cater for the cpus which have come online
916  * so mask in all cases should simply be TARGET_CPUS
917  */
918 #ifdef CONFIG_SMP
919 void __init setup_ioapic_dest(void)
920 {
921         int pin, ioapic, irq, irq_entry;
922
923         if (skip_ioapic_setup == 1)
924                 return;
925
926         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
927                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
928                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
929                         if (irq_entry == -1)
930                                 continue;
931                         irq = pin_2_irq(irq_entry, ioapic, pin);
932                         set_ioapic_affinity_irq(irq, TARGET_CPUS);
933                 }
934
935         }
936 }
937 #endif
938
939 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
940 /*
941  * EISA Edge/Level control register, ELCR
942  */
943 static int EISA_ELCR(unsigned int irq)
944 {
945         if (irq < 16) {
946                 unsigned int port = 0x4d0 + (irq >> 3);
947                 return (inb(port) >> (irq & 7)) & 1;
948         }
949         apic_printk(APIC_VERBOSE, KERN_INFO
950                         "Broken MPtable reports ISA irq %d\n", irq);
951         return 0;
952 }
953 #endif
954
955 /* ISA interrupts are always polarity zero edge triggered,
956  * when listed as conforming in the MP table. */
957
958 #define default_ISA_trigger(idx)        (0)
959 #define default_ISA_polarity(idx)       (0)
960
961 /* EISA interrupts are always polarity zero and can be edge or level
962  * trigger depending on the ELCR value.  If an interrupt is listed as
963  * EISA conforming in the MP table, that means its trigger type must
964  * be read in from the ELCR */
965
966 #define default_EISA_trigger(idx)       (EISA_ELCR(mp_irqs[idx].mp_srcbusirq))
967 #define default_EISA_polarity(idx)      default_ISA_polarity(idx)
968
969 /* PCI interrupts are always polarity one level triggered,
970  * when listed as conforming in the MP table. */
971
972 #define default_PCI_trigger(idx)        (1)
973 #define default_PCI_polarity(idx)       (1)
974
975 /* MCA interrupts are always polarity zero level triggered,
976  * when listed as conforming in the MP table. */
977
978 #define default_MCA_trigger(idx)        (1)
979 #define default_MCA_polarity(idx)       default_ISA_polarity(idx)
980
981 static int MPBIOS_polarity(int idx)
982 {
983         int bus = mp_irqs[idx].mp_srcbus;
984         int polarity;
985
986         /*
987          * Determine IRQ line polarity (high active or low active):
988          */
989         switch (mp_irqs[idx].mp_irqflag & 3) {
990         case 0: /* conforms, ie. bus-type dependent polarity */
991         {
992                 polarity = test_bit(bus, mp_bus_not_pci)?
993                         default_ISA_polarity(idx):
994                         default_PCI_polarity(idx);
995                 break;
996         }
997         case 1: /* high active */
998         {
999                 polarity = 0;
1000                 break;
1001         }
1002         case 2: /* reserved */
1003         {
1004                 printk(KERN_WARNING "broken BIOS!!\n");
1005                 polarity = 1;
1006                 break;
1007         }
1008         case 3: /* low active */
1009         {
1010                 polarity = 1;
1011                 break;
1012         }
1013         default: /* invalid */
1014         {
1015                 printk(KERN_WARNING "broken BIOS!!\n");
1016                 polarity = 1;
1017                 break;
1018         }
1019         }
1020         return polarity;
1021 }
1022
1023 static int MPBIOS_trigger(int idx)
1024 {
1025         int bus = mp_irqs[idx].mp_srcbus;
1026         int trigger;
1027
1028         /*
1029          * Determine IRQ trigger mode (edge or level sensitive):
1030          */
1031         switch ((mp_irqs[idx].mp_irqflag>>2) & 3) {
1032         case 0: /* conforms, ie. bus-type dependent */
1033         {
1034                 trigger = test_bit(bus, mp_bus_not_pci)?
1035                                 default_ISA_trigger(idx):
1036                                 default_PCI_trigger(idx);
1037 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1038                 switch (mp_bus_id_to_type[bus]) {
1039                 case MP_BUS_ISA: /* ISA pin */
1040                 {
1041                         /* set before the switch */
1042                         break;
1043                 }
1044                 case MP_BUS_EISA: /* EISA pin */
1045                 {
1046                         trigger = default_EISA_trigger(idx);
1047                         break;
1048                 }
1049                 case MP_BUS_PCI: /* PCI pin */
1050                 {
1051                         /* set before the switch */
1052                         break;
1053                 }
1054                 case MP_BUS_MCA: /* MCA pin */
1055                 {
1056                         trigger = default_MCA_trigger(idx);
1057                         break;
1058                 }
1059                 default:
1060                 {
1061                         printk(KERN_WARNING "broken BIOS!!\n");
1062                         trigger = 1;
1063                         break;
1064                 }
1065         }
1066 #endif
1067                 break;
1068         }
1069         case 1: /* edge */
1070         {
1071                 trigger = 0;
1072                 break;
1073         }
1074         case 2: /* reserved */
1075         {
1076                 printk(KERN_WARNING "broken BIOS!!\n");
1077                 trigger = 1;
1078                 break;
1079         }
1080         case 3: /* level */
1081         {
1082                 trigger = 1;
1083                 break;
1084         }
1085         default: /* invalid */
1086         {
1087                 printk(KERN_WARNING "broken BIOS!!\n");
1088                 trigger = 0;
1089                 break;
1090         }
1091         }
1092         return trigger;
1093 }
1094
1095 static inline int irq_polarity(int idx)
1096 {
1097         return MPBIOS_polarity(idx);
1098 }
1099
1100 static inline int irq_trigger(int idx)
1101 {
1102         return MPBIOS_trigger(idx);
1103 }
1104
1105 static int pin_2_irq(int idx, int apic, int pin)
1106 {
1107         int irq, i;
1108         int bus = mp_irqs[idx].mp_srcbus;
1109
1110         /*
1111          * Debugging check, we are in big trouble if this message pops up!
1112          */
1113         if (mp_irqs[idx].mp_dstirq != pin)
1114                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1115
1116         if (test_bit(bus, mp_bus_not_pci))
1117                 irq = mp_irqs[idx].mp_srcbusirq;
1118         else {
1119                 /*
1120                  * PCI IRQs are mapped in order
1121                  */
1122                 i = irq = 0;
1123                 while (i < apic)
1124                         irq += nr_ioapic_registers[i++];
1125                 irq += pin;
1126
1127                 /*
1128                  * For MPS mode, so far only needed by ES7000 platform
1129                  */
1130                 if (ioapic_renumber_irq)
1131                         irq = ioapic_renumber_irq(apic, irq);
1132         }
1133
1134         /*
1135          * PCI IRQ command line redirection. Yes, limits are hardcoded.
1136          */
1137         if ((pin >= 16) && (pin <= 23)) {
1138                 if (pirq_entries[pin-16] != -1) {
1139                         if (!pirq_entries[pin-16]) {
1140                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1141                                                 "disabling PIRQ%d\n", pin-16);
1142                         } else {
1143                                 irq = pirq_entries[pin-16];
1144                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1145                                                 "using PIRQ%d -> IRQ %d\n",
1146                                                 pin-16, irq);
1147                         }
1148                 }
1149         }
1150         return irq;
1151 }
1152
1153 static inline int IO_APIC_irq_trigger(int irq)
1154 {
1155         int apic, idx, pin;
1156
1157         for (apic = 0; apic < nr_ioapics; apic++) {
1158                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1159                         idx = find_irq_entry(apic, pin, mp_INT);
1160                         if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1161                                 return irq_trigger(idx);
1162                 }
1163         }
1164         /*
1165          * nonexistent IRQs are edge default
1166          */
1167         return 0;
1168 }
1169
1170 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1171 static u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 };
1172
1173 static int __assign_irq_vector(int irq)
1174 {
1175         static int current_vector = FIRST_DEVICE_VECTOR, current_offset;
1176         int vector, offset;
1177
1178         BUG_ON((unsigned)irq >= NR_IRQ_VECTORS);
1179
1180         if (irq_vector[irq] > 0)
1181                 return irq_vector[irq];
1182
1183         vector = current_vector;
1184         offset = current_offset;
1185 next:
1186         vector += 8;
1187         if (vector >= first_system_vector) {
1188                 offset = (offset + 1) % 8;
1189                 vector = FIRST_DEVICE_VECTOR + offset;
1190         }
1191         if (vector == current_vector)
1192                 return -ENOSPC;
1193         if (test_and_set_bit(vector, used_vectors))
1194                 goto next;
1195
1196         current_vector = vector;
1197         current_offset = offset;
1198         irq_vector[irq] = vector;
1199
1200         return vector;
1201 }
1202
1203 static int assign_irq_vector(int irq)
1204 {
1205         unsigned long flags;
1206         int vector;
1207
1208         spin_lock_irqsave(&vector_lock, flags);
1209         vector = __assign_irq_vector(irq);
1210         spin_unlock_irqrestore(&vector_lock, flags);
1211
1212         return vector;
1213 }
1214
1215 static struct irq_chip ioapic_chip;
1216
1217 #define IOAPIC_AUTO     -1
1218 #define IOAPIC_EDGE     0
1219 #define IOAPIC_LEVEL    1
1220
1221 static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
1222 {
1223         if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1224             trigger == IOAPIC_LEVEL) {
1225                 irq_desc[irq].status |= IRQ_LEVEL;
1226                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1227                                          handle_fasteoi_irq, "fasteoi");
1228         } else {
1229                 irq_desc[irq].status &= ~IRQ_LEVEL;
1230                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1231                                          handle_edge_irq, "edge");
1232         }
1233         set_intr_gate(vector, interrupt[irq]);
1234 }
1235
1236 static void __init setup_IO_APIC_irqs(void)
1237 {
1238         struct IO_APIC_route_entry entry;
1239         int apic, pin, idx, irq, first_notcon = 1, vector;
1240
1241         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1242
1243         for (apic = 0; apic < nr_ioapics; apic++) {
1244         for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1245
1246                 /*
1247                  * add it to the IO-APIC irq-routing table:
1248                  */
1249                 memset(&entry, 0, sizeof(entry));
1250
1251                 entry.delivery_mode = INT_DELIVERY_MODE;
1252                 entry.dest_mode = INT_DEST_MODE;
1253                 entry.mask = 0;                         /* enable IRQ */
1254                 entry.dest.logical.logical_dest =
1255                                         cpu_mask_to_apicid(TARGET_CPUS);
1256
1257                 idx = find_irq_entry(apic, pin, mp_INT);
1258                 if (idx == -1) {
1259                         if (first_notcon) {
1260                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1261                                                 " IO-APIC (apicid-pin) %d-%d",
1262                                                 mp_ioapics[apic].mp_apicid,
1263                                                 pin);
1264                                 first_notcon = 0;
1265                         } else
1266                                 apic_printk(APIC_VERBOSE, ", %d-%d",
1267                                         mp_ioapics[apic].mp_apicid, pin);
1268                         continue;
1269                 }
1270
1271                 if (!first_notcon) {
1272                         apic_printk(APIC_VERBOSE, " not connected.\n");
1273                         first_notcon = 1;
1274                 }
1275
1276                 entry.trigger = irq_trigger(idx);
1277                 entry.polarity = irq_polarity(idx);
1278
1279                 if (irq_trigger(idx)) {
1280                         entry.trigger = 1;
1281                         entry.mask = 1;
1282                 }
1283
1284                 irq = pin_2_irq(idx, apic, pin);
1285                 /*
1286                  * skip adding the timer int on secondary nodes, which causes
1287                  * a small but painful rift in the time-space continuum
1288                  */
1289                 if (multi_timer_check(apic, irq))
1290                         continue;
1291                 else
1292                         add_pin_to_irq(irq, apic, pin);
1293
1294                 if (!apic && !IO_APIC_IRQ(irq))
1295                         continue;
1296
1297                 if (IO_APIC_IRQ(irq)) {
1298                         vector = assign_irq_vector(irq);
1299                         entry.vector = vector;
1300                         ioapic_register_intr(irq, vector, IOAPIC_AUTO);
1301
1302                         if (!apic && (irq < 16))
1303                                 disable_8259A_irq(irq);
1304                 }
1305                 ioapic_write_entry(apic, pin, entry);
1306         }
1307         }
1308
1309         if (!first_notcon)
1310                 apic_printk(APIC_VERBOSE, " not connected.\n");
1311 }
1312
1313 /*
1314  * Set up the timer pin, possibly with the 8259A-master behind.
1315  */
1316 static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin,
1317                                         int vector)
1318 {
1319         struct IO_APIC_route_entry entry;
1320
1321         memset(&entry, 0, sizeof(entry));
1322
1323         /*
1324          * We use logical delivery to get the timer IRQ
1325          * to the first CPU.
1326          */
1327         entry.dest_mode = INT_DEST_MODE;
1328         entry.mask = 1;                                 /* mask IRQ now */
1329         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1330         entry.delivery_mode = INT_DELIVERY_MODE;
1331         entry.polarity = 0;
1332         entry.trigger = 0;
1333         entry.vector = vector;
1334
1335         /*
1336          * The timer IRQ doesn't have to know that behind the
1337          * scene we may have a 8259A-master in AEOI mode ...
1338          */
1339         ioapic_register_intr(0, vector, IOAPIC_EDGE);
1340
1341         /*
1342          * Add it to the IO-APIC irq-routing table:
1343          */
1344         ioapic_write_entry(apic, pin, entry);
1345 }
1346
1347
1348 __apicdebuginit(void) print_IO_APIC(void)
1349 {
1350         int apic, i;
1351         union IO_APIC_reg_00 reg_00;
1352         union IO_APIC_reg_01 reg_01;
1353         union IO_APIC_reg_02 reg_02;
1354         union IO_APIC_reg_03 reg_03;
1355         unsigned long flags;
1356
1357         if (apic_verbosity == APIC_QUIET)
1358                 return;
1359
1360         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1361         for (i = 0; i < nr_ioapics; i++)
1362                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1363                        mp_ioapics[i].mp_apicid, nr_ioapic_registers[i]);
1364
1365         /*
1366          * We are a bit conservative about what we expect.  We have to
1367          * know about every hardware change ASAP.
1368          */
1369         printk(KERN_INFO "testing the IO APIC.......................\n");
1370
1371         for (apic = 0; apic < nr_ioapics; apic++) {
1372
1373         spin_lock_irqsave(&ioapic_lock, flags);
1374         reg_00.raw = io_apic_read(apic, 0);
1375         reg_01.raw = io_apic_read(apic, 1);
1376         if (reg_01.bits.version >= 0x10)
1377                 reg_02.raw = io_apic_read(apic, 2);
1378         if (reg_01.bits.version >= 0x20)
1379                 reg_03.raw = io_apic_read(apic, 3);
1380         spin_unlock_irqrestore(&ioapic_lock, flags);
1381
1382         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mp_apicid);
1383         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1384         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
1385         printk(KERN_DEBUG ".......    : Delivery Type: %X\n", reg_00.bits.delivery_type);
1386         printk(KERN_DEBUG ".......    : LTS          : %X\n", reg_00.bits.LTS);
1387
1388         printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
1389         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
1390
1391         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
1392         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
1393
1394         /*
1395          * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1396          * but the value of reg_02 is read as the previous read register
1397          * value, so ignore it if reg_02 == reg_01.
1398          */
1399         if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1400                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1401                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
1402         }
1403
1404         /*
1405          * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1406          * or reg_03, but the value of reg_0[23] is read as the previous read
1407          * register value, so ignore it if reg_03 == reg_0[12].
1408          */
1409         if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1410             reg_03.raw != reg_01.raw) {
1411                 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1412                 printk(KERN_DEBUG ".......     : Boot DT    : %X\n", reg_03.bits.boot_DT);
1413         }
1414
1415         printk(KERN_DEBUG ".... IRQ redirection table:\n");
1416
1417         printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1418                           " Stat Dest Deli Vect:   \n");
1419
1420         for (i = 0; i <= reg_01.bits.entries; i++) {
1421                 struct IO_APIC_route_entry entry;
1422
1423                 entry = ioapic_read_entry(apic, i);
1424
1425                 printk(KERN_DEBUG " %02x %03X %02X  ",
1426                         i,
1427                         entry.dest.logical.logical_dest,
1428                         entry.dest.physical.physical_dest
1429                 );
1430
1431                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
1432                         entry.mask,
1433                         entry.trigger,
1434                         entry.irr,
1435                         entry.polarity,
1436                         entry.delivery_status,
1437                         entry.dest_mode,
1438                         entry.delivery_mode,
1439                         entry.vector
1440                 );
1441         }
1442         }
1443         printk(KERN_DEBUG "IRQ to pin mappings:\n");
1444         for (i = 0; i < NR_IRQS; i++) {
1445                 struct irq_pin_list *entry = irq_2_pin + i;
1446                 if (entry->pin < 0)
1447                         continue;
1448                 printk(KERN_DEBUG "IRQ%d ", i);
1449                 for (;;) {
1450                         printk("-> %d:%d", entry->apic, entry->pin);
1451                         if (!entry->next)
1452                                 break;
1453                         entry = irq_2_pin + entry->next;
1454                 }
1455                 printk("\n");
1456         }
1457
1458         printk(KERN_INFO ".................................... done.\n");
1459
1460         return;
1461 }
1462
1463 __apicdebuginit(void) print_APIC_bitfield(int base)
1464 {
1465         unsigned int v;
1466         int i, j;
1467
1468         if (apic_verbosity == APIC_QUIET)
1469                 return;
1470
1471         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1472         for (i = 0; i < 8; i++) {
1473                 v = apic_read(base + i*0x10);
1474                 for (j = 0; j < 32; j++) {
1475                         if (v & (1<<j))
1476                                 printk("1");
1477                         else
1478                                 printk("0");
1479                 }
1480                 printk("\n");
1481         }
1482 }
1483
1484 __apicdebuginit(void) print_local_APIC(void *dummy)
1485 {
1486         unsigned int v, ver, maxlvt;
1487         u64 icr;
1488
1489         if (apic_verbosity == APIC_QUIET)
1490                 return;
1491
1492         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1493                 smp_processor_id(), hard_smp_processor_id());
1494         v = apic_read(APIC_ID);
1495         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v,
1496                         GET_APIC_ID(v));
1497         v = apic_read(APIC_LVR);
1498         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1499         ver = GET_APIC_VERSION(v);
1500         maxlvt = lapic_get_maxlvt();
1501
1502         v = apic_read(APIC_TASKPRI);
1503         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1504
1505         if (APIC_INTEGRATED(ver)) {                     /* !82489DX */
1506                 v = apic_read(APIC_ARBPRI);
1507                 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1508                         v & APIC_ARBPRI_MASK);
1509                 v = apic_read(APIC_PROCPRI);
1510                 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1511         }
1512
1513         v = apic_read(APIC_EOI);
1514         printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1515         v = apic_read(APIC_RRR);
1516         printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1517         v = apic_read(APIC_LDR);
1518         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1519         v = apic_read(APIC_DFR);
1520         printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1521         v = apic_read(APIC_SPIV);
1522         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1523
1524         printk(KERN_DEBUG "... APIC ISR field:\n");
1525         print_APIC_bitfield(APIC_ISR);
1526         printk(KERN_DEBUG "... APIC TMR field:\n");
1527         print_APIC_bitfield(APIC_TMR);
1528         printk(KERN_DEBUG "... APIC IRR field:\n");
1529         print_APIC_bitfield(APIC_IRR);
1530
1531         if (APIC_INTEGRATED(ver)) {             /* !82489DX */
1532                 if (maxlvt > 3)         /* Due to the Pentium erratum 3AP. */
1533                         apic_write(APIC_ESR, 0);
1534                 v = apic_read(APIC_ESR);
1535                 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1536         }
1537
1538         icr = apic_icr_read();
1539         printk(KERN_DEBUG "... APIC ICR: %08x\n", icr);
1540         printk(KERN_DEBUG "... APIC ICR2: %08x\n", icr >> 32);
1541
1542         v = apic_read(APIC_LVTT);
1543         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1544
1545         if (maxlvt > 3) {                       /* PC is LVT#4. */
1546                 v = apic_read(APIC_LVTPC);
1547                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1548         }
1549         v = apic_read(APIC_LVT0);
1550         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1551         v = apic_read(APIC_LVT1);
1552         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1553
1554         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1555                 v = apic_read(APIC_LVTERR);
1556                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1557         }
1558
1559         v = apic_read(APIC_TMICT);
1560         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1561         v = apic_read(APIC_TMCCT);
1562         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1563         v = apic_read(APIC_TDCR);
1564         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1565         printk("\n");
1566 }
1567
1568 __apicdebuginit(void) print_all_local_APICs(void)
1569 {
1570         on_each_cpu(print_local_APIC, NULL, 1);
1571 }
1572
1573 __apicdebuginit(void) print_PIC(void)
1574 {
1575         unsigned int v;
1576         unsigned long flags;
1577
1578         if (apic_verbosity == APIC_QUIET)
1579                 return;
1580
1581         printk(KERN_DEBUG "\nprinting PIC contents\n");
1582
1583         spin_lock_irqsave(&i8259A_lock, flags);
1584
1585         v = inb(0xa1) << 8 | inb(0x21);
1586         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1587
1588         v = inb(0xa0) << 8 | inb(0x20);
1589         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1590
1591         outb(0x0b, 0xa0);
1592         outb(0x0b, 0x20);
1593         v = inb(0xa0) << 8 | inb(0x20);
1594         outb(0x0a, 0xa0);
1595         outb(0x0a, 0x20);
1596
1597         spin_unlock_irqrestore(&i8259A_lock, flags);
1598
1599         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1600
1601         v = inb(0x4d1) << 8 | inb(0x4d0);
1602         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1603 }
1604
1605 __apicdebuginit(int) print_all_ICs(void)
1606 {
1607         print_PIC();
1608         print_all_local_APICs();
1609         print_IO_APIC();
1610
1611         return 0;
1612 }
1613
1614 fs_initcall(print_all_ICs);
1615
1616
1617 static void __init enable_IO_APIC(void)
1618 {
1619         union IO_APIC_reg_01 reg_01;
1620         int i8259_apic, i8259_pin;
1621         int i, apic;
1622         unsigned long flags;
1623
1624         for (i = 0; i < PIN_MAP_SIZE; i++) {
1625                 irq_2_pin[i].pin = -1;
1626                 irq_2_pin[i].next = 0;
1627         }
1628         if (!pirqs_enabled)
1629                 for (i = 0; i < MAX_PIRQS; i++)
1630                         pirq_entries[i] = -1;
1631
1632         /*
1633          * The number of IO-APIC IRQ registers (== #pins):
1634          */
1635         for (apic = 0; apic < nr_ioapics; apic++) {
1636                 spin_lock_irqsave(&ioapic_lock, flags);
1637                 reg_01.raw = io_apic_read(apic, 1);
1638                 spin_unlock_irqrestore(&ioapic_lock, flags);
1639                 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1640         }
1641         for (apic = 0; apic < nr_ioapics; apic++) {
1642                 int pin;
1643                 /* See if any of the pins is in ExtINT mode */
1644                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1645                         struct IO_APIC_route_entry entry;
1646                         entry = ioapic_read_entry(apic, pin);
1647
1648
1649                         /* If the interrupt line is enabled and in ExtInt mode
1650                          * I have found the pin where the i8259 is connected.
1651                          */
1652                         if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1653                                 ioapic_i8259.apic = apic;
1654                                 ioapic_i8259.pin  = pin;
1655                                 goto found_i8259;
1656                         }
1657                 }
1658         }
1659  found_i8259:
1660         /* Look to see what if the MP table has reported the ExtINT */
1661         /* If we could not find the appropriate pin by looking at the ioapic
1662          * the i8259 probably is not connected the ioapic but give the
1663          * mptable a chance anyway.
1664          */
1665         i8259_pin  = find_isa_irq_pin(0, mp_ExtINT);
1666         i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1667         /* Trust the MP table if nothing is setup in the hardware */
1668         if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1669                 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1670                 ioapic_i8259.pin  = i8259_pin;
1671                 ioapic_i8259.apic = i8259_apic;
1672         }
1673         /* Complain if the MP table and the hardware disagree */
1674         if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1675                 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1676         {
1677                 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1678         }
1679
1680         /*
1681          * Do not trust the IO-APIC being empty at bootup
1682          */
1683         clear_IO_APIC();
1684 }
1685
1686 /*
1687  * Not an __init, needed by the reboot code
1688  */
1689 void disable_IO_APIC(void)
1690 {
1691         /*
1692          * Clear the IO-APIC before rebooting:
1693          */
1694         clear_IO_APIC();
1695
1696         /*
1697          * If the i8259 is routed through an IOAPIC
1698          * Put that IOAPIC in virtual wire mode
1699          * so legacy interrupts can be delivered.
1700          */
1701         if (ioapic_i8259.pin != -1) {
1702                 struct IO_APIC_route_entry entry;
1703
1704                 memset(&entry, 0, sizeof(entry));
1705                 entry.mask            = 0; /* Enabled */
1706                 entry.trigger         = 0; /* Edge */
1707                 entry.irr             = 0;
1708                 entry.polarity        = 0; /* High */
1709                 entry.delivery_status = 0;
1710                 entry.dest_mode       = 0; /* Physical */
1711                 entry.delivery_mode   = dest_ExtINT; /* ExtInt */
1712                 entry.vector          = 0;
1713                 entry.dest.physical.physical_dest = read_apic_id();
1714
1715                 /*
1716                  * Add it to the IO-APIC irq-routing table:
1717                  */
1718                 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1719         }
1720         disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1721 }
1722
1723 /*
1724  * function to set the IO-APIC physical IDs based on the
1725  * values stored in the MPC table.
1726  *
1727  * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
1728  */
1729
1730 static void __init setup_ioapic_ids_from_mpc(void)
1731 {
1732         union IO_APIC_reg_00 reg_00;
1733         physid_mask_t phys_id_present_map;
1734         int apic;
1735         int i;
1736         unsigned char old_id;
1737         unsigned long flags;
1738
1739         if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids())
1740                 return;
1741
1742         /*
1743          * Don't check I/O APIC IDs for xAPIC systems.  They have
1744          * no meaning without the serial APIC bus.
1745          */
1746         if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1747                 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
1748                 return;
1749         /*
1750          * This is broken; anything with a real cpu count has to
1751          * circumvent this idiocy regardless.
1752          */
1753         phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1754
1755         /*
1756          * Set the IOAPIC ID to the value stored in the MPC table.
1757          */
1758         for (apic = 0; apic < nr_ioapics; apic++) {
1759
1760                 /* Read the register 0 value */
1761                 spin_lock_irqsave(&ioapic_lock, flags);
1762                 reg_00.raw = io_apic_read(apic, 0);
1763                 spin_unlock_irqrestore(&ioapic_lock, flags);
1764
1765                 old_id = mp_ioapics[apic].mp_apicid;
1766
1767                 if (mp_ioapics[apic].mp_apicid >= get_physical_broadcast()) {
1768                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1769                                 apic, mp_ioapics[apic].mp_apicid);
1770                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1771                                 reg_00.bits.ID);
1772                         mp_ioapics[apic].mp_apicid = reg_00.bits.ID;
1773                 }
1774
1775                 /*
1776                  * Sanity check, is the ID really free? Every APIC in a
1777                  * system must have a unique ID or we get lots of nice
1778                  * 'stuck on smp_invalidate_needed IPI wait' messages.
1779                  */
1780                 if (check_apicid_used(phys_id_present_map,
1781                                         mp_ioapics[apic].mp_apicid)) {
1782                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1783                                 apic, mp_ioapics[apic].mp_apicid);
1784                         for (i = 0; i < get_physical_broadcast(); i++)
1785                                 if (!physid_isset(i, phys_id_present_map))
1786                                         break;
1787                         if (i >= get_physical_broadcast())
1788                                 panic("Max APIC ID exceeded!\n");
1789                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1790                                 i);
1791                         physid_set(i, phys_id_present_map);
1792                         mp_ioapics[apic].mp_apicid = i;
1793                 } else {
1794                         physid_mask_t tmp;
1795                         tmp = apicid_to_cpu_present(mp_ioapics[apic].mp_apicid);
1796                         apic_printk(APIC_VERBOSE, "Setting %d in the "
1797                                         "phys_id_present_map\n",
1798                                         mp_ioapics[apic].mp_apicid);
1799                         physids_or(phys_id_present_map, phys_id_present_map, tmp);
1800                 }
1801
1802
1803                 /*
1804                  * We need to adjust the IRQ routing table
1805                  * if the ID changed.
1806                  */
1807                 if (old_id != mp_ioapics[apic].mp_apicid)
1808                         for (i = 0; i < mp_irq_entries; i++)
1809                                 if (mp_irqs[i].mp_dstapic == old_id)
1810                                         mp_irqs[i].mp_dstapic
1811                                                 = mp_ioapics[apic].mp_apicid;
1812
1813                 /*
1814                  * Read the right value from the MPC table and
1815                  * write it into the ID register.
1816                  */
1817                 apic_printk(APIC_VERBOSE, KERN_INFO
1818                         "...changing IO-APIC physical APIC ID to %d ...",
1819                         mp_ioapics[apic].mp_apicid);
1820
1821                 reg_00.bits.ID = mp_ioapics[apic].mp_apicid;
1822                 spin_lock_irqsave(&ioapic_lock, flags);
1823                 io_apic_write(apic, 0, reg_00.raw);
1824                 spin_unlock_irqrestore(&ioapic_lock, flags);
1825
1826                 /*
1827                  * Sanity check
1828                  */
1829                 spin_lock_irqsave(&ioapic_lock, flags);
1830                 reg_00.raw = io_apic_read(apic, 0);
1831                 spin_unlock_irqrestore(&ioapic_lock, flags);
1832                 if (reg_00.bits.ID != mp_ioapics[apic].mp_apicid)
1833                         printk("could not set ID!\n");
1834                 else
1835                         apic_printk(APIC_VERBOSE, " ok.\n");
1836         }
1837 }
1838
1839 int no_timer_check __initdata;
1840
1841 static int __init notimercheck(char *s)
1842 {
1843         no_timer_check = 1;
1844         return 1;
1845 }
1846 __setup("no_timer_check", notimercheck);
1847
1848 /*
1849  * There is a nasty bug in some older SMP boards, their mptable lies
1850  * about the timer IRQ. We do the following to work around the situation:
1851  *
1852  *      - timer IRQ defaults to IO-APIC IRQ
1853  *      - if this function detects that timer IRQs are defunct, then we fall
1854  *        back to ISA timer IRQs
1855  */
1856 static int __init timer_irq_works(void)
1857 {
1858         unsigned long t1 = jiffies;
1859         unsigned long flags;
1860
1861         if (no_timer_check)
1862                 return 1;
1863
1864         local_save_flags(flags);
1865         local_irq_enable();
1866         /* Let ten ticks pass... */
1867         mdelay((10 * 1000) / HZ);
1868         local_irq_restore(flags);
1869
1870         /*
1871          * Expect a few ticks at least, to be sure some possible
1872          * glue logic does not lock up after one or two first
1873          * ticks in a non-ExtINT mode.  Also the local APIC
1874          * might have cached one ExtINT interrupt.  Finally, at
1875          * least one tick may be lost due to delays.
1876          */
1877         if (time_after(jiffies, t1 + 4))
1878                 return 1;
1879
1880         return 0;
1881 }
1882
1883 /*
1884  * In the SMP+IOAPIC case it might happen that there are an unspecified
1885  * number of pending IRQ events unhandled. These cases are very rare,
1886  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1887  * better to do it this way as thus we do not have to be aware of
1888  * 'pending' interrupts in the IRQ path, except at this point.
1889  */
1890 /*
1891  * Edge triggered needs to resend any interrupt
1892  * that was delayed but this is now handled in the device
1893  * independent code.
1894  */
1895
1896 /*
1897  * Startup quirk:
1898  *
1899  * Starting up a edge-triggered IO-APIC interrupt is
1900  * nasty - we need to make sure that we get the edge.
1901  * If it is already asserted for some reason, we need
1902  * return 1 to indicate that is was pending.
1903  *
1904  * This is not complete - we should be able to fake
1905  * an edge even if it isn't on the 8259A...
1906  *
1907  * (We do this for level-triggered IRQs too - it cannot hurt.)
1908  */
1909 static unsigned int startup_ioapic_irq(unsigned int irq)
1910 {
1911         int was_pending = 0;
1912         unsigned long flags;
1913
1914         spin_lock_irqsave(&ioapic_lock, flags);
1915         if (irq < 16) {
1916                 disable_8259A_irq(irq);
1917                 if (i8259A_irq_pending(irq))
1918                         was_pending = 1;
1919         }
1920         __unmask_IO_APIC_irq(irq);
1921         spin_unlock_irqrestore(&ioapic_lock, flags);
1922
1923         return was_pending;
1924 }
1925
1926 static void ack_ioapic_irq(unsigned int irq)
1927 {
1928         move_native_irq(irq);
1929         ack_APIC_irq();
1930 }
1931
1932 static void ack_ioapic_quirk_irq(unsigned int irq)
1933 {
1934         unsigned long v;
1935         int i;
1936
1937         move_native_irq(irq);
1938 /*
1939  * It appears there is an erratum which affects at least version 0x11
1940  * of I/O APIC (that's the 82093AA and cores integrated into various
1941  * chipsets).  Under certain conditions a level-triggered interrupt is
1942  * erroneously delivered as edge-triggered one but the respective IRR
1943  * bit gets set nevertheless.  As a result the I/O unit expects an EOI
1944  * message but it will never arrive and further interrupts are blocked
1945  * from the source.  The exact reason is so far unknown, but the
1946  * phenomenon was observed when two consecutive interrupt requests
1947  * from a given source get delivered to the same CPU and the source is
1948  * temporarily disabled in between.
1949  *
1950  * A workaround is to simulate an EOI message manually.  We achieve it
1951  * by setting the trigger mode to edge and then to level when the edge
1952  * trigger mode gets detected in the TMR of a local APIC for a
1953  * level-triggered interrupt.  We mask the source for the time of the
1954  * operation to prevent an edge-triggered interrupt escaping meanwhile.
1955  * The idea is from Manfred Spraul.  --macro
1956  */
1957         i = irq_vector[irq];
1958
1959         v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1960
1961         ack_APIC_irq();
1962
1963         if (!(v & (1 << (i & 0x1f)))) {
1964                 atomic_inc(&irq_mis_count);
1965                 spin_lock(&ioapic_lock);
1966                 __mask_and_edge_IO_APIC_irq(irq);
1967                 __unmask_and_level_IO_APIC_irq(irq);
1968                 spin_unlock(&ioapic_lock);
1969         }
1970 }
1971
1972 static int ioapic_retrigger_irq(unsigned int irq)
1973 {
1974         send_IPI_self(irq_vector[irq]);
1975
1976         return 1;
1977 }
1978
1979 static struct irq_chip ioapic_chip __read_mostly = {
1980         .name           = "IO-APIC",
1981         .startup        = startup_ioapic_irq,
1982         .mask           = mask_IO_APIC_irq,
1983         .unmask         = unmask_IO_APIC_irq,
1984         .ack            = ack_ioapic_irq,
1985         .eoi            = ack_ioapic_quirk_irq,
1986 #ifdef CONFIG_SMP
1987         .set_affinity   = set_ioapic_affinity_irq,
1988 #endif
1989         .retrigger      = ioapic_retrigger_irq,
1990 };
1991
1992
1993 static inline void init_IO_APIC_traps(void)
1994 {
1995         int irq;
1996
1997         /*
1998          * NOTE! The local APIC isn't very good at handling
1999          * multiple interrupts at the same interrupt level.
2000          * As the interrupt level is determined by taking the
2001          * vector number and shifting that right by 4, we
2002          * want to spread these out a bit so that they don't
2003          * all fall in the same interrupt level.
2004          *
2005          * Also, we've got to be careful not to trash gate
2006          * 0x80, because int 0x80 is hm, kind of importantish. ;)
2007          */
2008         for (irq = 0; irq < NR_IRQS ; irq++) {
2009                 if (IO_APIC_IRQ(irq) && !irq_vector[irq]) {
2010                         /*
2011                          * Hmm.. We don't have an entry for this,
2012                          * so default to an old-fashioned 8259
2013                          * interrupt if we can..
2014                          */
2015                         if (irq < 16)
2016                                 make_8259A_irq(irq);
2017                         else
2018                                 /* Strange. Oh, well.. */
2019                                 irq_desc[irq].chip = &no_irq_chip;
2020                 }
2021         }
2022 }
2023
2024 /*
2025  * The local APIC irq-chip implementation:
2026  */
2027
2028 static void ack_lapic_irq(unsigned int irq)
2029 {
2030         ack_APIC_irq();
2031 }
2032
2033 static void mask_lapic_irq(unsigned int irq)
2034 {
2035         unsigned long v;
2036
2037         v = apic_read(APIC_LVT0);
2038         apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2039 }
2040
2041 static void unmask_lapic_irq(unsigned int irq)
2042 {
2043         unsigned long v;
2044
2045         v = apic_read(APIC_LVT0);
2046         apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2047 }
2048
2049 static struct irq_chip lapic_chip __read_mostly = {
2050         .name           = "local-APIC",
2051         .mask           = mask_lapic_irq,
2052         .unmask         = unmask_lapic_irq,
2053         .ack            = ack_lapic_irq,
2054 };
2055
2056 static void lapic_register_intr(int irq, int vector)
2057 {
2058         irq_desc[irq].status &= ~IRQ_LEVEL;
2059         set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2060                                       "edge");
2061         set_intr_gate(vector, interrupt[irq]);
2062 }
2063
2064 static void __init setup_nmi(void)
2065 {
2066         /*
2067          * Dirty trick to enable the NMI watchdog ...
2068          * We put the 8259A master into AEOI mode and
2069          * unmask on all local APICs LVT0 as NMI.
2070          *
2071          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2072          * is from Maciej W. Rozycki - so we do not have to EOI from
2073          * the NMI handler or the timer interrupt.
2074          */
2075         apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2076
2077         enable_NMI_through_LVT0();
2078
2079         apic_printk(APIC_VERBOSE, " done.\n");
2080 }
2081
2082 /*
2083  * This looks a bit hackish but it's about the only one way of sending
2084  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
2085  * not support the ExtINT mode, unfortunately.  We need to send these
2086  * cycles as some i82489DX-based boards have glue logic that keeps the
2087  * 8259A interrupt line asserted until INTA.  --macro
2088  */
2089 static inline void __init unlock_ExtINT_logic(void)
2090 {
2091         int apic, pin, i;
2092         struct IO_APIC_route_entry entry0, entry1;
2093         unsigned char save_control, save_freq_select;
2094
2095         pin  = find_isa_irq_pin(8, mp_INT);
2096         if (pin == -1) {
2097                 WARN_ON_ONCE(1);
2098                 return;
2099         }
2100         apic = find_isa_irq_apic(8, mp_INT);
2101         if (apic == -1) {
2102                 WARN_ON_ONCE(1);
2103                 return;
2104         }
2105
2106         entry0 = ioapic_read_entry(apic, pin);
2107         clear_IO_APIC_pin(apic, pin);
2108
2109         memset(&entry1, 0, sizeof(entry1));
2110
2111         entry1.dest_mode = 0;                   /* physical delivery */
2112         entry1.mask = 0;                        /* unmask IRQ now */
2113         entry1.dest.physical.physical_dest = hard_smp_processor_id();
2114         entry1.delivery_mode = dest_ExtINT;
2115         entry1.polarity = entry0.polarity;
2116         entry1.trigger = 0;
2117         entry1.vector = 0;
2118
2119         ioapic_write_entry(apic, pin, entry1);
2120
2121         save_control = CMOS_READ(RTC_CONTROL);
2122         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2123         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2124                    RTC_FREQ_SELECT);
2125         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2126
2127         i = 100;
2128         while (i-- > 0) {
2129                 mdelay(10);
2130                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2131                         i -= 10;
2132         }
2133
2134         CMOS_WRITE(save_control, RTC_CONTROL);
2135         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2136         clear_IO_APIC_pin(apic, pin);
2137
2138         ioapic_write_entry(apic, pin, entry0);
2139 }
2140
2141 /*
2142  * This code may look a bit paranoid, but it's supposed to cooperate with
2143  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
2144  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
2145  * fanatically on his truly buggy board.
2146  */
2147 static inline void __init check_timer(void)
2148 {
2149         int apic1, pin1, apic2, pin2;
2150         int no_pin1 = 0;
2151         int vector;
2152         unsigned int ver;
2153         unsigned long flags;
2154
2155         local_irq_save(flags);
2156
2157         ver = apic_read(APIC_LVR);
2158         ver = GET_APIC_VERSION(ver);
2159
2160         /*
2161          * get/set the timer IRQ vector:
2162          */
2163         disable_8259A_irq(0);
2164         vector = assign_irq_vector(0);
2165         set_intr_gate(vector, interrupt[0]);
2166
2167         /*
2168          * As IRQ0 is to be enabled in the 8259A, the virtual
2169          * wire has to be disabled in the local APIC.  Also
2170          * timer interrupts need to be acknowledged manually in
2171          * the 8259A for the i82489DX when using the NMI
2172          * watchdog as that APIC treats NMIs as level-triggered.
2173          * The AEOI mode will finish them in the 8259A
2174          * automatically.
2175          */
2176         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2177         init_8259A(1);
2178         timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
2179
2180         pin1  = find_isa_irq_pin(0, mp_INT);
2181         apic1 = find_isa_irq_apic(0, mp_INT);
2182         pin2  = ioapic_i8259.pin;
2183         apic2 = ioapic_i8259.apic;
2184
2185         apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2186                     "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2187                     vector, apic1, pin1, apic2, pin2);
2188
2189         /*
2190          * Some BIOS writers are clueless and report the ExtINTA
2191          * I/O APIC input from the cascaded 8259A as the timer
2192          * interrupt input.  So just in case, if only one pin
2193          * was found above, try it both directly and through the
2194          * 8259A.
2195          */
2196         if (pin1 == -1) {
2197                 pin1 = pin2;
2198                 apic1 = apic2;
2199                 no_pin1 = 1;
2200         } else if (pin2 == -1) {
2201                 pin2 = pin1;
2202                 apic2 = apic1;
2203         }
2204
2205         if (pin1 != -1) {
2206                 /*
2207                  * Ok, does IRQ0 through the IOAPIC work?
2208                  */
2209                 if (no_pin1) {
2210                         add_pin_to_irq(0, apic1, pin1);
2211                         setup_timer_IRQ0_pin(apic1, pin1, vector);
2212                 }
2213                 unmask_IO_APIC_irq(0);
2214                 if (timer_irq_works()) {
2215                         if (nmi_watchdog == NMI_IO_APIC) {
2216                                 setup_nmi();
2217                                 enable_8259A_irq(0);
2218                         }
2219                         if (disable_timer_pin_1 > 0)
2220                                 clear_IO_APIC_pin(0, pin1);
2221                         goto out;
2222                 }
2223                 clear_IO_APIC_pin(apic1, pin1);
2224                 if (!no_pin1)
2225                         apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2226                                     "8254 timer not connected to IO-APIC\n");
2227
2228                 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2229                             "(IRQ0) through the 8259A ...\n");
2230                 apic_printk(APIC_QUIET, KERN_INFO
2231                             "..... (found apic %d pin %d) ...\n", apic2, pin2);
2232                 /*
2233                  * legacy devices should be connected to IO APIC #0
2234                  */
2235                 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
2236                 setup_timer_IRQ0_pin(apic2, pin2, vector);
2237                 unmask_IO_APIC_irq(0);
2238                 enable_8259A_irq(0);
2239                 if (timer_irq_works()) {
2240                         apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2241                         timer_through_8259 = 1;
2242                         if (nmi_watchdog == NMI_IO_APIC) {
2243                                 disable_8259A_irq(0);
2244                                 setup_nmi();
2245                                 enable_8259A_irq(0);
2246                         }
2247                         goto out;
2248                 }
2249                 /*
2250                  * Cleanup, just in case ...
2251                  */
2252                 disable_8259A_irq(0);
2253                 clear_IO_APIC_pin(apic2, pin2);
2254                 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2255         }
2256
2257         if (nmi_watchdog == NMI_IO_APIC) {
2258                 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
2259                             "through the IO-APIC - disabling NMI Watchdog!\n");
2260                 nmi_watchdog = NMI_NONE;
2261         }
2262         timer_ack = 0;
2263
2264         apic_printk(APIC_QUIET, KERN_INFO
2265                     "...trying to set up timer as Virtual Wire IRQ...\n");
2266
2267         lapic_register_intr(0, vector);
2268         apic_write(APIC_LVT0, APIC_DM_FIXED | vector);  /* Fixed mode */
2269         enable_8259A_irq(0);
2270
2271         if (timer_irq_works()) {
2272                 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2273                 goto out;
2274         }
2275         disable_8259A_irq(0);
2276         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
2277         apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
2278
2279         apic_printk(APIC_QUIET, KERN_INFO
2280                     "...trying to set up timer as ExtINT IRQ...\n");
2281
2282         init_8259A(0);
2283         make_8259A_irq(0);
2284         apic_write(APIC_LVT0, APIC_DM_EXTINT);
2285
2286         unlock_ExtINT_logic();
2287
2288         if (timer_irq_works()) {
2289                 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2290                 goto out;
2291         }
2292         apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
2293         panic("IO-APIC + timer doesn't work!  Boot with apic=debug and send a "
2294                 "report.  Then try booting with the 'noapic' option.\n");
2295 out:
2296         local_irq_restore(flags);
2297 }
2298
2299 /*
2300  * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2301  * to devices.  However there may be an I/O APIC pin available for
2302  * this interrupt regardless.  The pin may be left unconnected, but
2303  * typically it will be reused as an ExtINT cascade interrupt for
2304  * the master 8259A.  In the MPS case such a pin will normally be
2305  * reported as an ExtINT interrupt in the MP table.  With ACPI
2306  * there is no provision for ExtINT interrupts, and in the absence
2307  * of an override it would be treated as an ordinary ISA I/O APIC
2308  * interrupt, that is edge-triggered and unmasked by default.  We
2309  * used to do this, but it caused problems on some systems because
2310  * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2311  * the same ExtINT cascade interrupt to drive the local APIC of the
2312  * bootstrap processor.  Therefore we refrain from routing IRQ2 to
2313  * the I/O APIC in all cases now.  No actual device should request
2314  * it anyway.  --macro
2315  */
2316 #define PIC_IRQS        (1 << PIC_CASCADE_IR)
2317
2318 void __init setup_IO_APIC(void)
2319 {
2320         int i;
2321
2322         /* Reserve all the system vectors. */
2323         for (i = first_system_vector; i < NR_VECTORS; i++)
2324                 set_bit(i, used_vectors);
2325
2326         enable_IO_APIC();
2327
2328         io_apic_irqs = ~PIC_IRQS;
2329
2330         printk("ENABLING IO-APIC IRQs\n");
2331
2332         /*
2333          * Set up IO-APIC IRQ routing.
2334          */
2335         if (!acpi_ioapic)
2336                 setup_ioapic_ids_from_mpc();
2337         sync_Arb_IDs();
2338         setup_IO_APIC_irqs();
2339         init_IO_APIC_traps();
2340         check_timer();
2341 }
2342
2343 /*
2344  *      Called after all the initialization is done. If we didnt find any
2345  *      APIC bugs then we can allow the modify fast path
2346  */
2347
2348 static int __init io_apic_bug_finalize(void)
2349 {
2350         if (sis_apic_bug == -1)
2351                 sis_apic_bug = 0;
2352         return 0;
2353 }
2354
2355 late_initcall(io_apic_bug_finalize);
2356
2357 struct sysfs_ioapic_data {
2358         struct sys_device dev;
2359         struct IO_APIC_route_entry entry[0];
2360 };
2361 static struct sysfs_ioapic_data *mp_ioapic_data[MAX_IO_APICS];
2362
2363 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2364 {
2365         struct IO_APIC_route_entry *entry;
2366         struct sysfs_ioapic_data *data;
2367         int i;
2368
2369         data = container_of(dev, struct sysfs_ioapic_data, dev);
2370         entry = data->entry;
2371         for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
2372                 entry[i] = ioapic_read_entry(dev->id, i);
2373
2374         return 0;
2375 }
2376
2377 static int ioapic_resume(struct sys_device *dev)
2378 {
2379         struct IO_APIC_route_entry *entry;
2380         struct sysfs_ioapic_data *data;
2381         unsigned long flags;
2382         union IO_APIC_reg_00 reg_00;
2383         int i;
2384
2385         data = container_of(dev, struct sysfs_ioapic_data, dev);
2386         entry = data->entry;
2387
2388         spin_lock_irqsave(&ioapic_lock, flags);
2389         reg_00.raw = io_apic_read(dev->id, 0);
2390         if (reg_00.bits.ID != mp_ioapics[dev->id].mp_apicid) {
2391                 reg_00.bits.ID = mp_ioapics[dev->id].mp_apicid;
2392                 io_apic_write(dev->id, 0, reg_00.raw);
2393         }
2394         spin_unlock_irqrestore(&ioapic_lock, flags);
2395         for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
2396                 ioapic_write_entry(dev->id, i, entry[i]);
2397
2398         return 0;
2399 }
2400
2401 static struct sysdev_class ioapic_sysdev_class = {
2402         .name = "ioapic",
2403         .suspend = ioapic_suspend,
2404         .resume = ioapic_resume,
2405 };
2406
2407 static int __init ioapic_init_sysfs(void)
2408 {
2409         struct sys_device *dev;
2410         int i, size, error = 0;
2411
2412         error = sysdev_class_register(&ioapic_sysdev_class);
2413         if (error)
2414                 return error;
2415
2416         for (i = 0; i < nr_ioapics; i++) {
2417                 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2418                         * sizeof(struct IO_APIC_route_entry);
2419                 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
2420                 if (!mp_ioapic_data[i]) {
2421                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2422                         continue;
2423                 }
2424                 dev = &mp_ioapic_data[i]->dev;
2425                 dev->id = i;
2426                 dev->cls = &ioapic_sysdev_class;
2427                 error = sysdev_register(dev);
2428                 if (error) {
2429                         kfree(mp_ioapic_data[i]);
2430                         mp_ioapic_data[i] = NULL;
2431                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2432                         continue;
2433                 }
2434         }
2435
2436         return 0;
2437 }
2438
2439 device_initcall(ioapic_init_sysfs);
2440
2441 /*
2442  * Dynamic irq allocate and deallocation
2443  */
2444 int create_irq(void)
2445 {
2446         /* Allocate an unused irq */
2447         int irq, new, vector = 0;
2448         unsigned long flags;
2449
2450         irq = -ENOSPC;
2451         spin_lock_irqsave(&vector_lock, flags);
2452         for (new = (NR_IRQS - 1); new >= 0; new--) {
2453                 if (platform_legacy_irq(new))
2454                         continue;
2455                 if (irq_vector[new] != 0)
2456                         continue;
2457                 vector = __assign_irq_vector(new);
2458                 if (likely(vector > 0))
2459                         irq = new;
2460                 break;
2461         }
2462         spin_unlock_irqrestore(&vector_lock, flags);
2463
2464         if (irq >= 0) {
2465                 set_intr_gate(vector, interrupt[irq]);
2466                 dynamic_irq_init(irq);
2467         }
2468         return irq;
2469 }
2470
2471 void destroy_irq(unsigned int irq)
2472 {
2473         unsigned long flags;
2474
2475         dynamic_irq_cleanup(irq);
2476
2477         spin_lock_irqsave(&vector_lock, flags);
2478         clear_bit(irq_vector[irq], used_vectors);
2479         irq_vector[irq] = 0;
2480         spin_unlock_irqrestore(&vector_lock, flags);
2481 }
2482
2483 /*
2484  * MSI message composition
2485  */
2486 #ifdef CONFIG_PCI_MSI
2487 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
2488 {
2489         int vector;
2490         unsigned dest;
2491
2492         vector = assign_irq_vector(irq);
2493         if (vector >= 0) {
2494                 dest = cpu_mask_to_apicid(TARGET_CPUS);
2495
2496                 msg->address_hi = MSI_ADDR_BASE_HI;
2497                 msg->address_lo =
2498                         MSI_ADDR_BASE_LO |
2499                         ((INT_DEST_MODE == 0) ?
2500 MSI_ADDR_DEST_MODE_PHYSICAL:
2501                                 MSI_ADDR_DEST_MODE_LOGICAL) |
2502                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2503                                 MSI_ADDR_REDIRECTION_CPU:
2504                                 MSI_ADDR_REDIRECTION_LOWPRI) |
2505                         MSI_ADDR_DEST_ID(dest);
2506
2507                 msg->data =
2508                         MSI_DATA_TRIGGER_EDGE |
2509                         MSI_DATA_LEVEL_ASSERT |
2510                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2511 MSI_DATA_DELIVERY_FIXED:
2512                                 MSI_DATA_DELIVERY_LOWPRI) |
2513                         MSI_DATA_VECTOR(vector);
2514         }
2515         return vector;
2516 }
2517
2518 #ifdef CONFIG_SMP
2519 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
2520 {
2521         struct msi_msg msg;
2522         unsigned int dest;
2523         cpumask_t tmp;
2524         int vector;
2525
2526         cpus_and(tmp, mask, cpu_online_map);
2527         if (cpus_empty(tmp))
2528                 tmp = TARGET_CPUS;
2529
2530         vector = assign_irq_vector(irq);
2531         if (vector < 0)
2532                 return;
2533
2534         dest = cpu_mask_to_apicid(mask);
2535
2536         read_msi_msg(irq, &msg);
2537
2538         msg.data &= ~MSI_DATA_VECTOR_MASK;
2539         msg.data |= MSI_DATA_VECTOR(vector);
2540         msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2541         msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2542
2543         write_msi_msg(irq, &msg);
2544         irq_desc[irq].affinity = mask;
2545 }
2546 #endif /* CONFIG_SMP */
2547
2548 /*
2549  * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2550  * which implement the MSI or MSI-X Capability Structure.
2551  */
2552 static struct irq_chip msi_chip = {
2553         .name           = "PCI-MSI",
2554         .unmask         = unmask_msi_irq,
2555         .mask           = mask_msi_irq,
2556         .ack            = ack_ioapic_irq,
2557 #ifdef CONFIG_SMP
2558         .set_affinity   = set_msi_irq_affinity,
2559 #endif
2560         .retrigger      = ioapic_retrigger_irq,
2561 };
2562
2563 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
2564 {
2565         struct msi_msg msg;
2566         int irq, ret;
2567         irq = create_irq();
2568         if (irq < 0)
2569                 return irq;
2570
2571         ret = msi_compose_msg(dev, irq, &msg);
2572         if (ret < 0) {
2573                 destroy_irq(irq);
2574                 return ret;
2575         }
2576
2577         set_irq_msi(irq, desc);
2578         write_msi_msg(irq, &msg);
2579
2580         set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq,
2581                                       "edge");
2582
2583         return 0;
2584 }
2585
2586 void arch_teardown_msi_irq(unsigned int irq)
2587 {
2588         destroy_irq(irq);
2589 }
2590
2591 #endif /* CONFIG_PCI_MSI */
2592
2593 /*
2594  * Hypertransport interrupt support
2595  */
2596 #ifdef CONFIG_HT_IRQ
2597
2598 #ifdef CONFIG_SMP
2599
2600 static void target_ht_irq(unsigned int irq, unsigned int dest)
2601 {
2602         struct ht_irq_msg msg;
2603         fetch_ht_irq_msg(irq, &msg);
2604
2605         msg.address_lo &= ~(HT_IRQ_LOW_DEST_ID_MASK);
2606         msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
2607
2608         msg.address_lo |= HT_IRQ_LOW_DEST_ID(dest);
2609         msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
2610
2611         write_ht_irq_msg(irq, &msg);
2612 }
2613
2614 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
2615 {
2616         unsigned int dest;
2617         cpumask_t tmp;
2618
2619         cpus_and(tmp, mask, cpu_online_map);
2620         if (cpus_empty(tmp))
2621                 tmp = TARGET_CPUS;
2622
2623         cpus_and(mask, tmp, CPU_MASK_ALL);
2624
2625         dest = cpu_mask_to_apicid(mask);
2626
2627         target_ht_irq(irq, dest);
2628         irq_desc[irq].affinity = mask;
2629 }
2630 #endif
2631
2632 static struct irq_chip ht_irq_chip = {
2633         .name           = "PCI-HT",
2634         .mask           = mask_ht_irq,
2635         .unmask         = unmask_ht_irq,
2636         .ack            = ack_ioapic_irq,
2637 #ifdef CONFIG_SMP
2638         .set_affinity   = set_ht_irq_affinity,
2639 #endif
2640         .retrigger      = ioapic_retrigger_irq,
2641 };
2642
2643 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2644 {
2645         int vector;
2646
2647         vector = assign_irq_vector(irq);
2648         if (vector >= 0) {
2649                 struct ht_irq_msg msg;
2650                 unsigned dest;
2651                 cpumask_t tmp;
2652
2653                 cpus_clear(tmp);
2654                 cpu_set(vector >> 8, tmp);
2655                 dest = cpu_mask_to_apicid(tmp);
2656
2657                 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
2658
2659                 msg.address_lo =
2660                         HT_IRQ_LOW_BASE |
2661                         HT_IRQ_LOW_DEST_ID(dest) |
2662                         HT_IRQ_LOW_VECTOR(vector) |
2663                         ((INT_DEST_MODE == 0) ?
2664                                 HT_IRQ_LOW_DM_PHYSICAL :
2665                                 HT_IRQ_LOW_DM_LOGICAL) |
2666                         HT_IRQ_LOW_RQEOI_EDGE |
2667                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2668                                 HT_IRQ_LOW_MT_FIXED :
2669                                 HT_IRQ_LOW_MT_ARBITRATED) |
2670                         HT_IRQ_LOW_IRQ_MASKED;
2671
2672                 write_ht_irq_msg(irq, &msg);
2673
2674                 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2675                                               handle_edge_irq, "edge");
2676         }
2677         return vector;
2678 }
2679 #endif /* CONFIG_HT_IRQ */
2680
2681 /* --------------------------------------------------------------------------
2682                         ACPI-based IOAPIC Configuration
2683    -------------------------------------------------------------------------- */
2684
2685 #ifdef CONFIG_ACPI
2686
2687 int __init io_apic_get_unique_id(int ioapic, int apic_id)
2688 {
2689         union IO_APIC_reg_00 reg_00;
2690         static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2691         physid_mask_t tmp;
2692         unsigned long flags;
2693         int i = 0;
2694
2695         /*
2696          * The P4 platform supports up to 256 APIC IDs on two separate APIC
2697          * buses (one for LAPICs, one for IOAPICs), where predecessors only
2698          * supports up to 16 on one shared APIC bus.
2699          *
2700          * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2701          *      advantage of new APIC bus architecture.
2702          */
2703
2704         if (physids_empty(apic_id_map))
2705                 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
2706
2707         spin_lock_irqsave(&ioapic_lock, flags);
2708         reg_00.raw = io_apic_read(ioapic, 0);
2709         spin_unlock_irqrestore(&ioapic_lock, flags);
2710
2711         if (apic_id >= get_physical_broadcast()) {
2712                 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2713                         "%d\n", ioapic, apic_id, reg_00.bits.ID);
2714                 apic_id = reg_00.bits.ID;
2715         }
2716
2717         /*
2718          * Every APIC in a system must have a unique ID or we get lots of nice
2719          * 'stuck on smp_invalidate_needed IPI wait' messages.
2720          */
2721         if (check_apicid_used(apic_id_map, apic_id)) {
2722
2723                 for (i = 0; i < get_physical_broadcast(); i++) {
2724                         if (!check_apicid_used(apic_id_map, i))
2725                                 break;
2726                 }
2727
2728                 if (i == get_physical_broadcast())
2729                         panic("Max apic_id exceeded!\n");
2730
2731                 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2732                         "trying %d\n", ioapic, apic_id, i);
2733
2734                 apic_id = i;
2735         }
2736
2737         tmp = apicid_to_cpu_present(apic_id);
2738         physids_or(apic_id_map, apic_id_map, tmp);
2739
2740         if (reg_00.bits.ID != apic_id) {
2741                 reg_00.bits.ID = apic_id;
2742
2743                 spin_lock_irqsave(&ioapic_lock, flags);
2744                 io_apic_write(ioapic, 0, reg_00.raw);
2745                 reg_00.raw = io_apic_read(ioapic, 0);
2746                 spin_unlock_irqrestore(&ioapic_lock, flags);
2747
2748                 /* Sanity check */
2749                 if (reg_00.bits.ID != apic_id) {
2750                         printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
2751                         return -1;
2752                 }
2753         }
2754
2755         apic_printk(APIC_VERBOSE, KERN_INFO
2756                         "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2757
2758         return apic_id;
2759 }
2760
2761
2762 int __init io_apic_get_version(int ioapic)
2763 {
2764         union IO_APIC_reg_01    reg_01;
2765         unsigned long flags;
2766
2767         spin_lock_irqsave(&ioapic_lock, flags);
2768         reg_01.raw = io_apic_read(ioapic, 1);
2769         spin_unlock_irqrestore(&ioapic_lock, flags);
2770
2771         return reg_01.bits.version;
2772 }
2773
2774
2775 int __init io_apic_get_redir_entries(int ioapic)
2776 {
2777         union IO_APIC_reg_01    reg_01;
2778         unsigned long flags;
2779
2780         spin_lock_irqsave(&ioapic_lock, flags);
2781         reg_01.raw = io_apic_read(ioapic, 1);
2782         spin_unlock_irqrestore(&ioapic_lock, flags);
2783
2784         return reg_01.bits.entries;
2785 }
2786
2787
2788 int io_apic_set_pci_routing(int ioapic, int pin, int irq, int edge_level, int active_high_low)
2789 {
2790         struct IO_APIC_route_entry entry;
2791
2792         if (!IO_APIC_IRQ(irq)) {
2793                 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2794                         ioapic);
2795                 return -EINVAL;
2796         }
2797
2798         /*
2799          * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2800          * Note that we mask (disable) IRQs now -- these get enabled when the
2801          * corresponding device driver registers for this IRQ.
2802          */
2803
2804         memset(&entry, 0, sizeof(entry));
2805
2806         entry.delivery_mode = INT_DELIVERY_MODE;
2807         entry.dest_mode = INT_DEST_MODE;
2808         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2809         entry.trigger = edge_level;
2810         entry.polarity = active_high_low;
2811         entry.mask  = 1;
2812
2813         /*
2814          * IRQs < 16 are already in the irq_2_pin[] map
2815          */
2816         if (irq >= 16)
2817                 add_pin_to_irq(irq, ioapic, pin);
2818
2819         entry.vector = assign_irq_vector(irq);
2820
2821         apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry "
2822                 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic,
2823                 mp_ioapics[ioapic].mp_apicid, pin, entry.vector, irq,
2824                 edge_level, active_high_low);
2825
2826         ioapic_register_intr(irq, entry.vector, edge_level);
2827
2828         if (!ioapic && (irq < 16))
2829                 disable_8259A_irq(irq);
2830
2831         ioapic_write_entry(ioapic, pin, entry);
2832
2833         return 0;
2834 }
2835
2836 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
2837 {
2838         int i;
2839
2840         if (skip_ioapic_setup)
2841                 return -1;
2842
2843         for (i = 0; i < mp_irq_entries; i++)
2844                 if (mp_irqs[i].mp_irqtype == mp_INT &&
2845                     mp_irqs[i].mp_srcbusirq == bus_irq)
2846                         break;
2847         if (i >= mp_irq_entries)
2848                 return -1;
2849
2850         *trigger = irq_trigger(i);
2851         *polarity = irq_polarity(i);
2852         return 0;
2853 }
2854
2855 #endif /* CONFIG_ACPI */
2856
2857 static int __init parse_disable_timer_pin_1(char *arg)
2858 {
2859         disable_timer_pin_1 = 1;
2860         return 0;
2861 }
2862 early_param("disable_timer_pin_1", parse_disable_timer_pin_1);
2863
2864 static int __init parse_enable_timer_pin_1(char *arg)
2865 {
2866         disable_timer_pin_1 = -1;
2867         return 0;
2868 }
2869 early_param("enable_timer_pin_1", parse_enable_timer_pin_1);
2870
2871 static int __init parse_noapic(char *arg)
2872 {
2873         /* disable IO-APIC */
2874         disable_ioapic_setup();
2875         return 0;
2876 }
2877 early_param("noapic", parse_noapic);
2878
2879 void __init ioapic_init_mappings(void)
2880 {
2881         unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
2882         int i;
2883
2884         for (i = 0; i < nr_ioapics; i++) {
2885                 if (smp_found_config) {
2886                         ioapic_phys = mp_ioapics[i].mp_apicaddr;
2887                         if (!ioapic_phys) {
2888                                 printk(KERN_ERR
2889                                        "WARNING: bogus zero IO-APIC "
2890                                        "address found in MPTABLE, "
2891                                        "disabling IO/APIC support!\n");
2892                                 smp_found_config = 0;
2893                                 skip_ioapic_setup = 1;
2894                                 goto fake_ioapic_page;
2895                         }
2896                 } else {
2897 fake_ioapic_page:
2898                         ioapic_phys = (unsigned long)
2899                                       alloc_bootmem_pages(PAGE_SIZE);
2900                         ioapic_phys = __pa(ioapic_phys);
2901                 }
2902                 set_fixmap_nocache(idx, ioapic_phys);
2903                 printk(KERN_DEBUG "mapped IOAPIC to %08lx (%08lx)\n",
2904                        __fix_to_virt(idx), ioapic_phys);
2905                 idx++;
2906         }
2907 }
2908