x86: apic unification - merge down enable_NMI_through_LVT0
[linux-2.6.git] / arch / x86 / kernel / io_apic_32.c
1 /*
2  *      Intel IO-APIC support for multi-Pentium hosts.
3  *
4  *      Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5  *
6  *      Many thanks to Stig Venaas for trying out countless experimental
7  *      patches and reporting/debugging problems patiently!
8  *
9  *      (c) 1999, Multiple IO-APIC support, developed by
10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
13  *      and Ingo Molnar <mingo@redhat.com>
14  *
15  *      Fixes
16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
17  *                                      thanks to Eric Gilmore
18  *                                      and Rolf G. Tews
19  *                                      for testing these extensively
20  *      Paul Diefenbaugh        :       Added full ACPI support
21  */
22
23 #include <linux/mm.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/bootmem.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/pci.h>
35 #include <linux/msi.h>
36 #include <linux/htirq.h>
37 #include <linux/freezer.h>
38 #include <linux/kthread.h>
39 #include <linux/jiffies.h>      /* time_after() */
40
41 #include <asm/io.h>
42 #include <asm/smp.h>
43 #include <asm/desc.h>
44 #include <asm/timer.h>
45 #include <asm/i8259.h>
46 #include <asm/nmi.h>
47 #include <asm/msidef.h>
48 #include <asm/hypertransport.h>
49
50 #include <mach_apic.h>
51 #include <mach_apicdef.h>
52
53 #define __apicdebuginit(type) static type __init
54
55 int (*ioapic_renumber_irq)(int ioapic, int irq);
56 atomic_t irq_mis_count;
57
58 /* Where if anywhere is the i8259 connect in external int mode */
59 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
60
61 static DEFINE_SPINLOCK(ioapic_lock);
62 static DEFINE_SPINLOCK(vector_lock);
63
64 int timer_through_8259 __initdata;
65
66 /*
67  *      Is the SiS APIC rmw bug present ?
68  *      -1 = don't know, 0 = no, 1 = yes
69  */
70 int sis_apic_bug = -1;
71
72 /*
73  * # of IRQ routing registers
74  */
75 int nr_ioapic_registers[MAX_IO_APICS];
76
77 /* I/O APIC entries */
78 struct mp_config_ioapic mp_ioapics[MAX_IO_APICS];
79 int nr_ioapics;
80
81 /* MP IRQ source entries */
82 struct mp_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
83
84 /* # of MP IRQ source entries */
85 int mp_irq_entries;
86
87 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
88 int mp_bus_id_to_type[MAX_MP_BUSSES];
89 #endif
90
91 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
92
93 static int disable_timer_pin_1 __initdata;
94
95 /*
96  * Rough estimation of how many shared IRQs there are, can
97  * be changed anytime.
98  */
99 #define MAX_PLUS_SHARED_IRQS NR_IRQS
100 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
101
102 /*
103  * This is performance-critical, we want to do it O(1)
104  *
105  * the indexing order of this array favors 1:1 mappings
106  * between pins and IRQs.
107  */
108
109 static struct irq_pin_list {
110         int apic, pin, next;
111 } irq_2_pin[PIN_MAP_SIZE];
112
113 struct io_apic {
114         unsigned int index;
115         unsigned int unused[3];
116         unsigned int data;
117 };
118
119 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
120 {
121         return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
122                 + (mp_ioapics[idx].mp_apicaddr & ~PAGE_MASK);
123 }
124
125 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
126 {
127         struct io_apic __iomem *io_apic = io_apic_base(apic);
128         writel(reg, &io_apic->index);
129         return readl(&io_apic->data);
130 }
131
132 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
133 {
134         struct io_apic __iomem *io_apic = io_apic_base(apic);
135         writel(reg, &io_apic->index);
136         writel(value, &io_apic->data);
137 }
138
139 /*
140  * Re-write a value: to be used for read-modify-write
141  * cycles where the read already set up the index register.
142  *
143  * Older SiS APIC requires we rewrite the index register
144  */
145 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
146 {
147         volatile struct io_apic __iomem *io_apic = io_apic_base(apic);
148         if (sis_apic_bug)
149                 writel(reg, &io_apic->index);
150         writel(value, &io_apic->data);
151 }
152
153 union entry_union {
154         struct { u32 w1, w2; };
155         struct IO_APIC_route_entry entry;
156 };
157
158 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
159 {
160         union entry_union eu;
161         unsigned long flags;
162         spin_lock_irqsave(&ioapic_lock, flags);
163         eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
164         eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
165         spin_unlock_irqrestore(&ioapic_lock, flags);
166         return eu.entry;
167 }
168
169 /*
170  * When we write a new IO APIC routing entry, we need to write the high
171  * word first! If the mask bit in the low word is clear, we will enable
172  * the interrupt, and we need to make sure the entry is fully populated
173  * before that happens.
174  */
175 static void
176 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
177 {
178         union entry_union eu;
179         eu.entry = e;
180         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
181         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
182 }
183
184 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
185 {
186         unsigned long flags;
187         spin_lock_irqsave(&ioapic_lock, flags);
188         __ioapic_write_entry(apic, pin, e);
189         spin_unlock_irqrestore(&ioapic_lock, flags);
190 }
191
192 /*
193  * When we mask an IO APIC routing entry, we need to write the low
194  * word first, in order to set the mask bit before we change the
195  * high bits!
196  */
197 static void ioapic_mask_entry(int apic, int pin)
198 {
199         unsigned long flags;
200         union entry_union eu = { .entry.mask = 1 };
201
202         spin_lock_irqsave(&ioapic_lock, flags);
203         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
204         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
205         spin_unlock_irqrestore(&ioapic_lock, flags);
206 }
207
208 /*
209  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
210  * shared ISA-space IRQs, so we have to support them. We are super
211  * fast in the common case, and fast for shared ISA-space IRQs.
212  */
213 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
214 {
215         static int first_free_entry = NR_IRQS;
216         struct irq_pin_list *entry = irq_2_pin + irq;
217
218         while (entry->next)
219                 entry = irq_2_pin + entry->next;
220
221         if (entry->pin != -1) {
222                 entry->next = first_free_entry;
223                 entry = irq_2_pin + entry->next;
224                 if (++first_free_entry >= PIN_MAP_SIZE)
225                         panic("io_apic.c: whoops");
226         }
227         entry->apic = apic;
228         entry->pin = pin;
229 }
230
231 /*
232  * Reroute an IRQ to a different pin.
233  */
234 static void __init replace_pin_at_irq(unsigned int irq,
235                                       int oldapic, int oldpin,
236                                       int newapic, int newpin)
237 {
238         struct irq_pin_list *entry = irq_2_pin + irq;
239
240         while (1) {
241                 if (entry->apic == oldapic && entry->pin == oldpin) {
242                         entry->apic = newapic;
243                         entry->pin = newpin;
244                 }
245                 if (!entry->next)
246                         break;
247                 entry = irq_2_pin + entry->next;
248         }
249 }
250
251 static void __modify_IO_APIC_irq(unsigned int irq, unsigned long enable, unsigned long disable)
252 {
253         struct irq_pin_list *entry = irq_2_pin + irq;
254         unsigned int pin, reg;
255
256         for (;;) {
257                 pin = entry->pin;
258                 if (pin == -1)
259                         break;
260                 reg = io_apic_read(entry->apic, 0x10 + pin*2);
261                 reg &= ~disable;
262                 reg |= enable;
263                 io_apic_modify(entry->apic, 0x10 + pin*2, reg);
264                 if (!entry->next)
265                         break;
266                 entry = irq_2_pin + entry->next;
267         }
268 }
269
270 /* mask = 1 */
271 static void __mask_IO_APIC_irq(unsigned int irq)
272 {
273         __modify_IO_APIC_irq(irq, IO_APIC_REDIR_MASKED, 0);
274 }
275
276 /* mask = 0 */
277 static void __unmask_IO_APIC_irq(unsigned int irq)
278 {
279         __modify_IO_APIC_irq(irq, 0, IO_APIC_REDIR_MASKED);
280 }
281
282 /* mask = 1, trigger = 0 */
283 static void __mask_and_edge_IO_APIC_irq(unsigned int irq)
284 {
285         __modify_IO_APIC_irq(irq, IO_APIC_REDIR_MASKED,
286                                 IO_APIC_REDIR_LEVEL_TRIGGER);
287 }
288
289 /* mask = 0, trigger = 1 */
290 static void __unmask_and_level_IO_APIC_irq(unsigned int irq)
291 {
292         __modify_IO_APIC_irq(irq, IO_APIC_REDIR_LEVEL_TRIGGER,
293                                 IO_APIC_REDIR_MASKED);
294 }
295
296 static void mask_IO_APIC_irq(unsigned int irq)
297 {
298         unsigned long flags;
299
300         spin_lock_irqsave(&ioapic_lock, flags);
301         __mask_IO_APIC_irq(irq);
302         spin_unlock_irqrestore(&ioapic_lock, flags);
303 }
304
305 static void unmask_IO_APIC_irq(unsigned int irq)
306 {
307         unsigned long flags;
308
309         spin_lock_irqsave(&ioapic_lock, flags);
310         __unmask_IO_APIC_irq(irq);
311         spin_unlock_irqrestore(&ioapic_lock, flags);
312 }
313
314 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
315 {
316         struct IO_APIC_route_entry entry;
317
318         /* Check delivery_mode to be sure we're not clearing an SMI pin */
319         entry = ioapic_read_entry(apic, pin);
320         if (entry.delivery_mode == dest_SMI)
321                 return;
322
323         /*
324          * Disable it in the IO-APIC irq-routing table:
325          */
326         ioapic_mask_entry(apic, pin);
327 }
328
329 static void clear_IO_APIC(void)
330 {
331         int apic, pin;
332
333         for (apic = 0; apic < nr_ioapics; apic++)
334                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
335                         clear_IO_APIC_pin(apic, pin);
336 }
337
338 #ifdef CONFIG_SMP
339 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
340 {
341         unsigned long flags;
342         int pin;
343         struct irq_pin_list *entry = irq_2_pin + irq;
344         unsigned int apicid_value;
345         cpumask_t tmp;
346
347         cpus_and(tmp, cpumask, cpu_online_map);
348         if (cpus_empty(tmp))
349                 tmp = TARGET_CPUS;
350
351         cpus_and(cpumask, tmp, CPU_MASK_ALL);
352
353         apicid_value = cpu_mask_to_apicid(cpumask);
354         /* Prepare to do the io_apic_write */
355         apicid_value = apicid_value << 24;
356         spin_lock_irqsave(&ioapic_lock, flags);
357         for (;;) {
358                 pin = entry->pin;
359                 if (pin == -1)
360                         break;
361                 io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
362                 if (!entry->next)
363                         break;
364                 entry = irq_2_pin + entry->next;
365         }
366         irq_desc[irq].affinity = cpumask;
367         spin_unlock_irqrestore(&ioapic_lock, flags);
368 }
369
370 #if defined(CONFIG_IRQBALANCE)
371 # include <asm/processor.h>     /* kernel_thread() */
372 # include <linux/kernel_stat.h> /* kstat */
373 # include <linux/slab.h>                /* kmalloc() */
374 # include <linux/timer.h>
375
376 #define IRQBALANCE_CHECK_ARCH -999
377 #define MAX_BALANCED_IRQ_INTERVAL       (5*HZ)
378 #define MIN_BALANCED_IRQ_INTERVAL       (HZ/2)
379 #define BALANCED_IRQ_MORE_DELTA         (HZ/10)
380 #define BALANCED_IRQ_LESS_DELTA         (HZ)
381
382 static int irqbalance_disabled __read_mostly = IRQBALANCE_CHECK_ARCH;
383 static int physical_balance __read_mostly;
384 static long balanced_irq_interval __read_mostly = MAX_BALANCED_IRQ_INTERVAL;
385
386 static struct irq_cpu_info {
387         unsigned long *last_irq;
388         unsigned long *irq_delta;
389         unsigned long irq;
390 } irq_cpu_data[NR_CPUS];
391
392 #define CPU_IRQ(cpu)            (irq_cpu_data[cpu].irq)
393 #define LAST_CPU_IRQ(cpu, irq)   (irq_cpu_data[cpu].last_irq[irq])
394 #define IRQ_DELTA(cpu, irq)     (irq_cpu_data[cpu].irq_delta[irq])
395
396 #define IDLE_ENOUGH(cpu,now) \
397         (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
398
399 #define IRQ_ALLOWED(cpu, allowed_mask)  cpu_isset(cpu, allowed_mask)
400
401 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(per_cpu(cpu_sibling_map, i)))
402
403 static cpumask_t balance_irq_affinity[NR_IRQS] = {
404         [0 ... NR_IRQS-1] = CPU_MASK_ALL
405 };
406
407 void set_balance_irq_affinity(unsigned int irq, cpumask_t mask)
408 {
409         balance_irq_affinity[irq] = mask;
410 }
411
412 static unsigned long move(int curr_cpu, cpumask_t allowed_mask,
413                         unsigned long now, int direction)
414 {
415         int search_idle = 1;
416         int cpu = curr_cpu;
417
418         goto inside;
419
420         do {
421                 if (unlikely(cpu == curr_cpu))
422                         search_idle = 0;
423 inside:
424                 if (direction == 1) {
425                         cpu++;
426                         if (cpu >= NR_CPUS)
427                                 cpu = 0;
428                 } else {
429                         cpu--;
430                         if (cpu == -1)
431                                 cpu = NR_CPUS-1;
432                 }
433         } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu, allowed_mask) ||
434                         (search_idle && !IDLE_ENOUGH(cpu, now)));
435
436         return cpu;
437 }
438
439 static inline void balance_irq(int cpu, int irq)
440 {
441         unsigned long now = jiffies;
442         cpumask_t allowed_mask;
443         unsigned int new_cpu;
444
445         if (irqbalance_disabled)
446                 return;
447
448         cpus_and(allowed_mask, cpu_online_map, balance_irq_affinity[irq]);
449         new_cpu = move(cpu, allowed_mask, now, 1);
450         if (cpu != new_cpu)
451                 set_pending_irq(irq, cpumask_of_cpu(new_cpu));
452 }
453
454 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold)
455 {
456         int i, j;
457
458         for_each_online_cpu(i) {
459                 for (j = 0; j < NR_IRQS; j++) {
460                         if (!irq_desc[j].action)
461                                 continue;
462                         /* Is it a significant load ?  */
463                         if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i), j) <
464                                                 useful_load_threshold)
465                                 continue;
466                         balance_irq(i, j);
467                 }
468         }
469         balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
470                 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
471         return;
472 }
473
474 static void do_irq_balance(void)
475 {
476         int i, j;
477         unsigned long max_cpu_irq = 0, min_cpu_irq = (~0);
478         unsigned long move_this_load = 0;
479         int max_loaded = 0, min_loaded = 0;
480         int load;
481         unsigned long useful_load_threshold = balanced_irq_interval + 10;
482         int selected_irq;
483         int tmp_loaded, first_attempt = 1;
484         unsigned long tmp_cpu_irq;
485         unsigned long imbalance = 0;
486         cpumask_t allowed_mask, target_cpu_mask, tmp;
487
488         for_each_possible_cpu(i) {
489                 int package_index;
490                 CPU_IRQ(i) = 0;
491                 if (!cpu_online(i))
492                         continue;
493                 package_index = CPU_TO_PACKAGEINDEX(i);
494                 for (j = 0; j < NR_IRQS; j++) {
495                         unsigned long value_now, delta;
496                         /* Is this an active IRQ or balancing disabled ? */
497                         if (!irq_desc[j].action || irq_balancing_disabled(j))
498                                 continue;
499                         if (package_index == i)
500                                 IRQ_DELTA(package_index, j) = 0;
501                         /* Determine the total count per processor per IRQ */
502                         value_now = (unsigned long) kstat_cpu(i).irqs[j];
503
504                         /* Determine the activity per processor per IRQ */
505                         delta = value_now - LAST_CPU_IRQ(i, j);
506
507                         /* Update last_cpu_irq[][] for the next time */
508                         LAST_CPU_IRQ(i, j) = value_now;
509
510                         /* Ignore IRQs whose rate is less than the clock */
511                         if (delta < useful_load_threshold)
512                                 continue;
513                         /* update the load for the processor or package total */
514                         IRQ_DELTA(package_index, j) += delta;
515
516                         /* Keep track of the higher numbered sibling as well */
517                         if (i != package_index)
518                                 CPU_IRQ(i) += delta;
519                         /*
520                          * We have sibling A and sibling B in the package
521                          *
522                          * cpu_irq[A] = load for cpu A + load for cpu B
523                          * cpu_irq[B] = load for cpu B
524                          */
525                         CPU_IRQ(package_index) += delta;
526                 }
527         }
528         /* Find the least loaded processor package */
529         for_each_online_cpu(i) {
530                 if (i != CPU_TO_PACKAGEINDEX(i))
531                         continue;
532                 if (min_cpu_irq > CPU_IRQ(i)) {
533                         min_cpu_irq = CPU_IRQ(i);
534                         min_loaded = i;
535                 }
536         }
537         max_cpu_irq = ULONG_MAX;
538
539 tryanothercpu:
540         /*
541          * Look for heaviest loaded processor.
542          * We may come back to get the next heaviest loaded processor.
543          * Skip processors with trivial loads.
544          */
545         tmp_cpu_irq = 0;
546         tmp_loaded = -1;
547         for_each_online_cpu(i) {
548                 if (i != CPU_TO_PACKAGEINDEX(i))
549                         continue;
550                 if (max_cpu_irq <= CPU_IRQ(i))
551                         continue;
552                 if (tmp_cpu_irq < CPU_IRQ(i)) {
553                         tmp_cpu_irq = CPU_IRQ(i);
554                         tmp_loaded = i;
555                 }
556         }
557
558         if (tmp_loaded == -1) {
559          /*
560           * In the case of small number of heavy interrupt sources,
561           * loading some of the cpus too much. We use Ingo's original
562           * approach to rotate them around.
563           */
564                 if (!first_attempt && imbalance >= useful_load_threshold) {
565                         rotate_irqs_among_cpus(useful_load_threshold);
566                         return;
567                 }
568                 goto not_worth_the_effort;
569         }
570
571         first_attempt = 0;              /* heaviest search */
572         max_cpu_irq = tmp_cpu_irq;      /* load */
573         max_loaded = tmp_loaded;        /* processor */
574         imbalance = (max_cpu_irq - min_cpu_irq) / 2;
575
576         /*
577          * if imbalance is less than approx 10% of max load, then
578          * observe diminishing returns action. - quit
579          */
580         if (imbalance < (max_cpu_irq >> 3))
581                 goto not_worth_the_effort;
582
583 tryanotherirq:
584         /* if we select an IRQ to move that can't go where we want, then
585          * see if there is another one to try.
586          */
587         move_this_load = 0;
588         selected_irq = -1;
589         for (j = 0; j < NR_IRQS; j++) {
590                 /* Is this an active IRQ? */
591                 if (!irq_desc[j].action)
592                         continue;
593                 if (imbalance <= IRQ_DELTA(max_loaded, j))
594                         continue;
595                 /* Try to find the IRQ that is closest to the imbalance
596                  * without going over.
597                  */
598                 if (move_this_load < IRQ_DELTA(max_loaded, j)) {
599                         move_this_load = IRQ_DELTA(max_loaded, j);
600                         selected_irq = j;
601                 }
602         }
603         if (selected_irq == -1)
604                 goto tryanothercpu;
605
606         imbalance = move_this_load;
607
608         /* For physical_balance case, we accumulated both load
609          * values in the one of the siblings cpu_irq[],
610          * to use the same code for physical and logical processors
611          * as much as possible.
612          *
613          * NOTE: the cpu_irq[] array holds the sum of the load for
614          * sibling A and sibling B in the slot for the lowest numbered
615          * sibling (A), _AND_ the load for sibling B in the slot for
616          * the higher numbered sibling.
617          *
618          * We seek the least loaded sibling by making the comparison
619          * (A+B)/2 vs B
620          */
621         load = CPU_IRQ(min_loaded) >> 1;
622         for_each_cpu_mask(j, per_cpu(cpu_sibling_map, min_loaded)) {
623                 if (load > CPU_IRQ(j)) {
624                         /* This won't change cpu_sibling_map[min_loaded] */
625                         load = CPU_IRQ(j);
626                         min_loaded = j;
627                 }
628         }
629
630         cpus_and(allowed_mask,
631                 cpu_online_map,
632                 balance_irq_affinity[selected_irq]);
633         target_cpu_mask = cpumask_of_cpu(min_loaded);
634         cpus_and(tmp, target_cpu_mask, allowed_mask);
635
636         if (!cpus_empty(tmp)) {
637                 /* mark for change destination */
638                 set_pending_irq(selected_irq, cpumask_of_cpu(min_loaded));
639
640                 /* Since we made a change, come back sooner to
641                  * check for more variation.
642                  */
643                 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
644                         balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
645                 return;
646         }
647         goto tryanotherirq;
648
649 not_worth_the_effort:
650         /*
651          * if we did not find an IRQ to move, then adjust the time interval
652          * upward
653          */
654         balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL,
655                 balanced_irq_interval + BALANCED_IRQ_MORE_DELTA);
656         return;
657 }
658
659 static int balanced_irq(void *unused)
660 {
661         int i;
662         unsigned long prev_balance_time = jiffies;
663         long time_remaining = balanced_irq_interval;
664
665         /* push everything to CPU 0 to give us a starting point.  */
666         for (i = 0 ; i < NR_IRQS ; i++) {
667                 irq_desc[i].pending_mask = cpumask_of_cpu(0);
668                 set_pending_irq(i, cpumask_of_cpu(0));
669         }
670
671         set_freezable();
672         for ( ; ; ) {
673                 time_remaining = schedule_timeout_interruptible(time_remaining);
674                 try_to_freeze();
675                 if (time_after(jiffies,
676                                 prev_balance_time+balanced_irq_interval)) {
677                         preempt_disable();
678                         do_irq_balance();
679                         prev_balance_time = jiffies;
680                         time_remaining = balanced_irq_interval;
681                         preempt_enable();
682                 }
683         }
684         return 0;
685 }
686
687 static int __init balanced_irq_init(void)
688 {
689         int i;
690         struct cpuinfo_x86 *c;
691         cpumask_t tmp;
692
693         cpus_shift_right(tmp, cpu_online_map, 2);
694         c = &boot_cpu_data;
695         /* When not overwritten by the command line ask subarchitecture. */
696         if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH)
697                 irqbalance_disabled = NO_BALANCE_IRQ;
698         if (irqbalance_disabled)
699                 return 0;
700
701          /* disable irqbalance completely if there is only one processor online */
702         if (num_online_cpus() < 2) {
703                 irqbalance_disabled = 1;
704                 return 0;
705         }
706         /*
707          * Enable physical balance only if more than 1 physical processor
708          * is present
709          */
710         if (smp_num_siblings > 1 && !cpus_empty(tmp))
711                 physical_balance = 1;
712
713         for_each_online_cpu(i) {
714                 irq_cpu_data[i].irq_delta = kzalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
715                 irq_cpu_data[i].last_irq = kzalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
716                 if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) {
717                         printk(KERN_ERR "balanced_irq_init: out of memory");
718                         goto failed;
719                 }
720         }
721
722         printk(KERN_INFO "Starting balanced_irq\n");
723         if (!IS_ERR(kthread_run(balanced_irq, NULL, "kirqd")))
724                 return 0;
725         printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq");
726 failed:
727         for_each_possible_cpu(i) {
728                 kfree(irq_cpu_data[i].irq_delta);
729                 irq_cpu_data[i].irq_delta = NULL;
730                 kfree(irq_cpu_data[i].last_irq);
731                 irq_cpu_data[i].last_irq = NULL;
732         }
733         return 0;
734 }
735
736 int __devinit irqbalance_disable(char *str)
737 {
738         irqbalance_disabled = 1;
739         return 1;
740 }
741
742 __setup("noirqbalance", irqbalance_disable);
743
744 late_initcall(balanced_irq_init);
745 #endif /* CONFIG_IRQBALANCE */
746 #endif /* CONFIG_SMP */
747
748 #ifndef CONFIG_SMP
749 void send_IPI_self(int vector)
750 {
751         unsigned int cfg;
752
753         /*
754          * Wait for idle.
755          */
756         apic_wait_icr_idle();
757         cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
758         /*
759          * Send the IPI. The write to APIC_ICR fires this off.
760          */
761         apic_write(APIC_ICR, cfg);
762 }
763 #endif /* !CONFIG_SMP */
764
765
766 /*
767  * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
768  * specific CPU-side IRQs.
769  */
770
771 #define MAX_PIRQS 8
772 static int pirq_entries [MAX_PIRQS];
773 static int pirqs_enabled;
774 int skip_ioapic_setup;
775
776 static int __init ioapic_pirq_setup(char *str)
777 {
778         int i, max;
779         int ints[MAX_PIRQS+1];
780
781         get_options(str, ARRAY_SIZE(ints), ints);
782
783         for (i = 0; i < MAX_PIRQS; i++)
784                 pirq_entries[i] = -1;
785
786         pirqs_enabled = 1;
787         apic_printk(APIC_VERBOSE, KERN_INFO
788                         "PIRQ redirection, working around broken MP-BIOS.\n");
789         max = MAX_PIRQS;
790         if (ints[0] < MAX_PIRQS)
791                 max = ints[0];
792
793         for (i = 0; i < max; i++) {
794                 apic_printk(APIC_VERBOSE, KERN_DEBUG
795                                 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
796                 /*
797                  * PIRQs are mapped upside down, usually.
798                  */
799                 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
800         }
801         return 1;
802 }
803
804 __setup("pirq=", ioapic_pirq_setup);
805
806 /*
807  * Find the IRQ entry number of a certain pin.
808  */
809 static int find_irq_entry(int apic, int pin, int type)
810 {
811         int i;
812
813         for (i = 0; i < mp_irq_entries; i++)
814                 if (mp_irqs[i].mp_irqtype == type &&
815                     (mp_irqs[i].mp_dstapic == mp_ioapics[apic].mp_apicid ||
816                      mp_irqs[i].mp_dstapic == MP_APIC_ALL) &&
817                     mp_irqs[i].mp_dstirq == pin)
818                         return i;
819
820         return -1;
821 }
822
823 /*
824  * Find the pin to which IRQ[irq] (ISA) is connected
825  */
826 static int __init find_isa_irq_pin(int irq, int type)
827 {
828         int i;
829
830         for (i = 0; i < mp_irq_entries; i++) {
831                 int lbus = mp_irqs[i].mp_srcbus;
832
833                 if (test_bit(lbus, mp_bus_not_pci) &&
834                     (mp_irqs[i].mp_irqtype == type) &&
835                     (mp_irqs[i].mp_srcbusirq == irq))
836
837                         return mp_irqs[i].mp_dstirq;
838         }
839         return -1;
840 }
841
842 static int __init find_isa_irq_apic(int irq, int type)
843 {
844         int i;
845
846         for (i = 0; i < mp_irq_entries; i++) {
847                 int lbus = mp_irqs[i].mp_srcbus;
848
849                 if (test_bit(lbus, mp_bus_not_pci) &&
850                     (mp_irqs[i].mp_irqtype == type) &&
851                     (mp_irqs[i].mp_srcbusirq == irq))
852                         break;
853         }
854         if (i < mp_irq_entries) {
855                 int apic;
856                 for (apic = 0; apic < nr_ioapics; apic++) {
857                         if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic)
858                                 return apic;
859                 }
860         }
861
862         return -1;
863 }
864
865 /*
866  * Find a specific PCI IRQ entry.
867  * Not an __init, possibly needed by modules
868  */
869 static int pin_2_irq(int idx, int apic, int pin);
870
871 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
872 {
873         int apic, i, best_guess = -1;
874
875         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, "
876                 "slot:%d, pin:%d.\n", bus, slot, pin);
877         if (test_bit(bus, mp_bus_not_pci)) {
878                 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
879                 return -1;
880         }
881         for (i = 0; i < mp_irq_entries; i++) {
882                 int lbus = mp_irqs[i].mp_srcbus;
883
884                 for (apic = 0; apic < nr_ioapics; apic++)
885                         if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic ||
886                             mp_irqs[i].mp_dstapic == MP_APIC_ALL)
887                                 break;
888
889                 if (!test_bit(lbus, mp_bus_not_pci) &&
890                     !mp_irqs[i].mp_irqtype &&
891                     (bus == lbus) &&
892                     (slot == ((mp_irqs[i].mp_srcbusirq >> 2) & 0x1f))) {
893                         int irq = pin_2_irq(i, apic, mp_irqs[i].mp_dstirq);
894
895                         if (!(apic || IO_APIC_IRQ(irq)))
896                                 continue;
897
898                         if (pin == (mp_irqs[i].mp_srcbusirq & 3))
899                                 return irq;
900                         /*
901                          * Use the first all-but-pin matching entry as a
902                          * best-guess fuzzy result for broken mptables.
903                          */
904                         if (best_guess < 0)
905                                 best_guess = irq;
906                 }
907         }
908         return best_guess;
909 }
910 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
911
912 /*
913  * This function currently is only a helper for the i386 smp boot process where
914  * we need to reprogram the ioredtbls to cater for the cpus which have come online
915  * so mask in all cases should simply be TARGET_CPUS
916  */
917 #ifdef CONFIG_SMP
918 void __init setup_ioapic_dest(void)
919 {
920         int pin, ioapic, irq, irq_entry;
921
922         if (skip_ioapic_setup == 1)
923                 return;
924
925         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
926                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
927                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
928                         if (irq_entry == -1)
929                                 continue;
930                         irq = pin_2_irq(irq_entry, ioapic, pin);
931                         set_ioapic_affinity_irq(irq, TARGET_CPUS);
932                 }
933
934         }
935 }
936 #endif
937
938 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
939 /*
940  * EISA Edge/Level control register, ELCR
941  */
942 static int EISA_ELCR(unsigned int irq)
943 {
944         if (irq < 16) {
945                 unsigned int port = 0x4d0 + (irq >> 3);
946                 return (inb(port) >> (irq & 7)) & 1;
947         }
948         apic_printk(APIC_VERBOSE, KERN_INFO
949                         "Broken MPtable reports ISA irq %d\n", irq);
950         return 0;
951 }
952 #endif
953
954 /* ISA interrupts are always polarity zero edge triggered,
955  * when listed as conforming in the MP table. */
956
957 #define default_ISA_trigger(idx)        (0)
958 #define default_ISA_polarity(idx)       (0)
959
960 /* EISA interrupts are always polarity zero and can be edge or level
961  * trigger depending on the ELCR value.  If an interrupt is listed as
962  * EISA conforming in the MP table, that means its trigger type must
963  * be read in from the ELCR */
964
965 #define default_EISA_trigger(idx)       (EISA_ELCR(mp_irqs[idx].mp_srcbusirq))
966 #define default_EISA_polarity(idx)      default_ISA_polarity(idx)
967
968 /* PCI interrupts are always polarity one level triggered,
969  * when listed as conforming in the MP table. */
970
971 #define default_PCI_trigger(idx)        (1)
972 #define default_PCI_polarity(idx)       (1)
973
974 /* MCA interrupts are always polarity zero level triggered,
975  * when listed as conforming in the MP table. */
976
977 #define default_MCA_trigger(idx)        (1)
978 #define default_MCA_polarity(idx)       default_ISA_polarity(idx)
979
980 static int MPBIOS_polarity(int idx)
981 {
982         int bus = mp_irqs[idx].mp_srcbus;
983         int polarity;
984
985         /*
986          * Determine IRQ line polarity (high active or low active):
987          */
988         switch (mp_irqs[idx].mp_irqflag & 3) {
989         case 0: /* conforms, ie. bus-type dependent polarity */
990         {
991                 polarity = test_bit(bus, mp_bus_not_pci)?
992                         default_ISA_polarity(idx):
993                         default_PCI_polarity(idx);
994                 break;
995         }
996         case 1: /* high active */
997         {
998                 polarity = 0;
999                 break;
1000         }
1001         case 2: /* reserved */
1002         {
1003                 printk(KERN_WARNING "broken BIOS!!\n");
1004                 polarity = 1;
1005                 break;
1006         }
1007         case 3: /* low active */
1008         {
1009                 polarity = 1;
1010                 break;
1011         }
1012         default: /* invalid */
1013         {
1014                 printk(KERN_WARNING "broken BIOS!!\n");
1015                 polarity = 1;
1016                 break;
1017         }
1018         }
1019         return polarity;
1020 }
1021
1022 static int MPBIOS_trigger(int idx)
1023 {
1024         int bus = mp_irqs[idx].mp_srcbus;
1025         int trigger;
1026
1027         /*
1028          * Determine IRQ trigger mode (edge or level sensitive):
1029          */
1030         switch ((mp_irqs[idx].mp_irqflag>>2) & 3) {
1031         case 0: /* conforms, ie. bus-type dependent */
1032         {
1033                 trigger = test_bit(bus, mp_bus_not_pci)?
1034                                 default_ISA_trigger(idx):
1035                                 default_PCI_trigger(idx);
1036 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1037                 switch (mp_bus_id_to_type[bus]) {
1038                 case MP_BUS_ISA: /* ISA pin */
1039                 {
1040                         /* set before the switch */
1041                         break;
1042                 }
1043                 case MP_BUS_EISA: /* EISA pin */
1044                 {
1045                         trigger = default_EISA_trigger(idx);
1046                         break;
1047                 }
1048                 case MP_BUS_PCI: /* PCI pin */
1049                 {
1050                         /* set before the switch */
1051                         break;
1052                 }
1053                 case MP_BUS_MCA: /* MCA pin */
1054                 {
1055                         trigger = default_MCA_trigger(idx);
1056                         break;
1057                 }
1058                 default:
1059                 {
1060                         printk(KERN_WARNING "broken BIOS!!\n");
1061                         trigger = 1;
1062                         break;
1063                 }
1064         }
1065 #endif
1066                 break;
1067         }
1068         case 1: /* edge */
1069         {
1070                 trigger = 0;
1071                 break;
1072         }
1073         case 2: /* reserved */
1074         {
1075                 printk(KERN_WARNING "broken BIOS!!\n");
1076                 trigger = 1;
1077                 break;
1078         }
1079         case 3: /* level */
1080         {
1081                 trigger = 1;
1082                 break;
1083         }
1084         default: /* invalid */
1085         {
1086                 printk(KERN_WARNING "broken BIOS!!\n");
1087                 trigger = 0;
1088                 break;
1089         }
1090         }
1091         return trigger;
1092 }
1093
1094 static inline int irq_polarity(int idx)
1095 {
1096         return MPBIOS_polarity(idx);
1097 }
1098
1099 static inline int irq_trigger(int idx)
1100 {
1101         return MPBIOS_trigger(idx);
1102 }
1103
1104 static int pin_2_irq(int idx, int apic, int pin)
1105 {
1106         int irq, i;
1107         int bus = mp_irqs[idx].mp_srcbus;
1108
1109         /*
1110          * Debugging check, we are in big trouble if this message pops up!
1111          */
1112         if (mp_irqs[idx].mp_dstirq != pin)
1113                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1114
1115         if (test_bit(bus, mp_bus_not_pci))
1116                 irq = mp_irqs[idx].mp_srcbusirq;
1117         else {
1118                 /*
1119                  * PCI IRQs are mapped in order
1120                  */
1121                 i = irq = 0;
1122                 while (i < apic)
1123                         irq += nr_ioapic_registers[i++];
1124                 irq += pin;
1125
1126                 /*
1127                  * For MPS mode, so far only needed by ES7000 platform
1128                  */
1129                 if (ioapic_renumber_irq)
1130                         irq = ioapic_renumber_irq(apic, irq);
1131         }
1132
1133         /*
1134          * PCI IRQ command line redirection. Yes, limits are hardcoded.
1135          */
1136         if ((pin >= 16) && (pin <= 23)) {
1137                 if (pirq_entries[pin-16] != -1) {
1138                         if (!pirq_entries[pin-16]) {
1139                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1140                                                 "disabling PIRQ%d\n", pin-16);
1141                         } else {
1142                                 irq = pirq_entries[pin-16];
1143                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1144                                                 "using PIRQ%d -> IRQ %d\n",
1145                                                 pin-16, irq);
1146                         }
1147                 }
1148         }
1149         return irq;
1150 }
1151
1152 static inline int IO_APIC_irq_trigger(int irq)
1153 {
1154         int apic, idx, pin;
1155
1156         for (apic = 0; apic < nr_ioapics; apic++) {
1157                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1158                         idx = find_irq_entry(apic, pin, mp_INT);
1159                         if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1160                                 return irq_trigger(idx);
1161                 }
1162         }
1163         /*
1164          * nonexistent IRQs are edge default
1165          */
1166         return 0;
1167 }
1168
1169 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1170 static u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 };
1171
1172 static int __assign_irq_vector(int irq)
1173 {
1174         static int current_vector = FIRST_DEVICE_VECTOR, current_offset;
1175         int vector, offset;
1176
1177         BUG_ON((unsigned)irq >= NR_IRQ_VECTORS);
1178
1179         if (irq_vector[irq] > 0)
1180                 return irq_vector[irq];
1181
1182         vector = current_vector;
1183         offset = current_offset;
1184 next:
1185         vector += 8;
1186         if (vector >= first_system_vector) {
1187                 offset = (offset + 1) % 8;
1188                 vector = FIRST_DEVICE_VECTOR + offset;
1189         }
1190         if (vector == current_vector)
1191                 return -ENOSPC;
1192         if (test_and_set_bit(vector, used_vectors))
1193                 goto next;
1194
1195         current_vector = vector;
1196         current_offset = offset;
1197         irq_vector[irq] = vector;
1198
1199         return vector;
1200 }
1201
1202 static int assign_irq_vector(int irq)
1203 {
1204         unsigned long flags;
1205         int vector;
1206
1207         spin_lock_irqsave(&vector_lock, flags);
1208         vector = __assign_irq_vector(irq);
1209         spin_unlock_irqrestore(&vector_lock, flags);
1210
1211         return vector;
1212 }
1213
1214 void setup_vector_irq(int cpu)
1215 {
1216 }
1217
1218 static struct irq_chip ioapic_chip;
1219
1220 #define IOAPIC_AUTO     -1
1221 #define IOAPIC_EDGE     0
1222 #define IOAPIC_LEVEL    1
1223
1224 static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
1225 {
1226         if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1227             trigger == IOAPIC_LEVEL) {
1228                 irq_desc[irq].status |= IRQ_LEVEL;
1229                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1230                                          handle_fasteoi_irq, "fasteoi");
1231         } else {
1232                 irq_desc[irq].status &= ~IRQ_LEVEL;
1233                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1234                                          handle_edge_irq, "edge");
1235         }
1236         set_intr_gate(vector, interrupt[irq]);
1237 }
1238
1239 static void __init setup_IO_APIC_irqs(void)
1240 {
1241         struct IO_APIC_route_entry entry;
1242         int apic, pin, idx, irq, first_notcon = 1, vector;
1243
1244         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1245
1246         for (apic = 0; apic < nr_ioapics; apic++) {
1247         for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1248
1249                 /*
1250                  * add it to the IO-APIC irq-routing table:
1251                  */
1252                 memset(&entry, 0, sizeof(entry));
1253
1254                 entry.delivery_mode = INT_DELIVERY_MODE;
1255                 entry.dest_mode = INT_DEST_MODE;
1256                 entry.mask = 0;                         /* enable IRQ */
1257                 entry.dest.logical.logical_dest =
1258                                         cpu_mask_to_apicid(TARGET_CPUS);
1259
1260                 idx = find_irq_entry(apic, pin, mp_INT);
1261                 if (idx == -1) {
1262                         if (first_notcon) {
1263                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1264                                                 " IO-APIC (apicid-pin) %d-%d",
1265                                                 mp_ioapics[apic].mp_apicid,
1266                                                 pin);
1267                                 first_notcon = 0;
1268                         } else
1269                                 apic_printk(APIC_VERBOSE, ", %d-%d",
1270                                         mp_ioapics[apic].mp_apicid, pin);
1271                         continue;
1272                 }
1273
1274                 if (!first_notcon) {
1275                         apic_printk(APIC_VERBOSE, " not connected.\n");
1276                         first_notcon = 1;
1277                 }
1278
1279                 entry.trigger = irq_trigger(idx);
1280                 entry.polarity = irq_polarity(idx);
1281
1282                 if (irq_trigger(idx)) {
1283                         entry.trigger = 1;
1284                         entry.mask = 1;
1285                 }
1286
1287                 irq = pin_2_irq(idx, apic, pin);
1288                 /*
1289                  * skip adding the timer int on secondary nodes, which causes
1290                  * a small but painful rift in the time-space continuum
1291                  */
1292                 if (multi_timer_check(apic, irq))
1293                         continue;
1294                 else
1295                         add_pin_to_irq(irq, apic, pin);
1296
1297                 if (!apic && !IO_APIC_IRQ(irq))
1298                         continue;
1299
1300                 if (IO_APIC_IRQ(irq)) {
1301                         vector = assign_irq_vector(irq);
1302                         entry.vector = vector;
1303                         ioapic_register_intr(irq, vector, IOAPIC_AUTO);
1304
1305                         if (!apic && (irq < 16))
1306                                 disable_8259A_irq(irq);
1307                 }
1308                 ioapic_write_entry(apic, pin, entry);
1309         }
1310         }
1311
1312         if (!first_notcon)
1313                 apic_printk(APIC_VERBOSE, " not connected.\n");
1314 }
1315
1316 /*
1317  * Set up the timer pin, possibly with the 8259A-master behind.
1318  */
1319 static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin,
1320                                         int vector)
1321 {
1322         struct IO_APIC_route_entry entry;
1323
1324         memset(&entry, 0, sizeof(entry));
1325
1326         /*
1327          * We use logical delivery to get the timer IRQ
1328          * to the first CPU.
1329          */
1330         entry.dest_mode = INT_DEST_MODE;
1331         entry.mask = 1;                                 /* mask IRQ now */
1332         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1333         entry.delivery_mode = INT_DELIVERY_MODE;
1334         entry.polarity = 0;
1335         entry.trigger = 0;
1336         entry.vector = vector;
1337
1338         /*
1339          * The timer IRQ doesn't have to know that behind the
1340          * scene we may have a 8259A-master in AEOI mode ...
1341          */
1342         ioapic_register_intr(0, vector, IOAPIC_EDGE);
1343
1344         /*
1345          * Add it to the IO-APIC irq-routing table:
1346          */
1347         ioapic_write_entry(apic, pin, entry);
1348 }
1349
1350
1351 __apicdebuginit(void) print_IO_APIC(void)
1352 {
1353         int apic, i;
1354         union IO_APIC_reg_00 reg_00;
1355         union IO_APIC_reg_01 reg_01;
1356         union IO_APIC_reg_02 reg_02;
1357         union IO_APIC_reg_03 reg_03;
1358         unsigned long flags;
1359
1360         if (apic_verbosity == APIC_QUIET)
1361                 return;
1362
1363         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1364         for (i = 0; i < nr_ioapics; i++)
1365                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1366                        mp_ioapics[i].mp_apicid, nr_ioapic_registers[i]);
1367
1368         /*
1369          * We are a bit conservative about what we expect.  We have to
1370          * know about every hardware change ASAP.
1371          */
1372         printk(KERN_INFO "testing the IO APIC.......................\n");
1373
1374         for (apic = 0; apic < nr_ioapics; apic++) {
1375
1376         spin_lock_irqsave(&ioapic_lock, flags);
1377         reg_00.raw = io_apic_read(apic, 0);
1378         reg_01.raw = io_apic_read(apic, 1);
1379         if (reg_01.bits.version >= 0x10)
1380                 reg_02.raw = io_apic_read(apic, 2);
1381         if (reg_01.bits.version >= 0x20)
1382                 reg_03.raw = io_apic_read(apic, 3);
1383         spin_unlock_irqrestore(&ioapic_lock, flags);
1384
1385         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mp_apicid);
1386         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1387         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
1388         printk(KERN_DEBUG ".......    : Delivery Type: %X\n", reg_00.bits.delivery_type);
1389         printk(KERN_DEBUG ".......    : LTS          : %X\n", reg_00.bits.LTS);
1390
1391         printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
1392         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
1393
1394         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
1395         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
1396
1397         /*
1398          * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1399          * but the value of reg_02 is read as the previous read register
1400          * value, so ignore it if reg_02 == reg_01.
1401          */
1402         if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1403                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1404                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
1405         }
1406
1407         /*
1408          * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1409          * or reg_03, but the value of reg_0[23] is read as the previous read
1410          * register value, so ignore it if reg_03 == reg_0[12].
1411          */
1412         if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1413             reg_03.raw != reg_01.raw) {
1414                 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1415                 printk(KERN_DEBUG ".......     : Boot DT    : %X\n", reg_03.bits.boot_DT);
1416         }
1417
1418         printk(KERN_DEBUG ".... IRQ redirection table:\n");
1419
1420         printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1421                           " Stat Dest Deli Vect:   \n");
1422
1423         for (i = 0; i <= reg_01.bits.entries; i++) {
1424                 struct IO_APIC_route_entry entry;
1425
1426                 entry = ioapic_read_entry(apic, i);
1427
1428                 printk(KERN_DEBUG " %02x %03X %02X  ",
1429                         i,
1430                         entry.dest.logical.logical_dest,
1431                         entry.dest.physical.physical_dest
1432                 );
1433
1434                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
1435                         entry.mask,
1436                         entry.trigger,
1437                         entry.irr,
1438                         entry.polarity,
1439                         entry.delivery_status,
1440                         entry.dest_mode,
1441                         entry.delivery_mode,
1442                         entry.vector
1443                 );
1444         }
1445         }
1446         printk(KERN_DEBUG "IRQ to pin mappings:\n");
1447         for (i = 0; i < NR_IRQS; i++) {
1448                 struct irq_pin_list *entry = irq_2_pin + i;
1449                 if (entry->pin < 0)
1450                         continue;
1451                 printk(KERN_DEBUG "IRQ%d ", i);
1452                 for (;;) {
1453                         printk("-> %d:%d", entry->apic, entry->pin);
1454                         if (!entry->next)
1455                                 break;
1456                         entry = irq_2_pin + entry->next;
1457                 }
1458                 printk("\n");
1459         }
1460
1461         printk(KERN_INFO ".................................... done.\n");
1462
1463         return;
1464 }
1465
1466 __apicdebuginit(void) print_APIC_bitfield(int base)
1467 {
1468         unsigned int v;
1469         int i, j;
1470
1471         if (apic_verbosity == APIC_QUIET)
1472                 return;
1473
1474         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1475         for (i = 0; i < 8; i++) {
1476                 v = apic_read(base + i*0x10);
1477                 for (j = 0; j < 32; j++) {
1478                         if (v & (1<<j))
1479                                 printk("1");
1480                         else
1481                                 printk("0");
1482                 }
1483                 printk("\n");
1484         }
1485 }
1486
1487 __apicdebuginit(void) print_local_APIC(void *dummy)
1488 {
1489         unsigned int v, ver, maxlvt;
1490
1491         if (apic_verbosity == APIC_QUIET)
1492                 return;
1493
1494         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1495                 smp_processor_id(), hard_smp_processor_id());
1496         v = apic_read(APIC_ID);
1497         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v,
1498                         GET_APIC_ID(read_apic_id()));
1499         v = apic_read(APIC_LVR);
1500         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1501         ver = GET_APIC_VERSION(v);
1502         maxlvt = lapic_get_maxlvt();
1503
1504         v = apic_read(APIC_TASKPRI);
1505         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1506
1507         if (APIC_INTEGRATED(ver)) {                     /* !82489DX */
1508                 v = apic_read(APIC_ARBPRI);
1509                 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1510                         v & APIC_ARBPRI_MASK);
1511                 v = apic_read(APIC_PROCPRI);
1512                 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1513         }
1514
1515         v = apic_read(APIC_EOI);
1516         printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1517         v = apic_read(APIC_RRR);
1518         printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1519         v = apic_read(APIC_LDR);
1520         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1521         v = apic_read(APIC_DFR);
1522         printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1523         v = apic_read(APIC_SPIV);
1524         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1525
1526         printk(KERN_DEBUG "... APIC ISR field:\n");
1527         print_APIC_bitfield(APIC_ISR);
1528         printk(KERN_DEBUG "... APIC TMR field:\n");
1529         print_APIC_bitfield(APIC_TMR);
1530         printk(KERN_DEBUG "... APIC IRR field:\n");
1531         print_APIC_bitfield(APIC_IRR);
1532
1533         if (APIC_INTEGRATED(ver)) {             /* !82489DX */
1534                 if (maxlvt > 3)         /* Due to the Pentium erratum 3AP. */
1535                         apic_write(APIC_ESR, 0);
1536                 v = apic_read(APIC_ESR);
1537                 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1538         }
1539
1540         v = apic_read(APIC_ICR);
1541         printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1542         v = apic_read(APIC_ICR2);
1543         printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1544
1545         v = apic_read(APIC_LVTT);
1546         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1547
1548         if (maxlvt > 3) {                       /* PC is LVT#4. */
1549                 v = apic_read(APIC_LVTPC);
1550                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1551         }
1552         v = apic_read(APIC_LVT0);
1553         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1554         v = apic_read(APIC_LVT1);
1555         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1556
1557         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1558                 v = apic_read(APIC_LVTERR);
1559                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1560         }
1561
1562         v = apic_read(APIC_TMICT);
1563         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1564         v = apic_read(APIC_TMCCT);
1565         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1566         v = apic_read(APIC_TDCR);
1567         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1568         printk("\n");
1569 }
1570
1571 __apicdebuginit(void) print_all_local_APICs(void)
1572 {
1573         on_each_cpu(print_local_APIC, NULL, 1);
1574 }
1575
1576 __apicdebuginit(void) print_PIC(void)
1577 {
1578         unsigned int v;
1579         unsigned long flags;
1580
1581         if (apic_verbosity == APIC_QUIET)
1582                 return;
1583
1584         printk(KERN_DEBUG "\nprinting PIC contents\n");
1585
1586         spin_lock_irqsave(&i8259A_lock, flags);
1587
1588         v = inb(0xa1) << 8 | inb(0x21);
1589         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1590
1591         v = inb(0xa0) << 8 | inb(0x20);
1592         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1593
1594         outb(0x0b, 0xa0);
1595         outb(0x0b, 0x20);
1596         v = inb(0xa0) << 8 | inb(0x20);
1597         outb(0x0a, 0xa0);
1598         outb(0x0a, 0x20);
1599
1600         spin_unlock_irqrestore(&i8259A_lock, flags);
1601
1602         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1603
1604         v = inb(0x4d1) << 8 | inb(0x4d0);
1605         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1606 }
1607
1608 __apicdebuginit(int) print_all_ICs(void)
1609 {
1610         print_PIC();
1611         print_all_local_APICs();
1612         print_IO_APIC();
1613
1614         return 0;
1615 }
1616
1617 fs_initcall(print_all_ICs);
1618
1619
1620 static void __init enable_IO_APIC(void)
1621 {
1622         union IO_APIC_reg_01 reg_01;
1623         int i8259_apic, i8259_pin;
1624         int i, apic;
1625         unsigned long flags;
1626
1627         for (i = 0; i < PIN_MAP_SIZE; i++) {
1628                 irq_2_pin[i].pin = -1;
1629                 irq_2_pin[i].next = 0;
1630         }
1631         if (!pirqs_enabled)
1632                 for (i = 0; i < MAX_PIRQS; i++)
1633                         pirq_entries[i] = -1;
1634
1635         /*
1636          * The number of IO-APIC IRQ registers (== #pins):
1637          */
1638         for (apic = 0; apic < nr_ioapics; apic++) {
1639                 spin_lock_irqsave(&ioapic_lock, flags);
1640                 reg_01.raw = io_apic_read(apic, 1);
1641                 spin_unlock_irqrestore(&ioapic_lock, flags);
1642                 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1643         }
1644         for (apic = 0; apic < nr_ioapics; apic++) {
1645                 int pin;
1646                 /* See if any of the pins is in ExtINT mode */
1647                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1648                         struct IO_APIC_route_entry entry;
1649                         entry = ioapic_read_entry(apic, pin);
1650
1651
1652                         /* If the interrupt line is enabled and in ExtInt mode
1653                          * I have found the pin where the i8259 is connected.
1654                          */
1655                         if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1656                                 ioapic_i8259.apic = apic;
1657                                 ioapic_i8259.pin  = pin;
1658                                 goto found_i8259;
1659                         }
1660                 }
1661         }
1662  found_i8259:
1663         /* Look to see what if the MP table has reported the ExtINT */
1664         /* If we could not find the appropriate pin by looking at the ioapic
1665          * the i8259 probably is not connected the ioapic but give the
1666          * mptable a chance anyway.
1667          */
1668         i8259_pin  = find_isa_irq_pin(0, mp_ExtINT);
1669         i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1670         /* Trust the MP table if nothing is setup in the hardware */
1671         if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1672                 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1673                 ioapic_i8259.pin  = i8259_pin;
1674                 ioapic_i8259.apic = i8259_apic;
1675         }
1676         /* Complain if the MP table and the hardware disagree */
1677         if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1678                 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1679         {
1680                 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1681         }
1682
1683         /*
1684          * Do not trust the IO-APIC being empty at bootup
1685          */
1686         clear_IO_APIC();
1687 }
1688
1689 /*
1690  * Not an __init, needed by the reboot code
1691  */
1692 void disable_IO_APIC(void)
1693 {
1694         /*
1695          * Clear the IO-APIC before rebooting:
1696          */
1697         clear_IO_APIC();
1698
1699         /*
1700          * If the i8259 is routed through an IOAPIC
1701          * Put that IOAPIC in virtual wire mode
1702          * so legacy interrupts can be delivered.
1703          */
1704         if (ioapic_i8259.pin != -1) {
1705                 struct IO_APIC_route_entry entry;
1706
1707                 memset(&entry, 0, sizeof(entry));
1708                 entry.mask            = 0; /* Enabled */
1709                 entry.trigger         = 0; /* Edge */
1710                 entry.irr             = 0;
1711                 entry.polarity        = 0; /* High */
1712                 entry.delivery_status = 0;
1713                 entry.dest_mode       = 0; /* Physical */
1714                 entry.delivery_mode   = dest_ExtINT; /* ExtInt */
1715                 entry.vector          = 0;
1716                 entry.dest.physical.physical_dest =
1717                                         GET_APIC_ID(read_apic_id());
1718
1719                 /*
1720                  * Add it to the IO-APIC irq-routing table:
1721                  */
1722                 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1723         }
1724         disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1725 }
1726
1727 /*
1728  * function to set the IO-APIC physical IDs based on the
1729  * values stored in the MPC table.
1730  *
1731  * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
1732  */
1733
1734 static void __init setup_ioapic_ids_from_mpc(void)
1735 {
1736         union IO_APIC_reg_00 reg_00;
1737         physid_mask_t phys_id_present_map;
1738         int apic;
1739         int i;
1740         unsigned char old_id;
1741         unsigned long flags;
1742
1743 #ifdef CONFIG_X86_NUMAQ
1744         if (found_numaq)
1745                 return;
1746 #endif
1747
1748         /*
1749          * Don't check I/O APIC IDs for xAPIC systems.  They have
1750          * no meaning without the serial APIC bus.
1751          */
1752         if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1753                 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
1754                 return;
1755         /*
1756          * This is broken; anything with a real cpu count has to
1757          * circumvent this idiocy regardless.
1758          */
1759         phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1760
1761         /*
1762          * Set the IOAPIC ID to the value stored in the MPC table.
1763          */
1764         for (apic = 0; apic < nr_ioapics; apic++) {
1765
1766                 /* Read the register 0 value */
1767                 spin_lock_irqsave(&ioapic_lock, flags);
1768                 reg_00.raw = io_apic_read(apic, 0);
1769                 spin_unlock_irqrestore(&ioapic_lock, flags);
1770
1771                 old_id = mp_ioapics[apic].mp_apicid;
1772
1773                 if (mp_ioapics[apic].mp_apicid >= get_physical_broadcast()) {
1774                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1775                                 apic, mp_ioapics[apic].mp_apicid);
1776                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1777                                 reg_00.bits.ID);
1778                         mp_ioapics[apic].mp_apicid = reg_00.bits.ID;
1779                 }
1780
1781                 /*
1782                  * Sanity check, is the ID really free? Every APIC in a
1783                  * system must have a unique ID or we get lots of nice
1784                  * 'stuck on smp_invalidate_needed IPI wait' messages.
1785                  */
1786                 if (check_apicid_used(phys_id_present_map,
1787                                         mp_ioapics[apic].mp_apicid)) {
1788                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1789                                 apic, mp_ioapics[apic].mp_apicid);
1790                         for (i = 0; i < get_physical_broadcast(); i++)
1791                                 if (!physid_isset(i, phys_id_present_map))
1792                                         break;
1793                         if (i >= get_physical_broadcast())
1794                                 panic("Max APIC ID exceeded!\n");
1795                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1796                                 i);
1797                         physid_set(i, phys_id_present_map);
1798                         mp_ioapics[apic].mp_apicid = i;
1799                 } else {
1800                         physid_mask_t tmp;
1801                         tmp = apicid_to_cpu_present(mp_ioapics[apic].mp_apicid);
1802                         apic_printk(APIC_VERBOSE, "Setting %d in the "
1803                                         "phys_id_present_map\n",
1804                                         mp_ioapics[apic].mp_apicid);
1805                         physids_or(phys_id_present_map, phys_id_present_map, tmp);
1806                 }
1807
1808
1809                 /*
1810                  * We need to adjust the IRQ routing table
1811                  * if the ID changed.
1812                  */
1813                 if (old_id != mp_ioapics[apic].mp_apicid)
1814                         for (i = 0; i < mp_irq_entries; i++)
1815                                 if (mp_irqs[i].mp_dstapic == old_id)
1816                                         mp_irqs[i].mp_dstapic
1817                                                 = mp_ioapics[apic].mp_apicid;
1818
1819                 /*
1820                  * Read the right value from the MPC table and
1821                  * write it into the ID register.
1822                  */
1823                 apic_printk(APIC_VERBOSE, KERN_INFO
1824                         "...changing IO-APIC physical APIC ID to %d ...",
1825                         mp_ioapics[apic].mp_apicid);
1826
1827                 reg_00.bits.ID = mp_ioapics[apic].mp_apicid;
1828                 spin_lock_irqsave(&ioapic_lock, flags);
1829                 io_apic_write(apic, 0, reg_00.raw);
1830                 spin_unlock_irqrestore(&ioapic_lock, flags);
1831
1832                 /*
1833                  * Sanity check
1834                  */
1835                 spin_lock_irqsave(&ioapic_lock, flags);
1836                 reg_00.raw = io_apic_read(apic, 0);
1837                 spin_unlock_irqrestore(&ioapic_lock, flags);
1838                 if (reg_00.bits.ID != mp_ioapics[apic].mp_apicid)
1839                         printk("could not set ID!\n");
1840                 else
1841                         apic_printk(APIC_VERBOSE, " ok.\n");
1842         }
1843 }
1844
1845 int no_timer_check __initdata;
1846
1847 static int __init notimercheck(char *s)
1848 {
1849         no_timer_check = 1;
1850         return 1;
1851 }
1852 __setup("no_timer_check", notimercheck);
1853
1854 /*
1855  * There is a nasty bug in some older SMP boards, their mptable lies
1856  * about the timer IRQ. We do the following to work around the situation:
1857  *
1858  *      - timer IRQ defaults to IO-APIC IRQ
1859  *      - if this function detects that timer IRQs are defunct, then we fall
1860  *        back to ISA timer IRQs
1861  */
1862 static int __init timer_irq_works(void)
1863 {
1864         unsigned long t1 = jiffies;
1865         unsigned long flags;
1866
1867         if (no_timer_check)
1868                 return 1;
1869
1870         local_save_flags(flags);
1871         local_irq_enable();
1872         /* Let ten ticks pass... */
1873         mdelay((10 * 1000) / HZ);
1874         local_irq_restore(flags);
1875
1876         /*
1877          * Expect a few ticks at least, to be sure some possible
1878          * glue logic does not lock up after one or two first
1879          * ticks in a non-ExtINT mode.  Also the local APIC
1880          * might have cached one ExtINT interrupt.  Finally, at
1881          * least one tick may be lost due to delays.
1882          */
1883         if (time_after(jiffies, t1 + 4))
1884                 return 1;
1885
1886         return 0;
1887 }
1888
1889 /*
1890  * In the SMP+IOAPIC case it might happen that there are an unspecified
1891  * number of pending IRQ events unhandled. These cases are very rare,
1892  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1893  * better to do it this way as thus we do not have to be aware of
1894  * 'pending' interrupts in the IRQ path, except at this point.
1895  */
1896 /*
1897  * Edge triggered needs to resend any interrupt
1898  * that was delayed but this is now handled in the device
1899  * independent code.
1900  */
1901
1902 /*
1903  * Startup quirk:
1904  *
1905  * Starting up a edge-triggered IO-APIC interrupt is
1906  * nasty - we need to make sure that we get the edge.
1907  * If it is already asserted for some reason, we need
1908  * return 1 to indicate that is was pending.
1909  *
1910  * This is not complete - we should be able to fake
1911  * an edge even if it isn't on the 8259A...
1912  *
1913  * (We do this for level-triggered IRQs too - it cannot hurt.)
1914  */
1915 static unsigned int startup_ioapic_irq(unsigned int irq)
1916 {
1917         int was_pending = 0;
1918         unsigned long flags;
1919
1920         spin_lock_irqsave(&ioapic_lock, flags);
1921         if (irq < 16) {
1922                 disable_8259A_irq(irq);
1923                 if (i8259A_irq_pending(irq))
1924                         was_pending = 1;
1925         }
1926         __unmask_IO_APIC_irq(irq);
1927         spin_unlock_irqrestore(&ioapic_lock, flags);
1928
1929         return was_pending;
1930 }
1931
1932 static void ack_ioapic_irq(unsigned int irq)
1933 {
1934         move_native_irq(irq);
1935         ack_APIC_irq();
1936 }
1937
1938 static void ack_ioapic_quirk_irq(unsigned int irq)
1939 {
1940         unsigned long v;
1941         int i;
1942
1943         move_native_irq(irq);
1944 /*
1945  * It appears there is an erratum which affects at least version 0x11
1946  * of I/O APIC (that's the 82093AA and cores integrated into various
1947  * chipsets).  Under certain conditions a level-triggered interrupt is
1948  * erroneously delivered as edge-triggered one but the respective IRR
1949  * bit gets set nevertheless.  As a result the I/O unit expects an EOI
1950  * message but it will never arrive and further interrupts are blocked
1951  * from the source.  The exact reason is so far unknown, but the
1952  * phenomenon was observed when two consecutive interrupt requests
1953  * from a given source get delivered to the same CPU and the source is
1954  * temporarily disabled in between.
1955  *
1956  * A workaround is to simulate an EOI message manually.  We achieve it
1957  * by setting the trigger mode to edge and then to level when the edge
1958  * trigger mode gets detected in the TMR of a local APIC for a
1959  * level-triggered interrupt.  We mask the source for the time of the
1960  * operation to prevent an edge-triggered interrupt escaping meanwhile.
1961  * The idea is from Manfred Spraul.  --macro
1962  */
1963         i = irq_vector[irq];
1964
1965         v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1966
1967         ack_APIC_irq();
1968
1969         if (!(v & (1 << (i & 0x1f)))) {
1970                 atomic_inc(&irq_mis_count);
1971                 spin_lock(&ioapic_lock);
1972                 __mask_and_edge_IO_APIC_irq(irq);
1973                 __unmask_and_level_IO_APIC_irq(irq);
1974                 spin_unlock(&ioapic_lock);
1975         }
1976 }
1977
1978 static int ioapic_retrigger_irq(unsigned int irq)
1979 {
1980         send_IPI_self(irq_vector[irq]);
1981
1982         return 1;
1983 }
1984
1985 static struct irq_chip ioapic_chip __read_mostly = {
1986         .name           = "IO-APIC",
1987         .startup        = startup_ioapic_irq,
1988         .mask           = mask_IO_APIC_irq,
1989         .unmask         = unmask_IO_APIC_irq,
1990         .ack            = ack_ioapic_irq,
1991         .eoi            = ack_ioapic_quirk_irq,
1992 #ifdef CONFIG_SMP
1993         .set_affinity   = set_ioapic_affinity_irq,
1994 #endif
1995         .retrigger      = ioapic_retrigger_irq,
1996 };
1997
1998
1999 static inline void init_IO_APIC_traps(void)
2000 {
2001         int irq;
2002
2003         /*
2004          * NOTE! The local APIC isn't very good at handling
2005          * multiple interrupts at the same interrupt level.
2006          * As the interrupt level is determined by taking the
2007          * vector number and shifting that right by 4, we
2008          * want to spread these out a bit so that they don't
2009          * all fall in the same interrupt level.
2010          *
2011          * Also, we've got to be careful not to trash gate
2012          * 0x80, because int 0x80 is hm, kind of importantish. ;)
2013          */
2014         for (irq = 0; irq < NR_IRQS ; irq++) {
2015                 if (IO_APIC_IRQ(irq) && !irq_vector[irq]) {
2016                         /*
2017                          * Hmm.. We don't have an entry for this,
2018                          * so default to an old-fashioned 8259
2019                          * interrupt if we can..
2020                          */
2021                         if (irq < 16)
2022                                 make_8259A_irq(irq);
2023                         else
2024                                 /* Strange. Oh, well.. */
2025                                 irq_desc[irq].chip = &no_irq_chip;
2026                 }
2027         }
2028 }
2029
2030 /*
2031  * The local APIC irq-chip implementation:
2032  */
2033
2034 static void ack_lapic_irq(unsigned int irq)
2035 {
2036         ack_APIC_irq();
2037 }
2038
2039 static void mask_lapic_irq(unsigned int irq)
2040 {
2041         unsigned long v;
2042
2043         v = apic_read(APIC_LVT0);
2044         apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2045 }
2046
2047 static void unmask_lapic_irq(unsigned int irq)
2048 {
2049         unsigned long v;
2050
2051         v = apic_read(APIC_LVT0);
2052         apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2053 }
2054
2055 static struct irq_chip lapic_chip __read_mostly = {
2056         .name           = "local-APIC",
2057         .mask           = mask_lapic_irq,
2058         .unmask         = unmask_lapic_irq,
2059         .ack            = ack_lapic_irq,
2060 };
2061
2062 static void lapic_register_intr(int irq, int vector)
2063 {
2064         irq_desc[irq].status &= ~IRQ_LEVEL;
2065         set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2066                                       "edge");
2067         set_intr_gate(vector, interrupt[irq]);
2068 }
2069
2070 static void __init setup_nmi(void)
2071 {
2072         /*
2073          * Dirty trick to enable the NMI watchdog ...
2074          * We put the 8259A master into AEOI mode and
2075          * unmask on all local APICs LVT0 as NMI.
2076          *
2077          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2078          * is from Maciej W. Rozycki - so we do not have to EOI from
2079          * the NMI handler or the timer interrupt.
2080          */
2081         apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2082
2083         enable_NMI_through_LVT0();
2084
2085         apic_printk(APIC_VERBOSE, " done.\n");
2086 }
2087
2088 /*
2089  * This looks a bit hackish but it's about the only one way of sending
2090  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
2091  * not support the ExtINT mode, unfortunately.  We need to send these
2092  * cycles as some i82489DX-based boards have glue logic that keeps the
2093  * 8259A interrupt line asserted until INTA.  --macro
2094  */
2095 static inline void __init unlock_ExtINT_logic(void)
2096 {
2097         int apic, pin, i;
2098         struct IO_APIC_route_entry entry0, entry1;
2099         unsigned char save_control, save_freq_select;
2100
2101         pin  = find_isa_irq_pin(8, mp_INT);
2102         if (pin == -1) {
2103                 WARN_ON_ONCE(1);
2104                 return;
2105         }
2106         apic = find_isa_irq_apic(8, mp_INT);
2107         if (apic == -1) {
2108                 WARN_ON_ONCE(1);
2109                 return;
2110         }
2111
2112         entry0 = ioapic_read_entry(apic, pin);
2113         clear_IO_APIC_pin(apic, pin);
2114
2115         memset(&entry1, 0, sizeof(entry1));
2116
2117         entry1.dest_mode = 0;                   /* physical delivery */
2118         entry1.mask = 0;                        /* unmask IRQ now */
2119         entry1.dest.physical.physical_dest = hard_smp_processor_id();
2120         entry1.delivery_mode = dest_ExtINT;
2121         entry1.polarity = entry0.polarity;
2122         entry1.trigger = 0;
2123         entry1.vector = 0;
2124
2125         ioapic_write_entry(apic, pin, entry1);
2126
2127         save_control = CMOS_READ(RTC_CONTROL);
2128         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2129         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2130                    RTC_FREQ_SELECT);
2131         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2132
2133         i = 100;
2134         while (i-- > 0) {
2135                 mdelay(10);
2136                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2137                         i -= 10;
2138         }
2139
2140         CMOS_WRITE(save_control, RTC_CONTROL);
2141         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2142         clear_IO_APIC_pin(apic, pin);
2143
2144         ioapic_write_entry(apic, pin, entry0);
2145 }
2146
2147 /*
2148  * This code may look a bit paranoid, but it's supposed to cooperate with
2149  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
2150  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
2151  * fanatically on his truly buggy board.
2152  */
2153 static inline void __init check_timer(void)
2154 {
2155         int apic1, pin1, apic2, pin2;
2156         int no_pin1 = 0;
2157         int vector;
2158         unsigned int ver;
2159         unsigned long flags;
2160
2161         local_irq_save(flags);
2162
2163         ver = apic_read(APIC_LVR);
2164         ver = GET_APIC_VERSION(ver);
2165
2166         /*
2167          * get/set the timer IRQ vector:
2168          */
2169         disable_8259A_irq(0);
2170         vector = assign_irq_vector(0);
2171         set_intr_gate(vector, interrupt[0]);
2172
2173         /*
2174          * As IRQ0 is to be enabled in the 8259A, the virtual
2175          * wire has to be disabled in the local APIC.  Also
2176          * timer interrupts need to be acknowledged manually in
2177          * the 8259A for the i82489DX when using the NMI
2178          * watchdog as that APIC treats NMIs as level-triggered.
2179          * The AEOI mode will finish them in the 8259A
2180          * automatically.
2181          */
2182         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2183         init_8259A(1);
2184         timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
2185
2186         pin1  = find_isa_irq_pin(0, mp_INT);
2187         apic1 = find_isa_irq_apic(0, mp_INT);
2188         pin2  = ioapic_i8259.pin;
2189         apic2 = ioapic_i8259.apic;
2190
2191         apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2192                     "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2193                     vector, apic1, pin1, apic2, pin2);
2194
2195         /*
2196          * Some BIOS writers are clueless and report the ExtINTA
2197          * I/O APIC input from the cascaded 8259A as the timer
2198          * interrupt input.  So just in case, if only one pin
2199          * was found above, try it both directly and through the
2200          * 8259A.
2201          */
2202         if (pin1 == -1) {
2203                 pin1 = pin2;
2204                 apic1 = apic2;
2205                 no_pin1 = 1;
2206         } else if (pin2 == -1) {
2207                 pin2 = pin1;
2208                 apic2 = apic1;
2209         }
2210
2211         if (pin1 != -1) {
2212                 /*
2213                  * Ok, does IRQ0 through the IOAPIC work?
2214                  */
2215                 if (no_pin1) {
2216                         add_pin_to_irq(0, apic1, pin1);
2217                         setup_timer_IRQ0_pin(apic1, pin1, vector);
2218                 }
2219                 unmask_IO_APIC_irq(0);
2220                 if (timer_irq_works()) {
2221                         if (nmi_watchdog == NMI_IO_APIC) {
2222                                 setup_nmi();
2223                                 enable_8259A_irq(0);
2224                         }
2225                         if (disable_timer_pin_1 > 0)
2226                                 clear_IO_APIC_pin(0, pin1);
2227                         goto out;
2228                 }
2229                 clear_IO_APIC_pin(apic1, pin1);
2230                 if (!no_pin1)
2231                         apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2232                                     "8254 timer not connected to IO-APIC\n");
2233
2234                 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2235                             "(IRQ0) through the 8259A ...\n");
2236                 apic_printk(APIC_QUIET, KERN_INFO
2237                             "..... (found apic %d pin %d) ...\n", apic2, pin2);
2238                 /*
2239                  * legacy devices should be connected to IO APIC #0
2240                  */
2241                 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
2242                 setup_timer_IRQ0_pin(apic2, pin2, vector);
2243                 unmask_IO_APIC_irq(0);
2244                 enable_8259A_irq(0);
2245                 if (timer_irq_works()) {
2246                         apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2247                         timer_through_8259 = 1;
2248                         if (nmi_watchdog == NMI_IO_APIC) {
2249                                 disable_8259A_irq(0);
2250                                 setup_nmi();
2251                                 enable_8259A_irq(0);
2252                         }
2253                         goto out;
2254                 }
2255                 /*
2256                  * Cleanup, just in case ...
2257                  */
2258                 disable_8259A_irq(0);
2259                 clear_IO_APIC_pin(apic2, pin2);
2260                 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2261         }
2262
2263         if (nmi_watchdog == NMI_IO_APIC) {
2264                 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
2265                             "through the IO-APIC - disabling NMI Watchdog!\n");
2266                 nmi_watchdog = NMI_NONE;
2267         }
2268         timer_ack = 0;
2269
2270         apic_printk(APIC_QUIET, KERN_INFO
2271                     "...trying to set up timer as Virtual Wire IRQ...\n");
2272
2273         lapic_register_intr(0, vector);
2274         apic_write(APIC_LVT0, APIC_DM_FIXED | vector);  /* Fixed mode */
2275         enable_8259A_irq(0);
2276
2277         if (timer_irq_works()) {
2278                 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2279                 goto out;
2280         }
2281         disable_8259A_irq(0);
2282         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
2283         apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
2284
2285         apic_printk(APIC_QUIET, KERN_INFO
2286                     "...trying to set up timer as ExtINT IRQ...\n");
2287
2288         init_8259A(0);
2289         make_8259A_irq(0);
2290         apic_write(APIC_LVT0, APIC_DM_EXTINT);
2291
2292         unlock_ExtINT_logic();
2293
2294         if (timer_irq_works()) {
2295                 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2296                 goto out;
2297         }
2298         apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
2299         panic("IO-APIC + timer doesn't work!  Boot with apic=debug and send a "
2300                 "report.  Then try booting with the 'noapic' option.\n");
2301 out:
2302         local_irq_restore(flags);
2303 }
2304
2305 /*
2306  * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2307  * to devices.  However there may be an I/O APIC pin available for
2308  * this interrupt regardless.  The pin may be left unconnected, but
2309  * typically it will be reused as an ExtINT cascade interrupt for
2310  * the master 8259A.  In the MPS case such a pin will normally be
2311  * reported as an ExtINT interrupt in the MP table.  With ACPI
2312  * there is no provision for ExtINT interrupts, and in the absence
2313  * of an override it would be treated as an ordinary ISA I/O APIC
2314  * interrupt, that is edge-triggered and unmasked by default.  We
2315  * used to do this, but it caused problems on some systems because
2316  * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2317  * the same ExtINT cascade interrupt to drive the local APIC of the
2318  * bootstrap processor.  Therefore we refrain from routing IRQ2 to
2319  * the I/O APIC in all cases now.  No actual device should request
2320  * it anyway.  --macro
2321  */
2322 #define PIC_IRQS        (1 << PIC_CASCADE_IR)
2323
2324 void __init setup_IO_APIC(void)
2325 {
2326         int i;
2327
2328         /* Reserve all the system vectors. */
2329         for (i = first_system_vector; i < NR_VECTORS; i++)
2330                 set_bit(i, used_vectors);
2331
2332         enable_IO_APIC();
2333
2334         io_apic_irqs = ~PIC_IRQS;
2335
2336         printk("ENABLING IO-APIC IRQs\n");
2337
2338         /*
2339          * Set up IO-APIC IRQ routing.
2340          */
2341         if (!acpi_ioapic)
2342                 setup_ioapic_ids_from_mpc();
2343         sync_Arb_IDs();
2344         setup_IO_APIC_irqs();
2345         init_IO_APIC_traps();
2346         check_timer();
2347 }
2348
2349 /*
2350  *      Called after all the initialization is done. If we didnt find any
2351  *      APIC bugs then we can allow the modify fast path
2352  */
2353
2354 static int __init io_apic_bug_finalize(void)
2355 {
2356         if (sis_apic_bug == -1)
2357                 sis_apic_bug = 0;
2358         return 0;
2359 }
2360
2361 late_initcall(io_apic_bug_finalize);
2362
2363 struct sysfs_ioapic_data {
2364         struct sys_device dev;
2365         struct IO_APIC_route_entry entry[0];
2366 };
2367 static struct sysfs_ioapic_data *mp_ioapic_data[MAX_IO_APICS];
2368
2369 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2370 {
2371         struct IO_APIC_route_entry *entry;
2372         struct sysfs_ioapic_data *data;
2373         int i;
2374
2375         data = container_of(dev, struct sysfs_ioapic_data, dev);
2376         entry = data->entry;
2377         for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
2378                 entry[i] = ioapic_read_entry(dev->id, i);
2379
2380         return 0;
2381 }
2382
2383 static int ioapic_resume(struct sys_device *dev)
2384 {
2385         struct IO_APIC_route_entry *entry;
2386         struct sysfs_ioapic_data *data;
2387         unsigned long flags;
2388         union IO_APIC_reg_00 reg_00;
2389         int i;
2390
2391         data = container_of(dev, struct sysfs_ioapic_data, dev);
2392         entry = data->entry;
2393
2394         spin_lock_irqsave(&ioapic_lock, flags);
2395         reg_00.raw = io_apic_read(dev->id, 0);
2396         if (reg_00.bits.ID != mp_ioapics[dev->id].mp_apicid) {
2397                 reg_00.bits.ID = mp_ioapics[dev->id].mp_apicid;
2398                 io_apic_write(dev->id, 0, reg_00.raw);
2399         }
2400         spin_unlock_irqrestore(&ioapic_lock, flags);
2401         for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
2402                 ioapic_write_entry(dev->id, i, entry[i]);
2403
2404         return 0;
2405 }
2406
2407 static struct sysdev_class ioapic_sysdev_class = {
2408         .name = "ioapic",
2409         .suspend = ioapic_suspend,
2410         .resume = ioapic_resume,
2411 };
2412
2413 static int __init ioapic_init_sysfs(void)
2414 {
2415         struct sys_device *dev;
2416         int i, size, error = 0;
2417
2418         error = sysdev_class_register(&ioapic_sysdev_class);
2419         if (error)
2420                 return error;
2421
2422         for (i = 0; i < nr_ioapics; i++) {
2423                 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2424                         * sizeof(struct IO_APIC_route_entry);
2425                 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
2426                 if (!mp_ioapic_data[i]) {
2427                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2428                         continue;
2429                 }
2430                 dev = &mp_ioapic_data[i]->dev;
2431                 dev->id = i;
2432                 dev->cls = &ioapic_sysdev_class;
2433                 error = sysdev_register(dev);
2434                 if (error) {
2435                         kfree(mp_ioapic_data[i]);
2436                         mp_ioapic_data[i] = NULL;
2437                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2438                         continue;
2439                 }
2440         }
2441
2442         return 0;
2443 }
2444
2445 device_initcall(ioapic_init_sysfs);
2446
2447 /*
2448  * Dynamic irq allocate and deallocation
2449  */
2450 int create_irq(void)
2451 {
2452         /* Allocate an unused irq */
2453         int irq, new, vector = 0;
2454         unsigned long flags;
2455
2456         irq = -ENOSPC;
2457         spin_lock_irqsave(&vector_lock, flags);
2458         for (new = (NR_IRQS - 1); new >= 0; new--) {
2459                 if (platform_legacy_irq(new))
2460                         continue;
2461                 if (irq_vector[new] != 0)
2462                         continue;
2463                 vector = __assign_irq_vector(new);
2464                 if (likely(vector > 0))
2465                         irq = new;
2466                 break;
2467         }
2468         spin_unlock_irqrestore(&vector_lock, flags);
2469
2470         if (irq >= 0) {
2471                 set_intr_gate(vector, interrupt[irq]);
2472                 dynamic_irq_init(irq);
2473         }
2474         return irq;
2475 }
2476
2477 void destroy_irq(unsigned int irq)
2478 {
2479         unsigned long flags;
2480
2481         dynamic_irq_cleanup(irq);
2482
2483         spin_lock_irqsave(&vector_lock, flags);
2484         clear_bit(irq_vector[irq], used_vectors);
2485         irq_vector[irq] = 0;
2486         spin_unlock_irqrestore(&vector_lock, flags);
2487 }
2488
2489 /*
2490  * MSI message composition
2491  */
2492 #ifdef CONFIG_PCI_MSI
2493 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
2494 {
2495         int vector;
2496         unsigned dest;
2497
2498         vector = assign_irq_vector(irq);
2499         if (vector >= 0) {
2500                 dest = cpu_mask_to_apicid(TARGET_CPUS);
2501
2502                 msg->address_hi = MSI_ADDR_BASE_HI;
2503                 msg->address_lo =
2504                         MSI_ADDR_BASE_LO |
2505                         ((INT_DEST_MODE == 0) ?
2506 MSI_ADDR_DEST_MODE_PHYSICAL:
2507                                 MSI_ADDR_DEST_MODE_LOGICAL) |
2508                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2509                                 MSI_ADDR_REDIRECTION_CPU:
2510                                 MSI_ADDR_REDIRECTION_LOWPRI) |
2511                         MSI_ADDR_DEST_ID(dest);
2512
2513                 msg->data =
2514                         MSI_DATA_TRIGGER_EDGE |
2515                         MSI_DATA_LEVEL_ASSERT |
2516                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2517 MSI_DATA_DELIVERY_FIXED:
2518                                 MSI_DATA_DELIVERY_LOWPRI) |
2519                         MSI_DATA_VECTOR(vector);
2520         }
2521         return vector;
2522 }
2523
2524 #ifdef CONFIG_SMP
2525 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
2526 {
2527         struct msi_msg msg;
2528         unsigned int dest;
2529         cpumask_t tmp;
2530         int vector;
2531
2532         cpus_and(tmp, mask, cpu_online_map);
2533         if (cpus_empty(tmp))
2534                 tmp = TARGET_CPUS;
2535
2536         vector = assign_irq_vector(irq);
2537         if (vector < 0)
2538                 return;
2539
2540         dest = cpu_mask_to_apicid(mask);
2541
2542         read_msi_msg(irq, &msg);
2543
2544         msg.data &= ~MSI_DATA_VECTOR_MASK;
2545         msg.data |= MSI_DATA_VECTOR(vector);
2546         msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2547         msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2548
2549         write_msi_msg(irq, &msg);
2550         irq_desc[irq].affinity = mask;
2551 }
2552 #endif /* CONFIG_SMP */
2553
2554 /*
2555  * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2556  * which implement the MSI or MSI-X Capability Structure.
2557  */
2558 static struct irq_chip msi_chip = {
2559         .name           = "PCI-MSI",
2560         .unmask         = unmask_msi_irq,
2561         .mask           = mask_msi_irq,
2562         .ack            = ack_ioapic_irq,
2563 #ifdef CONFIG_SMP
2564         .set_affinity   = set_msi_irq_affinity,
2565 #endif
2566         .retrigger      = ioapic_retrigger_irq,
2567 };
2568
2569 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
2570 {
2571         struct msi_msg msg;
2572         int irq, ret;
2573         irq = create_irq();
2574         if (irq < 0)
2575                 return irq;
2576
2577         ret = msi_compose_msg(dev, irq, &msg);
2578         if (ret < 0) {
2579                 destroy_irq(irq);
2580                 return ret;
2581         }
2582
2583         set_irq_msi(irq, desc);
2584         write_msi_msg(irq, &msg);
2585
2586         set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq,
2587                                       "edge");
2588
2589         return 0;
2590 }
2591
2592 void arch_teardown_msi_irq(unsigned int irq)
2593 {
2594         destroy_irq(irq);
2595 }
2596
2597 #endif /* CONFIG_PCI_MSI */
2598
2599 /*
2600  * Hypertransport interrupt support
2601  */
2602 #ifdef CONFIG_HT_IRQ
2603
2604 #ifdef CONFIG_SMP
2605
2606 static void target_ht_irq(unsigned int irq, unsigned int dest)
2607 {
2608         struct ht_irq_msg msg;
2609         fetch_ht_irq_msg(irq, &msg);
2610
2611         msg.address_lo &= ~(HT_IRQ_LOW_DEST_ID_MASK);
2612         msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
2613
2614         msg.address_lo |= HT_IRQ_LOW_DEST_ID(dest);
2615         msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
2616
2617         write_ht_irq_msg(irq, &msg);
2618 }
2619
2620 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
2621 {
2622         unsigned int dest;
2623         cpumask_t tmp;
2624
2625         cpus_and(tmp, mask, cpu_online_map);
2626         if (cpus_empty(tmp))
2627                 tmp = TARGET_CPUS;
2628
2629         cpus_and(mask, tmp, CPU_MASK_ALL);
2630
2631         dest = cpu_mask_to_apicid(mask);
2632
2633         target_ht_irq(irq, dest);
2634         irq_desc[irq].affinity = mask;
2635 }
2636 #endif
2637
2638 static struct irq_chip ht_irq_chip = {
2639         .name           = "PCI-HT",
2640         .mask           = mask_ht_irq,
2641         .unmask         = unmask_ht_irq,
2642         .ack            = ack_ioapic_irq,
2643 #ifdef CONFIG_SMP
2644         .set_affinity   = set_ht_irq_affinity,
2645 #endif
2646         .retrigger      = ioapic_retrigger_irq,
2647 };
2648
2649 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2650 {
2651         int vector;
2652
2653         vector = assign_irq_vector(irq);
2654         if (vector >= 0) {
2655                 struct ht_irq_msg msg;
2656                 unsigned dest;
2657                 cpumask_t tmp;
2658
2659                 cpus_clear(tmp);
2660                 cpu_set(vector >> 8, tmp);
2661                 dest = cpu_mask_to_apicid(tmp);
2662
2663                 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
2664
2665                 msg.address_lo =
2666                         HT_IRQ_LOW_BASE |
2667                         HT_IRQ_LOW_DEST_ID(dest) |
2668                         HT_IRQ_LOW_VECTOR(vector) |
2669                         ((INT_DEST_MODE == 0) ?
2670                                 HT_IRQ_LOW_DM_PHYSICAL :
2671                                 HT_IRQ_LOW_DM_LOGICAL) |
2672                         HT_IRQ_LOW_RQEOI_EDGE |
2673                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2674                                 HT_IRQ_LOW_MT_FIXED :
2675                                 HT_IRQ_LOW_MT_ARBITRATED) |
2676                         HT_IRQ_LOW_IRQ_MASKED;
2677
2678                 write_ht_irq_msg(irq, &msg);
2679
2680                 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2681                                               handle_edge_irq, "edge");
2682         }
2683         return vector;
2684 }
2685 #endif /* CONFIG_HT_IRQ */
2686
2687 /* --------------------------------------------------------------------------
2688                         ACPI-based IOAPIC Configuration
2689    -------------------------------------------------------------------------- */
2690
2691 #ifdef CONFIG_ACPI
2692
2693 int __init io_apic_get_unique_id(int ioapic, int apic_id)
2694 {
2695         union IO_APIC_reg_00 reg_00;
2696         static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2697         physid_mask_t tmp;
2698         unsigned long flags;
2699         int i = 0;
2700
2701         /*
2702          * The P4 platform supports up to 256 APIC IDs on two separate APIC
2703          * buses (one for LAPICs, one for IOAPICs), where predecessors only
2704          * supports up to 16 on one shared APIC bus.
2705          *
2706          * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2707          *      advantage of new APIC bus architecture.
2708          */
2709
2710         if (physids_empty(apic_id_map))
2711                 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
2712
2713         spin_lock_irqsave(&ioapic_lock, flags);
2714         reg_00.raw = io_apic_read(ioapic, 0);
2715         spin_unlock_irqrestore(&ioapic_lock, flags);
2716
2717         if (apic_id >= get_physical_broadcast()) {
2718                 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2719                         "%d\n", ioapic, apic_id, reg_00.bits.ID);
2720                 apic_id = reg_00.bits.ID;
2721         }
2722
2723         /*
2724          * Every APIC in a system must have a unique ID or we get lots of nice
2725          * 'stuck on smp_invalidate_needed IPI wait' messages.
2726          */
2727         if (check_apicid_used(apic_id_map, apic_id)) {
2728
2729                 for (i = 0; i < get_physical_broadcast(); i++) {
2730                         if (!check_apicid_used(apic_id_map, i))
2731                                 break;
2732                 }
2733
2734                 if (i == get_physical_broadcast())
2735                         panic("Max apic_id exceeded!\n");
2736
2737                 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2738                         "trying %d\n", ioapic, apic_id, i);
2739
2740                 apic_id = i;
2741         }
2742
2743         tmp = apicid_to_cpu_present(apic_id);
2744         physids_or(apic_id_map, apic_id_map, tmp);
2745
2746         if (reg_00.bits.ID != apic_id) {
2747                 reg_00.bits.ID = apic_id;
2748
2749                 spin_lock_irqsave(&ioapic_lock, flags);
2750                 io_apic_write(ioapic, 0, reg_00.raw);
2751                 reg_00.raw = io_apic_read(ioapic, 0);
2752                 spin_unlock_irqrestore(&ioapic_lock, flags);
2753
2754                 /* Sanity check */
2755                 if (reg_00.bits.ID != apic_id) {
2756                         printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
2757                         return -1;
2758                 }
2759         }
2760
2761         apic_printk(APIC_VERBOSE, KERN_INFO
2762                         "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2763
2764         return apic_id;
2765 }
2766
2767
2768 int __init io_apic_get_version(int ioapic)
2769 {
2770         union IO_APIC_reg_01    reg_01;
2771         unsigned long flags;
2772
2773         spin_lock_irqsave(&ioapic_lock, flags);
2774         reg_01.raw = io_apic_read(ioapic, 1);
2775         spin_unlock_irqrestore(&ioapic_lock, flags);
2776
2777         return reg_01.bits.version;
2778 }
2779
2780
2781 int __init io_apic_get_redir_entries(int ioapic)
2782 {
2783         union IO_APIC_reg_01    reg_01;
2784         unsigned long flags;
2785
2786         spin_lock_irqsave(&ioapic_lock, flags);
2787         reg_01.raw = io_apic_read(ioapic, 1);
2788         spin_unlock_irqrestore(&ioapic_lock, flags);
2789
2790         return reg_01.bits.entries;
2791 }
2792
2793
2794 int io_apic_set_pci_routing(int ioapic, int pin, int irq, int edge_level, int active_high_low)
2795 {
2796         struct IO_APIC_route_entry entry;
2797
2798         if (!IO_APIC_IRQ(irq)) {
2799                 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2800                         ioapic);
2801                 return -EINVAL;
2802         }
2803
2804         /*
2805          * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2806          * Note that we mask (disable) IRQs now -- these get enabled when the
2807          * corresponding device driver registers for this IRQ.
2808          */
2809
2810         memset(&entry, 0, sizeof(entry));
2811
2812         entry.delivery_mode = INT_DELIVERY_MODE;
2813         entry.dest_mode = INT_DEST_MODE;
2814         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2815         entry.trigger = edge_level;
2816         entry.polarity = active_high_low;
2817         entry.mask  = 1;
2818
2819         /*
2820          * IRQs < 16 are already in the irq_2_pin[] map
2821          */
2822         if (irq >= 16)
2823                 add_pin_to_irq(irq, ioapic, pin);
2824
2825         entry.vector = assign_irq_vector(irq);
2826
2827         apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry "
2828                 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic,
2829                 mp_ioapics[ioapic].mp_apicid, pin, entry.vector, irq,
2830                 edge_level, active_high_low);
2831
2832         ioapic_register_intr(irq, entry.vector, edge_level);
2833
2834         if (!ioapic && (irq < 16))
2835                 disable_8259A_irq(irq);
2836
2837         ioapic_write_entry(ioapic, pin, entry);
2838
2839         return 0;
2840 }
2841
2842 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
2843 {
2844         int i;
2845
2846         if (skip_ioapic_setup)
2847                 return -1;
2848
2849         for (i = 0; i < mp_irq_entries; i++)
2850                 if (mp_irqs[i].mp_irqtype == mp_INT &&
2851                     mp_irqs[i].mp_srcbusirq == bus_irq)
2852                         break;
2853         if (i >= mp_irq_entries)
2854                 return -1;
2855
2856         *trigger = irq_trigger(i);
2857         *polarity = irq_polarity(i);
2858         return 0;
2859 }
2860
2861 #endif /* CONFIG_ACPI */
2862
2863 static int __init parse_disable_timer_pin_1(char *arg)
2864 {
2865         disable_timer_pin_1 = 1;
2866         return 0;
2867 }
2868 early_param("disable_timer_pin_1", parse_disable_timer_pin_1);
2869
2870 static int __init parse_enable_timer_pin_1(char *arg)
2871 {
2872         disable_timer_pin_1 = -1;
2873         return 0;
2874 }
2875 early_param("enable_timer_pin_1", parse_enable_timer_pin_1);
2876
2877 static int __init parse_noapic(char *arg)
2878 {
2879         /* disable IO-APIC */
2880         disable_ioapic_setup();
2881         return 0;
2882 }
2883 early_param("noapic", parse_noapic);
2884
2885 void __init ioapic_init_mappings(void)
2886 {
2887         unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
2888         int i;
2889
2890         for (i = 0; i < nr_ioapics; i++) {
2891                 if (smp_found_config) {
2892                         ioapic_phys = mp_ioapics[i].mp_apicaddr;
2893                         if (!ioapic_phys) {
2894                                 printk(KERN_ERR
2895                                        "WARNING: bogus zero IO-APIC "
2896                                        "address found in MPTABLE, "
2897                                        "disabling IO/APIC support!\n");
2898                                 smp_found_config = 0;
2899                                 skip_ioapic_setup = 1;
2900                                 goto fake_ioapic_page;
2901                         }
2902                 } else {
2903 fake_ioapic_page:
2904                         ioapic_phys = (unsigned long)
2905                                       alloc_bootmem_pages(PAGE_SIZE);
2906                         ioapic_phys = __pa(ioapic_phys);
2907                 }
2908                 set_fixmap_nocache(idx, ioapic_phys);
2909                 printk(KERN_DEBUG "mapped IOAPIC to %08lx (%08lx)\n",
2910                        __fix_to_virt(idx), ioapic_phys);
2911                 idx++;
2912         }
2913 }
2914