Merge branch 'x86/ptrace' into x86/tsc
[linux-2.6.git] / arch / x86 / kernel / cpu / intel.c
1 #include <linux/init.h>
2 #include <linux/kernel.h>
3
4 #include <linux/string.h>
5 #include <linux/bitops.h>
6 #include <linux/smp.h>
7 #include <linux/thread_info.h>
8 #include <linux/module.h>
9
10 #include <asm/processor.h>
11 #include <asm/pgtable.h>
12 #include <asm/msr.h>
13 #include <asm/uaccess.h>
14 #include <asm/ptrace.h>
15 #include <asm/ds.h>
16 #include <asm/bugs.h>
17
18 #ifdef CONFIG_X86_64
19 #include <asm/topology.h>
20 #include <asm/numa_64.h>
21 #endif
22
23 #include "cpu.h"
24
25 #ifdef CONFIG_X86_LOCAL_APIC
26 #include <asm/mpspec.h>
27 #include <asm/apic.h>
28 #include <mach_apic.h>
29 #endif
30
31 static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
32 {
33         if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
34                 (c->x86 == 0x6 && c->x86_model >= 0x0e))
35                 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
36
37 #ifdef CONFIG_X86_64
38         set_cpu_cap(c, X86_FEATURE_SYSENTER32);
39 #else
40         /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
41         if (c->x86 == 15 && c->x86_cache_alignment == 64)
42                 c->x86_cache_alignment = 128;
43 #endif
44
45         /*
46          * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
47          * with P/T states and does not stop in deep C-states
48          */
49         if (c->x86_power & (1 << 8)) {
50                 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
51                 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
52         }
53
54 }
55
56 #ifdef CONFIG_X86_32
57 /*
58  *      Early probe support logic for ppro memory erratum #50
59  *
60  *      This is called before we do cpu ident work
61  */
62
63 int __cpuinit ppro_with_ram_bug(void)
64 {
65         /* Uses data from early_cpu_detect now */
66         if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
67             boot_cpu_data.x86 == 6 &&
68             boot_cpu_data.x86_model == 1 &&
69             boot_cpu_data.x86_mask < 8) {
70                 printk(KERN_INFO "Pentium Pro with Errata#50 detected. Taking evasive action.\n");
71                 return 1;
72         }
73         return 0;
74 }
75
76 #ifdef CONFIG_X86_F00F_BUG
77 static void __cpuinit trap_init_f00f_bug(void)
78 {
79         __set_fixmap(FIX_F00F_IDT, __pa(&idt_table), PAGE_KERNEL_RO);
80
81         /*
82          * Update the IDT descriptor and reload the IDT so that
83          * it uses the read-only mapped virtual address.
84          */
85         idt_descr.address = fix_to_virt(FIX_F00F_IDT);
86         load_idt(&idt_descr);
87 }
88 #endif
89
90 static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
91 {
92         unsigned long lo, hi;
93
94 #ifdef CONFIG_X86_F00F_BUG
95         /*
96          * All current models of Pentium and Pentium with MMX technology CPUs
97          * have the F0 0F bug, which lets nonprivileged users lock up the system.
98          * Note that the workaround only should be initialized once...
99          */
100         c->f00f_bug = 0;
101         if (!paravirt_enabled() && c->x86 == 5) {
102                 static int f00f_workaround_enabled;
103
104                 c->f00f_bug = 1;
105                 if (!f00f_workaround_enabled) {
106                         trap_init_f00f_bug();
107                         printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n");
108                         f00f_workaround_enabled = 1;
109                 }
110         }
111 #endif
112
113         /*
114          * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until
115          * model 3 mask 3
116          */
117         if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633)
118                 clear_cpu_cap(c, X86_FEATURE_SEP);
119
120         /*
121          * P4 Xeon errata 037 workaround.
122          * Hardware prefetcher may cause stale data to be loaded into the cache.
123          */
124         if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
125                 rdmsr(MSR_IA32_MISC_ENABLE, lo, hi);
126                 if ((lo & (1<<9)) == 0) {
127                         printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n");
128                         printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n");
129                         lo |= (1<<9);   /* Disable hw prefetching */
130                         wrmsr (MSR_IA32_MISC_ENABLE, lo, hi);
131                 }
132         }
133
134         /*
135          * See if we have a good local APIC by checking for buggy Pentia,
136          * i.e. all B steppings and the C2 stepping of P54C when using their
137          * integrated APIC (see 11AP erratum in "Pentium Processor
138          * Specification Update").
139          */
140         if (cpu_has_apic && (c->x86<<8 | c->x86_model<<4) == 0x520 &&
141             (c->x86_mask < 0x6 || c->x86_mask == 0xb))
142                 set_cpu_cap(c, X86_FEATURE_11AP);
143
144
145 #ifdef CONFIG_X86_INTEL_USERCOPY
146         /*
147          * Set up the preferred alignment for movsl bulk memory moves
148          */
149         switch (c->x86) {
150         case 4:         /* 486: untested */
151                 break;
152         case 5:         /* Old Pentia: untested */
153                 break;
154         case 6:         /* PII/PIII only like movsl with 8-byte alignment */
155                 movsl_mask.mask = 7;
156                 break;
157         case 15:        /* P4 is OK down to 8-byte alignment */
158                 movsl_mask.mask = 7;
159                 break;
160         }
161 #endif
162
163 #ifdef CONFIG_X86_NUMAQ
164         numaq_tsc_disable();
165 #endif
166 }
167 #else
168 static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
169 {
170 }
171 #endif
172
173 static void __cpuinit srat_detect_node(void)
174 {
175 #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64)
176         unsigned node;
177         int cpu = smp_processor_id();
178         int apicid = hard_smp_processor_id();
179
180         /* Don't do the funky fallback heuristics the AMD version employs
181            for now. */
182         node = apicid_to_node[apicid];
183         if (node == NUMA_NO_NODE || !node_online(node))
184                 node = first_node(node_online_map);
185         numa_set_node(cpu, node);
186
187         printk(KERN_INFO "CPU %d/0x%x -> Node %d\n", cpu, apicid, node);
188 #endif
189 }
190
191 /*
192  * find out the number of processor cores on the die
193  */
194 static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
195 {
196         unsigned int eax, ebx, ecx, edx;
197
198         if (c->cpuid_level < 4)
199                 return 1;
200
201         /* Intel has a non-standard dependency on %ecx for this CPUID level. */
202         cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
203         if (eax & 0x1f)
204                 return ((eax >> 26) + 1);
205         else
206                 return 1;
207 }
208
209 static void __cpuinit detect_vmx_virtcap(struct cpuinfo_x86 *c)
210 {
211         /* Intel VMX MSR indicated features */
212 #define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW    0x00200000
213 #define X86_VMX_FEATURE_PROC_CTLS_VNMI          0x00400000
214 #define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS      0x80000000
215 #define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC    0x00000001
216 #define X86_VMX_FEATURE_PROC_CTLS2_EPT          0x00000002
217 #define X86_VMX_FEATURE_PROC_CTLS2_VPID         0x00000020
218
219         u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2;
220
221         clear_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
222         clear_cpu_cap(c, X86_FEATURE_VNMI);
223         clear_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
224         clear_cpu_cap(c, X86_FEATURE_EPT);
225         clear_cpu_cap(c, X86_FEATURE_VPID);
226
227         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high);
228         msr_ctl = vmx_msr_high | vmx_msr_low;
229         if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)
230                 set_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
231         if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI)
232                 set_cpu_cap(c, X86_FEATURE_VNMI);
233         if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) {
234                 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
235                       vmx_msr_low, vmx_msr_high);
236                 msr_ctl2 = vmx_msr_high | vmx_msr_low;
237                 if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) &&
238                     (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW))
239                         set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
240                 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT)
241                         set_cpu_cap(c, X86_FEATURE_EPT);
242                 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID)
243                         set_cpu_cap(c, X86_FEATURE_VPID);
244         }
245 }
246
247 static void __cpuinit init_intel(struct cpuinfo_x86 *c)
248 {
249         unsigned int l2 = 0;
250
251         early_init_intel(c);
252
253         intel_workarounds(c);
254
255         /*
256          * Detect the extended topology information if available. This
257          * will reinitialise the initial_apicid which will be used
258          * in init_intel_cacheinfo()
259          */
260         detect_extended_topology(c);
261
262         l2 = init_intel_cacheinfo(c);
263         if (c->cpuid_level > 9) {
264                 unsigned eax = cpuid_eax(10);
265                 /* Check for version and the number of counters */
266                 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
267                         set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
268         }
269
270         if (cpu_has_xmm2)
271                 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
272         if (cpu_has_ds) {
273                 unsigned int l1;
274                 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
275                 if (!(l1 & (1<<11)))
276                         set_cpu_cap(c, X86_FEATURE_BTS);
277                 if (!(l1 & (1<<12)))
278                         set_cpu_cap(c, X86_FEATURE_PEBS);
279                 ds_init_intel(c);
280         }
281
282 #ifdef CONFIG_X86_64
283         if (c->x86 == 15)
284                 c->x86_cache_alignment = c->x86_clflush_size * 2;
285         if (c->x86 == 6)
286                 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
287 #else
288         /*
289          * Names for the Pentium II/Celeron processors
290          * detectable only by also checking the cache size.
291          * Dixon is NOT a Celeron.
292          */
293         if (c->x86 == 6) {
294                 char *p = NULL;
295
296                 switch (c->x86_model) {
297                 case 5:
298                         if (c->x86_mask == 0) {
299                                 if (l2 == 0)
300                                         p = "Celeron (Covington)";
301                                 else if (l2 == 256)
302                                         p = "Mobile Pentium II (Dixon)";
303                         }
304                         break;
305
306                 case 6:
307                         if (l2 == 128)
308                                 p = "Celeron (Mendocino)";
309                         else if (c->x86_mask == 0 || c->x86_mask == 5)
310                                 p = "Celeron-A";
311                         break;
312
313                 case 8:
314                         if (l2 == 128)
315                                 p = "Celeron (Coppermine)";
316                         break;
317                 }
318
319                 if (p)
320                         strcpy(c->x86_model_id, p);
321         }
322
323         if (c->x86 == 15)
324                 set_cpu_cap(c, X86_FEATURE_P4);
325         if (c->x86 == 6)
326                 set_cpu_cap(c, X86_FEATURE_P3);
327 #endif
328
329         if (cpu_has_bts)
330                 ptrace_bts_init_intel(c);
331
332         if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {
333                 /*
334                  * let's use the legacy cpuid vector 0x1 and 0x4 for topology
335                  * detection.
336                  */
337                 c->x86_max_cores = intel_num_cpu_cores(c);
338 #ifdef CONFIG_X86_32
339                 detect_ht(c);
340 #endif
341         }
342
343         /* Work around errata */
344         srat_detect_node();
345
346         if (cpu_has(c, X86_FEATURE_VMX))
347                 detect_vmx_virtcap(c);
348 }
349
350 #ifdef CONFIG_X86_32
351 static unsigned int __cpuinit intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
352 {
353         /*
354          * Intel PIII Tualatin. This comes in two flavours.
355          * One has 256kb of cache, the other 512. We have no way
356          * to determine which, so we use a boottime override
357          * for the 512kb model, and assume 256 otherwise.
358          */
359         if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
360                 size = 256;
361         return size;
362 }
363 #endif
364
365 static struct cpu_dev intel_cpu_dev __cpuinitdata = {
366         .c_vendor       = "Intel",
367         .c_ident        = { "GenuineIntel" },
368 #ifdef CONFIG_X86_32
369         .c_models = {
370                 { .vendor = X86_VENDOR_INTEL, .family = 4, .model_names =
371                   {
372                           [0] = "486 DX-25/33",
373                           [1] = "486 DX-50",
374                           [2] = "486 SX",
375                           [3] = "486 DX/2",
376                           [4] = "486 SL",
377                           [5] = "486 SX/2",
378                           [7] = "486 DX/2-WB",
379                           [8] = "486 DX/4",
380                           [9] = "486 DX/4-WB"
381                   }
382                 },
383                 { .vendor = X86_VENDOR_INTEL, .family = 5, .model_names =
384                   {
385                           [0] = "Pentium 60/66 A-step",
386                           [1] = "Pentium 60/66",
387                           [2] = "Pentium 75 - 200",
388                           [3] = "OverDrive PODP5V83",
389                           [4] = "Pentium MMX",
390                           [7] = "Mobile Pentium 75 - 200",
391                           [8] = "Mobile Pentium MMX"
392                   }
393                 },
394                 { .vendor = X86_VENDOR_INTEL, .family = 6, .model_names =
395                   {
396                           [0] = "Pentium Pro A-step",
397                           [1] = "Pentium Pro",
398                           [3] = "Pentium II (Klamath)",
399                           [4] = "Pentium II (Deschutes)",
400                           [5] = "Pentium II (Deschutes)",
401                           [6] = "Mobile Pentium II",
402                           [7] = "Pentium III (Katmai)",
403                           [8] = "Pentium III (Coppermine)",
404                           [10] = "Pentium III (Cascades)",
405                           [11] = "Pentium III (Tualatin)",
406                   }
407                 },
408                 { .vendor = X86_VENDOR_INTEL, .family = 15, .model_names =
409                   {
410                           [0] = "Pentium 4 (Unknown)",
411                           [1] = "Pentium 4 (Willamette)",
412                           [2] = "Pentium 4 (Northwood)",
413                           [4] = "Pentium 4 (Foster)",
414                           [5] = "Pentium 4 (Foster)",
415                   }
416                 },
417         },
418         .c_size_cache   = intel_size_cache,
419 #endif
420         .c_early_init   = early_init_intel,
421         .c_init         = init_intel,
422         .c_x86_vendor   = X86_VENDOR_INTEL,
423 };
424
425 cpu_dev_register(intel_cpu_dev);
426