Merge branch 'x86-cleanups-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[linux-2.6.git] / arch / x86 / include / asm / hyperv.h
1 #ifndef _ASM_X86_KVM_HYPERV_H
2 #define _ASM_X86_KVM_HYPERV_H
3
4 #include <linux/types.h>
5
6 /*
7  * The below CPUID leaves are present if VersionAndFeatures.HypervisorPresent
8  * is set by CPUID(HvCpuIdFunctionVersionAndFeatures).
9  */
10 #define HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS   0x40000000
11 #define HYPERV_CPUID_INTERFACE                  0x40000001
12 #define HYPERV_CPUID_VERSION                    0x40000002
13 #define HYPERV_CPUID_FEATURES                   0x40000003
14 #define HYPERV_CPUID_ENLIGHTMENT_INFO           0x40000004
15 #define HYPERV_CPUID_IMPLEMENT_LIMITS           0x40000005
16
17 /*
18  * Feature identification. EAX indicates which features are available
19  * to the partition based upon the current partition privileges.
20  */
21
22 /* VP Runtime (HV_X64_MSR_VP_RUNTIME) available */
23 #define HV_X64_MSR_VP_RUNTIME_AVAILABLE         (1 << 0)
24 /* Partition Reference Counter (HV_X64_MSR_TIME_REF_COUNT) available*/
25 #define HV_X64_MSR_TIME_REF_COUNT_AVAILABLE     (1 << 1)
26 /*
27  * Basic SynIC MSRs (HV_X64_MSR_SCONTROL through HV_X64_MSR_EOM
28  * and HV_X64_MSR_SINT0 through HV_X64_MSR_SINT15) available
29  */
30 #define HV_X64_MSR_SYNIC_AVAILABLE              (1 << 2)
31 /*
32  * Synthetic Timer MSRs (HV_X64_MSR_STIMER0_CONFIG through
33  * HV_X64_MSR_STIMER3_COUNT) available
34  */
35 #define HV_X64_MSR_SYNTIMER_AVAILABLE           (1 << 3)
36 /*
37  * APIC access MSRs (HV_X64_MSR_EOI, HV_X64_MSR_ICR and HV_X64_MSR_TPR)
38  * are available
39  */
40 #define HV_X64_MSR_APIC_ACCESS_AVAILABLE        (1 << 4)
41 /* Hypercall MSRs (HV_X64_MSR_GUEST_OS_ID and HV_X64_MSR_HYPERCALL) available*/
42 #define HV_X64_MSR_HYPERCALL_AVAILABLE          (1 << 5)
43 /* Access virtual processor index MSR (HV_X64_MSR_VP_INDEX) available*/
44 #define HV_X64_MSR_VP_INDEX_AVAILABLE           (1 << 6)
45 /* Virtual system reset MSR (HV_X64_MSR_RESET) is available*/
46 #define HV_X64_MSR_RESET_AVAILABLE              (1 << 7)
47  /*
48   * Access statistics pages MSRs (HV_X64_MSR_STATS_PARTITION_RETAIL_PAGE,
49   * HV_X64_MSR_STATS_PARTITION_INTERNAL_PAGE, HV_X64_MSR_STATS_VP_RETAIL_PAGE,
50   * HV_X64_MSR_STATS_VP_INTERNAL_PAGE) available
51   */
52 #define HV_X64_MSR_STAT_PAGES_AVAILABLE         (1 << 8)
53
54 /*
55  * Feature identification: EBX indicates which flags were specified at
56  * partition creation. The format is the same as the partition creation
57  * flag structure defined in section Partition Creation Flags.
58  */
59 #define HV_X64_CREATE_PARTITIONS                (1 << 0)
60 #define HV_X64_ACCESS_PARTITION_ID              (1 << 1)
61 #define HV_X64_ACCESS_MEMORY_POOL               (1 << 2)
62 #define HV_X64_ADJUST_MESSAGE_BUFFERS           (1 << 3)
63 #define HV_X64_POST_MESSAGES                    (1 << 4)
64 #define HV_X64_SIGNAL_EVENTS                    (1 << 5)
65 #define HV_X64_CREATE_PORT                      (1 << 6)
66 #define HV_X64_CONNECT_PORT                     (1 << 7)
67 #define HV_X64_ACCESS_STATS                     (1 << 8)
68 #define HV_X64_DEBUGGING                        (1 << 11)
69 #define HV_X64_CPU_POWER_MANAGEMENT             (1 << 12)
70 #define HV_X64_CONFIGURE_PROFILER               (1 << 13)
71
72 /*
73  * Feature identification. EDX indicates which miscellaneous features
74  * are available to the partition.
75  */
76 /* The MWAIT instruction is available (per section MONITOR / MWAIT) */
77 #define HV_X64_MWAIT_AVAILABLE                          (1 << 0)
78 /* Guest debugging support is available */
79 #define HV_X64_GUEST_DEBUGGING_AVAILABLE                (1 << 1)
80 /* Performance Monitor support is available*/
81 #define HV_X64_PERF_MONITOR_AVAILABLE                   (1 << 2)
82 /* Support for physical CPU dynamic partitioning events is available*/
83 #define HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE       (1 << 3)
84 /*
85  * Support for passing hypercall input parameter block via XMM
86  * registers is available
87  */
88 #define HV_X64_HYPERCALL_PARAMS_XMM_AVAILABLE           (1 << 4)
89 /* Support for a virtual guest idle state is available */
90 #define HV_X64_GUEST_IDLE_STATE_AVAILABLE               (1 << 5)
91
92 /*
93  * Implementation recommendations. Indicates which behaviors the hypervisor
94  * recommends the OS implement for optimal performance.
95  */
96  /*
97   * Recommend using hypercall for address space switches rather
98   * than MOV to CR3 instruction
99   */
100 #define HV_X64_MWAIT_RECOMMENDED                (1 << 0)
101 /* Recommend using hypercall for local TLB flushes rather
102  * than INVLPG or MOV to CR3 instructions */
103 #define HV_X64_LOCAL_TLB_FLUSH_RECOMMENDED      (1 << 1)
104 /*
105  * Recommend using hypercall for remote TLB flushes rather
106  * than inter-processor interrupts
107  */
108 #define HV_X64_REMOTE_TLB_FLUSH_RECOMMENDED     (1 << 2)
109 /*
110  * Recommend using MSRs for accessing APIC registers
111  * EOI, ICR and TPR rather than their memory-mapped counterparts
112  */
113 #define HV_X64_APIC_ACCESS_RECOMMENDED          (1 << 3)
114 /* Recommend using the hypervisor-provided MSR to initiate a system RESET */
115 #define HV_X64_SYSTEM_RESET_RECOMMENDED         (1 << 4)
116 /*
117  * Recommend using relaxed timing for this partition. If used,
118  * the VM should disable any watchdog timeouts that rely on the
119  * timely delivery of external interrupts
120  */
121 #define HV_X64_RELAXED_TIMING_RECOMMENDED       (1 << 5)
122
123 /* MSR used to identify the guest OS. */
124 #define HV_X64_MSR_GUEST_OS_ID                  0x40000000
125
126 /* MSR used to setup pages used to communicate with the hypervisor. */
127 #define HV_X64_MSR_HYPERCALL                    0x40000001
128
129 /* MSR used to provide vcpu index */
130 #define HV_X64_MSR_VP_INDEX                     0x40000002
131
132 /* Define the virtual APIC registers */
133 #define HV_X64_MSR_EOI                          0x40000070
134 #define HV_X64_MSR_ICR                          0x40000071
135 #define HV_X64_MSR_TPR                          0x40000072
136 #define HV_X64_MSR_APIC_ASSIST_PAGE             0x40000073
137
138 /* Define synthetic interrupt controller model specific registers. */
139 #define HV_X64_MSR_SCONTROL                     0x40000080
140 #define HV_X64_MSR_SVERSION                     0x40000081
141 #define HV_X64_MSR_SIEFP                        0x40000082
142 #define HV_X64_MSR_SIMP                         0x40000083
143 #define HV_X64_MSR_EOM                          0x40000084
144 #define HV_X64_MSR_SINT0                        0x40000090
145 #define HV_X64_MSR_SINT1                        0x40000091
146 #define HV_X64_MSR_SINT2                        0x40000092
147 #define HV_X64_MSR_SINT3                        0x40000093
148 #define HV_X64_MSR_SINT4                        0x40000094
149 #define HV_X64_MSR_SINT5                        0x40000095
150 #define HV_X64_MSR_SINT6                        0x40000096
151 #define HV_X64_MSR_SINT7                        0x40000097
152 #define HV_X64_MSR_SINT8                        0x40000098
153 #define HV_X64_MSR_SINT9                        0x40000099
154 #define HV_X64_MSR_SINT10                       0x4000009A
155 #define HV_X64_MSR_SINT11                       0x4000009B
156 #define HV_X64_MSR_SINT12                       0x4000009C
157 #define HV_X64_MSR_SINT13                       0x4000009D
158 #define HV_X64_MSR_SINT14                       0x4000009E
159 #define HV_X64_MSR_SINT15                       0x4000009F
160
161
162 #define HV_X64_MSR_HYPERCALL_ENABLE             0x00000001
163 #define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT 12
164 #define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_MASK  \
165                 (~((1ull << HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT) - 1))
166
167 /* Declare the various hypercall operations. */
168 #define HV_X64_HV_NOTIFY_LONG_SPIN_WAIT         0x0008
169
170 #define HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE              0x00000001
171 #define HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT       12
172 #define HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_MASK        \
173                 (~((1ull << HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT) - 1))
174
175 #define HV_PROCESSOR_POWER_STATE_C0             0
176 #define HV_PROCESSOR_POWER_STATE_C1             1
177 #define HV_PROCESSOR_POWER_STATE_C2             2
178 #define HV_PROCESSOR_POWER_STATE_C3             3
179
180 /* hypercall status code */
181 #define HV_STATUS_SUCCESS                       0
182 #define HV_STATUS_INVALID_HYPERCALL_CODE        2
183 #define HV_STATUS_INVALID_HYPERCALL_INPUT       3
184 #define HV_STATUS_INVALID_ALIGNMENT             4
185
186 #endif