[PATCH] Kprobes: prevent possible race conditions sparc64 changes
[linux-2.6.git] / arch / sparc64 / mm / init.c
1 /*  $Id: init.c,v 1.209 2002/02/09 19:49:31 davem Exp $
2  *  arch/sparc64/mm/init.c
3  *
4  *  Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
5  *  Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
6  */
7  
8 #include <linux/config.h>
9 #include <linux/kernel.h>
10 #include <linux/sched.h>
11 #include <linux/string.h>
12 #include <linux/init.h>
13 #include <linux/bootmem.h>
14 #include <linux/mm.h>
15 #include <linux/hugetlb.h>
16 #include <linux/slab.h>
17 #include <linux/initrd.h>
18 #include <linux/swap.h>
19 #include <linux/pagemap.h>
20 #include <linux/fs.h>
21 #include <linux/seq_file.h>
22 #include <linux/kprobes.h>
23
24 #include <asm/head.h>
25 #include <asm/system.h>
26 #include <asm/page.h>
27 #include <asm/pgalloc.h>
28 #include <asm/pgtable.h>
29 #include <asm/oplib.h>
30 #include <asm/iommu.h>
31 #include <asm/io.h>
32 #include <asm/uaccess.h>
33 #include <asm/mmu_context.h>
34 #include <asm/tlbflush.h>
35 #include <asm/dma.h>
36 #include <asm/starfire.h>
37 #include <asm/tlb.h>
38 #include <asm/spitfire.h>
39 #include <asm/sections.h>
40
41 extern void device_scan(void);
42
43 struct sparc_phys_banks sp_banks[SPARC_PHYS_BANKS];
44
45 unsigned long *sparc64_valid_addr_bitmap;
46
47 /* Ugly, but necessary... -DaveM */
48 unsigned long phys_base;
49 unsigned long kern_base;
50 unsigned long kern_size;
51 unsigned long pfn_base;
52
53 /* This is even uglier. We have a problem where the kernel may not be
54  * located at phys_base. However, initial __alloc_bootmem() calls need to
55  * be adjusted to be within the 4-8Megs that the kernel is mapped to, else
56  * those page mappings wont work. Things are ok after inherit_prom_mappings
57  * is called though. Dave says he'll clean this up some other time.
58  * -- BenC
59  */
60 static unsigned long bootmap_base;
61
62 /* get_new_mmu_context() uses "cache + 1".  */
63 DEFINE_SPINLOCK(ctx_alloc_lock);
64 unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
65 #define CTX_BMAP_SLOTS (1UL << (CTX_NR_BITS - 6))
66 unsigned long mmu_context_bmap[CTX_BMAP_SLOTS];
67
68 /* References to special section boundaries */
69 extern char  _start[], _end[];
70
71 /* Initial ramdisk setup */
72 extern unsigned long sparc_ramdisk_image64;
73 extern unsigned int sparc_ramdisk_image;
74 extern unsigned int sparc_ramdisk_size;
75
76 struct page *mem_map_zero;
77
78 int bigkernel = 0;
79
80 /* XXX Tune this... */
81 #define PGT_CACHE_LOW   25
82 #define PGT_CACHE_HIGH  50
83
84 void check_pgt_cache(void)
85 {
86         preempt_disable();
87         if (pgtable_cache_size > PGT_CACHE_HIGH) {
88                 do {
89                         if (pgd_quicklist)
90                                 free_pgd_slow(get_pgd_fast());
91                         if (pte_quicklist[0])
92                                 free_pte_slow(pte_alloc_one_fast(NULL, 0));
93                         if (pte_quicklist[1])
94                                 free_pte_slow(pte_alloc_one_fast(NULL, 1 << (PAGE_SHIFT + 10)));
95                 } while (pgtable_cache_size > PGT_CACHE_LOW);
96         }
97         preempt_enable();
98 }
99
100 #ifdef CONFIG_DEBUG_DCFLUSH
101 atomic_t dcpage_flushes = ATOMIC_INIT(0);
102 #ifdef CONFIG_SMP
103 atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
104 #endif
105 #endif
106
107 __inline__ void flush_dcache_page_impl(struct page *page)
108 {
109 #ifdef CONFIG_DEBUG_DCFLUSH
110         atomic_inc(&dcpage_flushes);
111 #endif
112
113 #ifdef DCACHE_ALIASING_POSSIBLE
114         __flush_dcache_page(page_address(page),
115                             ((tlb_type == spitfire) &&
116                              page_mapping(page) != NULL));
117 #else
118         if (page_mapping(page) != NULL &&
119             tlb_type == spitfire)
120                 __flush_icache_page(__pa(page_address(page)));
121 #endif
122 }
123
124 #define PG_dcache_dirty         PG_arch_1
125 #define PG_dcache_cpu_shift     24
126 #define PG_dcache_cpu_mask      (256 - 1)
127
128 #if NR_CPUS > 256
129 #error D-cache dirty tracking and thread_info->cpu need fixing for > 256 cpus
130 #endif
131
132 #define dcache_dirty_cpu(page) \
133         (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
134
135 static __inline__ void set_dcache_dirty(struct page *page, int this_cpu)
136 {
137         unsigned long mask = this_cpu;
138         unsigned long non_cpu_bits;
139
140         non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
141         mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
142
143         __asm__ __volatile__("1:\n\t"
144                              "ldx       [%2], %%g7\n\t"
145                              "and       %%g7, %1, %%g1\n\t"
146                              "or        %%g1, %0, %%g1\n\t"
147                              "casx      [%2], %%g7, %%g1\n\t"
148                              "cmp       %%g7, %%g1\n\t"
149                              "membar    #StoreLoad | #StoreStore\n\t"
150                              "bne,pn    %%xcc, 1b\n\t"
151                              " nop"
152                              : /* no outputs */
153                              : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
154                              : "g1", "g7");
155 }
156
157 static __inline__ void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
158 {
159         unsigned long mask = (1UL << PG_dcache_dirty);
160
161         __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
162                              "1:\n\t"
163                              "ldx       [%2], %%g7\n\t"
164                              "srlx      %%g7, %4, %%g1\n\t"
165                              "and       %%g1, %3, %%g1\n\t"
166                              "cmp       %%g1, %0\n\t"
167                              "bne,pn    %%icc, 2f\n\t"
168                              " andn     %%g7, %1, %%g1\n\t"
169                              "casx      [%2], %%g7, %%g1\n\t"
170                              "cmp       %%g7, %%g1\n\t"
171                              "membar    #StoreLoad | #StoreStore\n\t"
172                              "bne,pn    %%xcc, 1b\n\t"
173                              " nop\n"
174                              "2:"
175                              : /* no outputs */
176                              : "r" (cpu), "r" (mask), "r" (&page->flags),
177                                "i" (PG_dcache_cpu_mask),
178                                "i" (PG_dcache_cpu_shift)
179                              : "g1", "g7");
180 }
181
182 extern void __update_mmu_cache(unsigned long mmu_context_hw, unsigned long address, pte_t pte, int code);
183
184 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
185 {
186         struct page *page;
187         unsigned long pfn;
188         unsigned long pg_flags;
189
190         pfn = pte_pfn(pte);
191         if (pfn_valid(pfn) &&
192             (page = pfn_to_page(pfn), page_mapping(page)) &&
193             ((pg_flags = page->flags) & (1UL << PG_dcache_dirty))) {
194                 int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
195                            PG_dcache_cpu_mask);
196                 int this_cpu = get_cpu();
197
198                 /* This is just to optimize away some function calls
199                  * in the SMP case.
200                  */
201                 if (cpu == this_cpu)
202                         flush_dcache_page_impl(page);
203                 else
204                         smp_flush_dcache_page_impl(page, cpu);
205
206                 clear_dcache_dirty_cpu(page, cpu);
207
208                 put_cpu();
209         }
210
211         if (get_thread_fault_code())
212                 __update_mmu_cache(CTX_NRBITS(vma->vm_mm->context),
213                                    address, pte, get_thread_fault_code());
214 }
215
216 void flush_dcache_page(struct page *page)
217 {
218         struct address_space *mapping;
219         int this_cpu;
220
221         /* Do not bother with the expensive D-cache flush if it
222          * is merely the zero page.  The 'bigcore' testcase in GDB
223          * causes this case to run millions of times.
224          */
225         if (page == ZERO_PAGE(0))
226                 return;
227
228         this_cpu = get_cpu();
229
230         mapping = page_mapping(page);
231         if (mapping && !mapping_mapped(mapping)) {
232                 int dirty = test_bit(PG_dcache_dirty, &page->flags);
233                 if (dirty) {
234                         int dirty_cpu = dcache_dirty_cpu(page);
235
236                         if (dirty_cpu == this_cpu)
237                                 goto out;
238                         smp_flush_dcache_page_impl(page, dirty_cpu);
239                 }
240                 set_dcache_dirty(page, this_cpu);
241         } else {
242                 /* We could delay the flush for the !page_mapping
243                  * case too.  But that case is for exec env/arg
244                  * pages and those are %99 certainly going to get
245                  * faulted into the tlb (and thus flushed) anyways.
246                  */
247                 flush_dcache_page_impl(page);
248         }
249
250 out:
251         put_cpu();
252 }
253
254 void __kprobes flush_icache_range(unsigned long start, unsigned long end)
255 {
256         /* Cheetah has coherent I-cache. */
257         if (tlb_type == spitfire) {
258                 unsigned long kaddr;
259
260                 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE)
261                         __flush_icache_page(__get_phys(kaddr));
262         }
263 }
264
265 unsigned long page_to_pfn(struct page *page)
266 {
267         return (unsigned long) ((page - mem_map) + pfn_base);
268 }
269
270 struct page *pfn_to_page(unsigned long pfn)
271 {
272         return (mem_map + (pfn - pfn_base));
273 }
274
275 void show_mem(void)
276 {
277         printk("Mem-info:\n");
278         show_free_areas();
279         printk("Free swap:       %6ldkB\n",
280                nr_swap_pages << (PAGE_SHIFT-10));
281         printk("%ld pages of RAM\n", num_physpages);
282         printk("%d free pages\n", nr_free_pages());
283         printk("%d pages in page table cache\n",pgtable_cache_size);
284 }
285
286 void mmu_info(struct seq_file *m)
287 {
288         if (tlb_type == cheetah)
289                 seq_printf(m, "MMU Type\t: Cheetah\n");
290         else if (tlb_type == cheetah_plus)
291                 seq_printf(m, "MMU Type\t: Cheetah+\n");
292         else if (tlb_type == spitfire)
293                 seq_printf(m, "MMU Type\t: Spitfire\n");
294         else
295                 seq_printf(m, "MMU Type\t: ???\n");
296
297 #ifdef CONFIG_DEBUG_DCFLUSH
298         seq_printf(m, "DCPageFlushes\t: %d\n",
299                    atomic_read(&dcpage_flushes));
300 #ifdef CONFIG_SMP
301         seq_printf(m, "DCPageFlushesXC\t: %d\n",
302                    atomic_read(&dcpage_flushes_xcall));
303 #endif /* CONFIG_SMP */
304 #endif /* CONFIG_DEBUG_DCFLUSH */
305 }
306
307 struct linux_prom_translation {
308         unsigned long virt;
309         unsigned long size;
310         unsigned long data;
311 };
312
313 extern unsigned long prom_boot_page;
314 extern void prom_remap(unsigned long physpage, unsigned long virtpage, int mmu_ihandle);
315 extern int prom_get_mmu_ihandle(void);
316 extern void register_prom_callbacks(void);
317
318 /* Exported for SMP bootup purposes. */
319 unsigned long kern_locked_tte_data;
320
321 void __init early_pgtable_allocfail(char *type)
322 {
323         prom_printf("inherit_prom_mappings: Cannot alloc kernel %s.\n", type);
324         prom_halt();
325 }
326
327 #define BASE_PAGE_SIZE 8192
328 static pmd_t *prompmd;
329
330 /*
331  * Translate PROM's mapping we capture at boot time into physical address.
332  * The second parameter is only set from prom_callback() invocations.
333  */
334 unsigned long prom_virt_to_phys(unsigned long promva, int *error)
335 {
336         pmd_t *pmdp = prompmd + ((promva >> 23) & 0x7ff);
337         pte_t *ptep;
338         unsigned long base;
339
340         if (pmd_none(*pmdp)) {
341                 if (error)
342                         *error = 1;
343                 return(0);
344         }
345         ptep = (pte_t *)__pmd_page(*pmdp) + ((promva >> 13) & 0x3ff);
346         if (!pte_present(*ptep)) {
347                 if (error)
348                         *error = 1;
349                 return(0);
350         }
351         if (error) {
352                 *error = 0;
353                 return(pte_val(*ptep));
354         }
355         base = pte_val(*ptep) & _PAGE_PADDR;
356         return(base + (promva & (BASE_PAGE_SIZE - 1)));
357 }
358
359 static void inherit_prom_mappings(void)
360 {
361         struct linux_prom_translation *trans;
362         unsigned long phys_page, tte_vaddr, tte_data;
363         void (*remap_func)(unsigned long, unsigned long, int);
364         pmd_t *pmdp;
365         pte_t *ptep;
366         int node, n, i, tsz;
367         extern unsigned int obp_iaddr_patch[2], obp_daddr_patch[2];
368
369         node = prom_finddevice("/virtual-memory");
370         n = prom_getproplen(node, "translations");
371         if (n == 0 || n == -1) {
372                 prom_printf("Couldn't get translation property\n");
373                 prom_halt();
374         }
375         n += 5 * sizeof(struct linux_prom_translation);
376         for (tsz = 1; tsz < n; tsz <<= 1)
377                 /* empty */;
378         trans = __alloc_bootmem(tsz, SMP_CACHE_BYTES, bootmap_base);
379         if (trans == NULL) {
380                 prom_printf("inherit_prom_mappings: Cannot alloc translations.\n");
381                 prom_halt();
382         }
383         memset(trans, 0, tsz);
384
385         if ((n = prom_getproperty(node, "translations", (char *)trans, tsz)) == -1) {
386                 prom_printf("Couldn't get translation property\n");
387                 prom_halt();
388         }
389         n = n / sizeof(*trans);
390
391         /*
392          * The obp translations are saved based on 8k pagesize, since obp can
393          * use a mixture of pagesizes. Misses to the 0xf0000000 - 0x100000000,
394          * ie obp range, are handled in entry.S and do not use the vpte scheme
395          * (see rant in inherit_locked_prom_mappings()).
396          */
397 #define OBP_PMD_SIZE 2048
398         prompmd = __alloc_bootmem(OBP_PMD_SIZE, OBP_PMD_SIZE, bootmap_base);
399         if (prompmd == NULL)
400                 early_pgtable_allocfail("pmd");
401         memset(prompmd, 0, OBP_PMD_SIZE);
402         for (i = 0; i < n; i++) {
403                 unsigned long vaddr;
404
405                 if (trans[i].virt >= LOW_OBP_ADDRESS && trans[i].virt < HI_OBP_ADDRESS) {
406                         for (vaddr = trans[i].virt;
407                              ((vaddr < trans[i].virt + trans[i].size) && 
408                              (vaddr < HI_OBP_ADDRESS));
409                              vaddr += BASE_PAGE_SIZE) {
410                                 unsigned long val;
411
412                                 pmdp = prompmd + ((vaddr >> 23) & 0x7ff);
413                                 if (pmd_none(*pmdp)) {
414                                         ptep = __alloc_bootmem(BASE_PAGE_SIZE,
415                                                                BASE_PAGE_SIZE,
416                                                                bootmap_base);
417                                         if (ptep == NULL)
418                                                 early_pgtable_allocfail("pte");
419                                         memset(ptep, 0, BASE_PAGE_SIZE);
420                                         pmd_set(pmdp, ptep);
421                                 }
422                                 ptep = (pte_t *)__pmd_page(*pmdp) +
423                                                 ((vaddr >> 13) & 0x3ff);
424
425                                 val = trans[i].data;
426
427                                 /* Clear diag TTE bits. */
428                                 if (tlb_type == spitfire)
429                                         val &= ~0x0003fe0000000000UL;
430
431                                 set_pte_at(&init_mm, vaddr,
432                                            ptep, __pte(val | _PAGE_MODIFIED));
433                                 trans[i].data += BASE_PAGE_SIZE;
434                         }
435                 }
436         }
437         phys_page = __pa(prompmd);
438         obp_iaddr_patch[0] |= (phys_page >> 10);
439         obp_iaddr_patch[1] |= (phys_page & 0x3ff);
440         flushi((long)&obp_iaddr_patch[0]);
441         obp_daddr_patch[0] |= (phys_page >> 10);
442         obp_daddr_patch[1] |= (phys_page & 0x3ff);
443         flushi((long)&obp_daddr_patch[0]);
444
445         /* Now fixup OBP's idea about where we really are mapped. */
446         prom_printf("Remapping the kernel... ");
447
448         /* Spitfire Errata #32 workaround */
449         /* NOTE: Using plain zero for the context value is
450          *       correct here, we are not using the Linux trap
451          *       tables yet so we should not use the special
452          *       UltraSPARC-III+ page size encodings yet.
453          */
454         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
455                              "flush     %%g6"
456                              : /* No outputs */
457                              : "r" (0), "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
458
459         switch (tlb_type) {
460         default:
461         case spitfire:
462                 phys_page = spitfire_get_dtlb_data(sparc64_highest_locked_tlbent());
463                 break;
464
465         case cheetah:
466         case cheetah_plus:
467                 phys_page = cheetah_get_litlb_data(sparc64_highest_locked_tlbent());
468                 break;
469         };
470
471         phys_page &= _PAGE_PADDR;
472         phys_page += ((unsigned long)&prom_boot_page -
473                       (unsigned long)KERNBASE);
474
475         if (tlb_type == spitfire) {
476                 /* Lock this into i/d tlb entry 59 */
477                 __asm__ __volatile__(
478                         "stxa   %%g0, [%2] %3\n\t"
479                         "stxa   %0, [%1] %4\n\t"
480                         "membar #Sync\n\t"
481                         "flush  %%g6\n\t"
482                         "stxa   %%g0, [%2] %5\n\t"
483                         "stxa   %0, [%1] %6\n\t"
484                         "membar #Sync\n\t"
485                         "flush  %%g6"
486                         : : "r" (phys_page | _PAGE_VALID | _PAGE_SZ8K | _PAGE_CP |
487                                  _PAGE_CV | _PAGE_P | _PAGE_L | _PAGE_W),
488                         "r" (59 << 3), "r" (TLB_TAG_ACCESS),
489                         "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS),
490                         "i" (ASI_IMMU), "i" (ASI_ITLB_DATA_ACCESS)
491                         : "memory");
492         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
493                 /* Lock this into i/d tlb-0 entry 11 */
494                 __asm__ __volatile__(
495                         "stxa   %%g0, [%2] %3\n\t"
496                         "stxa   %0, [%1] %4\n\t"
497                         "membar #Sync\n\t"
498                         "flush  %%g6\n\t"
499                         "stxa   %%g0, [%2] %5\n\t"
500                         "stxa   %0, [%1] %6\n\t"
501                         "membar #Sync\n\t"
502                         "flush  %%g6"
503                         : : "r" (phys_page | _PAGE_VALID | _PAGE_SZ8K | _PAGE_CP |
504                                  _PAGE_CV | _PAGE_P | _PAGE_L | _PAGE_W),
505                         "r" ((0 << 16) | (11 << 3)), "r" (TLB_TAG_ACCESS),
506                         "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS),
507                         "i" (ASI_IMMU), "i" (ASI_ITLB_DATA_ACCESS)
508                         : "memory");
509         } else {
510                 /* Implement me :-) */
511                 BUG();
512         }
513
514         tte_vaddr = (unsigned long) KERNBASE;
515
516         /* Spitfire Errata #32 workaround */
517         /* NOTE: Using plain zero for the context value is
518          *       correct here, we are not using the Linux trap
519          *       tables yet so we should not use the special
520          *       UltraSPARC-III+ page size encodings yet.
521          */
522         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
523                              "flush     %%g6"
524                              : /* No outputs */
525                              : "r" (0),
526                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
527
528         if (tlb_type == spitfire)
529                 tte_data = spitfire_get_dtlb_data(sparc64_highest_locked_tlbent());
530         else
531                 tte_data = cheetah_get_ldtlb_data(sparc64_highest_locked_tlbent());
532
533         kern_locked_tte_data = tte_data;
534
535         remap_func = (void *)  ((unsigned long) &prom_remap -
536                                 (unsigned long) &prom_boot_page);
537
538
539         /* Spitfire Errata #32 workaround */
540         /* NOTE: Using plain zero for the context value is
541          *       correct here, we are not using the Linux trap
542          *       tables yet so we should not use the special
543          *       UltraSPARC-III+ page size encodings yet.
544          */
545         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
546                              "flush     %%g6"
547                              : /* No outputs */
548                              : "r" (0),
549                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
550
551         remap_func((tlb_type == spitfire ?
552                     (spitfire_get_dtlb_data(sparc64_highest_locked_tlbent()) & _PAGE_PADDR) :
553                     (cheetah_get_litlb_data(sparc64_highest_locked_tlbent()) & _PAGE_PADDR)),
554                    (unsigned long) KERNBASE,
555                    prom_get_mmu_ihandle());
556
557         if (bigkernel)
558                 remap_func(((tte_data + 0x400000) & _PAGE_PADDR),
559                         (unsigned long) KERNBASE + 0x400000, prom_get_mmu_ihandle());
560
561         /* Flush out that temporary mapping. */
562         spitfire_flush_dtlb_nucleus_page(0x0);
563         spitfire_flush_itlb_nucleus_page(0x0);
564
565         /* Now lock us back into the TLBs via OBP. */
566         prom_dtlb_load(sparc64_highest_locked_tlbent(), tte_data, tte_vaddr);
567         prom_itlb_load(sparc64_highest_locked_tlbent(), tte_data, tte_vaddr);
568         if (bigkernel) {
569                 prom_dtlb_load(sparc64_highest_locked_tlbent()-1, tte_data + 0x400000, 
570                                                                 tte_vaddr + 0x400000);
571                 prom_itlb_load(sparc64_highest_locked_tlbent()-1, tte_data + 0x400000, 
572                                                                 tte_vaddr + 0x400000);
573         }
574
575         /* Re-read translations property. */
576         if ((n = prom_getproperty(node, "translations", (char *)trans, tsz)) == -1) {
577                 prom_printf("Couldn't get translation property\n");
578                 prom_halt();
579         }
580         n = n / sizeof(*trans);
581
582         for (i = 0; i < n; i++) {
583                 unsigned long vaddr = trans[i].virt;
584                 unsigned long size = trans[i].size;
585
586                 if (vaddr < 0xf0000000UL) {
587                         unsigned long avoid_start = (unsigned long) KERNBASE;
588                         unsigned long avoid_end = avoid_start + (4 * 1024 * 1024);
589
590                         if (bigkernel)
591                                 avoid_end += (4 * 1024 * 1024);
592                         if (vaddr < avoid_start) {
593                                 unsigned long top = vaddr + size;
594
595                                 if (top > avoid_start)
596                                         top = avoid_start;
597                                 prom_unmap(top - vaddr, vaddr);
598                         }
599                         if ((vaddr + size) > avoid_end) {
600                                 unsigned long bottom = vaddr;
601
602                                 if (bottom < avoid_end)
603                                         bottom = avoid_end;
604                                 prom_unmap((vaddr + size) - bottom, bottom);
605                         }
606                 }
607         }
608
609         prom_printf("done.\n");
610
611         register_prom_callbacks();
612 }
613
614 /* The OBP specifications for sun4u mark 0xfffffffc00000000 and
615  * upwards as reserved for use by the firmware (I wonder if this
616  * will be the same on Cheetah...).  We use this virtual address
617  * range for the VPTE table mappings of the nucleus so we need
618  * to zap them when we enter the PROM.  -DaveM
619  */
620 static void __flush_nucleus_vptes(void)
621 {
622         unsigned long prom_reserved_base = 0xfffffffc00000000UL;
623         int i;
624
625         /* Only DTLB must be checked for VPTE entries. */
626         if (tlb_type == spitfire) {
627                 for (i = 0; i < 63; i++) {
628                         unsigned long tag;
629
630                         /* Spitfire Errata #32 workaround */
631                         /* NOTE: Always runs on spitfire, so no cheetah+
632                          *       page size encodings.
633                          */
634                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
635                                              "flush     %%g6"
636                                              : /* No outputs */
637                                              : "r" (0),
638                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
639
640                         tag = spitfire_get_dtlb_tag(i);
641                         if (((tag & ~(PAGE_MASK)) == 0) &&
642                             ((tag &  (PAGE_MASK)) >= prom_reserved_base)) {
643                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
644                                                      "membar #Sync"
645                                                      : /* no outputs */
646                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
647                                 spitfire_put_dtlb_data(i, 0x0UL);
648                         }
649                 }
650         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
651                 for (i = 0; i < 512; i++) {
652                         unsigned long tag = cheetah_get_dtlb_tag(i, 2);
653
654                         if ((tag & ~PAGE_MASK) == 0 &&
655                             (tag & PAGE_MASK) >= prom_reserved_base) {
656                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
657                                                      "membar #Sync"
658                                                      : /* no outputs */
659                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
660                                 cheetah_put_dtlb_data(i, 0x0UL, 2);
661                         }
662
663                         if (tlb_type != cheetah_plus)
664                                 continue;
665
666                         tag = cheetah_get_dtlb_tag(i, 3);
667
668                         if ((tag & ~PAGE_MASK) == 0 &&
669                             (tag & PAGE_MASK) >= prom_reserved_base) {
670                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
671                                                      "membar #Sync"
672                                                      : /* no outputs */
673                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
674                                 cheetah_put_dtlb_data(i, 0x0UL, 3);
675                         }
676                 }
677         } else {
678                 /* Implement me :-) */
679                 BUG();
680         }
681 }
682
683 static int prom_ditlb_set;
684 struct prom_tlb_entry {
685         int             tlb_ent;
686         unsigned long   tlb_tag;
687         unsigned long   tlb_data;
688 };
689 struct prom_tlb_entry prom_itlb[16], prom_dtlb[16];
690
691 void prom_world(int enter)
692 {
693         unsigned long pstate;
694         int i;
695
696         if (!enter)
697                 set_fs((mm_segment_t) { get_thread_current_ds() });
698
699         if (!prom_ditlb_set)
700                 return;
701
702         /* Make sure the following runs atomically. */
703         __asm__ __volatile__("flushw\n\t"
704                              "rdpr      %%pstate, %0\n\t"
705                              "wrpr      %0, %1, %%pstate"
706                              : "=r" (pstate)
707                              : "i" (PSTATE_IE));
708
709         if (enter) {
710                 /* Kick out nucleus VPTEs. */
711                 __flush_nucleus_vptes();
712
713                 /* Install PROM world. */
714                 for (i = 0; i < 16; i++) {
715                         if (prom_dtlb[i].tlb_ent != -1) {
716                                 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
717                                                      "membar #Sync"
718                                         : : "r" (prom_dtlb[i].tlb_tag), "r" (TLB_TAG_ACCESS),
719                                         "i" (ASI_DMMU));
720                                 if (tlb_type == spitfire)
721                                         spitfire_put_dtlb_data(prom_dtlb[i].tlb_ent,
722                                                                prom_dtlb[i].tlb_data);
723                                 else if (tlb_type == cheetah || tlb_type == cheetah_plus)
724                                         cheetah_put_ldtlb_data(prom_dtlb[i].tlb_ent,
725                                                                prom_dtlb[i].tlb_data);
726                         }
727                         if (prom_itlb[i].tlb_ent != -1) {
728                                 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
729                                                      "membar #Sync"
730                                                      : : "r" (prom_itlb[i].tlb_tag),
731                                                      "r" (TLB_TAG_ACCESS),
732                                                      "i" (ASI_IMMU));
733                                 if (tlb_type == spitfire)
734                                         spitfire_put_itlb_data(prom_itlb[i].tlb_ent,
735                                                                prom_itlb[i].tlb_data);
736                                 else if (tlb_type == cheetah || tlb_type == cheetah_plus)
737                                         cheetah_put_litlb_data(prom_itlb[i].tlb_ent,
738                                                                prom_itlb[i].tlb_data);
739                         }
740                 }
741         } else {
742                 for (i = 0; i < 16; i++) {
743                         if (prom_dtlb[i].tlb_ent != -1) {
744                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
745                                                      "membar #Sync"
746                                         : : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
747                                 if (tlb_type == spitfire)
748                                         spitfire_put_dtlb_data(prom_dtlb[i].tlb_ent, 0x0UL);
749                                 else
750                                         cheetah_put_ldtlb_data(prom_dtlb[i].tlb_ent, 0x0UL);
751                         }
752                         if (prom_itlb[i].tlb_ent != -1) {
753                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
754                                                      "membar #Sync"
755                                                      : : "r" (TLB_TAG_ACCESS),
756                                                      "i" (ASI_IMMU));
757                                 if (tlb_type == spitfire)
758                                         spitfire_put_itlb_data(prom_itlb[i].tlb_ent, 0x0UL);
759                                 else
760                                         cheetah_put_litlb_data(prom_itlb[i].tlb_ent, 0x0UL);
761                         }
762                 }
763         }
764         __asm__ __volatile__("wrpr      %0, 0, %%pstate"
765                              : : "r" (pstate));
766 }
767
768 void inherit_locked_prom_mappings(int save_p)
769 {
770         int i;
771         int dtlb_seen = 0;
772         int itlb_seen = 0;
773
774         /* Fucking losing PROM has more mappings in the TLB, but
775          * it (conveniently) fails to mention any of these in the
776          * translations property.  The only ones that matter are
777          * the locked PROM tlb entries, so we impose the following
778          * irrecovable rule on the PROM, it is allowed 8 locked
779          * entries in the ITLB and 8 in the DTLB.
780          *
781          * Supposedly the upper 16GB of the address space is
782          * reserved for OBP, BUT I WISH THIS WAS DOCUMENTED
783          * SOMEWHERE!!!!!!!!!!!!!!!!!  Furthermore the entire interface
784          * used between the client program and the firmware on sun5
785          * systems to coordinate mmu mappings is also COMPLETELY
786          * UNDOCUMENTED!!!!!! Thanks S(t)un!
787          */
788         if (save_p) {
789                 for (i = 0; i < 16; i++) {
790                         prom_itlb[i].tlb_ent = -1;
791                         prom_dtlb[i].tlb_ent = -1;
792                 }
793         }
794         if (tlb_type == spitfire) {
795                 int high = SPITFIRE_HIGHEST_LOCKED_TLBENT - bigkernel;
796                 for (i = 0; i < high; i++) {
797                         unsigned long data;
798
799                         /* Spitfire Errata #32 workaround */
800                         /* NOTE: Always runs on spitfire, so no cheetah+
801                          *       page size encodings.
802                          */
803                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
804                                              "flush     %%g6"
805                                              : /* No outputs */
806                                              : "r" (0),
807                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
808
809                         data = spitfire_get_dtlb_data(i);
810                         if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
811                                 unsigned long tag;
812
813                                 /* Spitfire Errata #32 workaround */
814                                 /* NOTE: Always runs on spitfire, so no
815                                  *       cheetah+ page size encodings.
816                                  */
817                                 __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
818                                                      "flush     %%g6"
819                                                      : /* No outputs */
820                                                      : "r" (0),
821                                                      "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
822
823                                 tag = spitfire_get_dtlb_tag(i);
824                                 if (save_p) {
825                                         prom_dtlb[dtlb_seen].tlb_ent = i;
826                                         prom_dtlb[dtlb_seen].tlb_tag = tag;
827                                         prom_dtlb[dtlb_seen].tlb_data = data;
828                                 }
829                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
830                                                      "membar #Sync"
831                                                      : : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
832                                 spitfire_put_dtlb_data(i, 0x0UL);
833
834                                 dtlb_seen++;
835                                 if (dtlb_seen > 15)
836                                         break;
837                         }
838                 }
839
840                 for (i = 0; i < high; i++) {
841                         unsigned long data;
842
843                         /* Spitfire Errata #32 workaround */
844                         /* NOTE: Always runs on spitfire, so no
845                          *       cheetah+ page size encodings.
846                          */
847                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
848                                              "flush     %%g6"
849                                              : /* No outputs */
850                                              : "r" (0),
851                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
852
853                         data = spitfire_get_itlb_data(i);
854                         if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
855                                 unsigned long tag;
856
857                                 /* Spitfire Errata #32 workaround */
858                                 /* NOTE: Always runs on spitfire, so no
859                                  *       cheetah+ page size encodings.
860                                  */
861                                 __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
862                                                      "flush     %%g6"
863                                                      : /* No outputs */
864                                                      : "r" (0),
865                                                      "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
866
867                                 tag = spitfire_get_itlb_tag(i);
868                                 if (save_p) {
869                                         prom_itlb[itlb_seen].tlb_ent = i;
870                                         prom_itlb[itlb_seen].tlb_tag = tag;
871                                         prom_itlb[itlb_seen].tlb_data = data;
872                                 }
873                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
874                                                      "membar #Sync"
875                                                      : : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
876                                 spitfire_put_itlb_data(i, 0x0UL);
877
878                                 itlb_seen++;
879                                 if (itlb_seen > 15)
880                                         break;
881                         }
882                 }
883         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
884                 int high = CHEETAH_HIGHEST_LOCKED_TLBENT - bigkernel;
885
886                 for (i = 0; i < high; i++) {
887                         unsigned long data;
888
889                         data = cheetah_get_ldtlb_data(i);
890                         if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
891                                 unsigned long tag;
892
893                                 tag = cheetah_get_ldtlb_tag(i);
894                                 if (save_p) {
895                                         prom_dtlb[dtlb_seen].tlb_ent = i;
896                                         prom_dtlb[dtlb_seen].tlb_tag = tag;
897                                         prom_dtlb[dtlb_seen].tlb_data = data;
898                                 }
899                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
900                                                      "membar #Sync"
901                                                      : : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
902                                 cheetah_put_ldtlb_data(i, 0x0UL);
903
904                                 dtlb_seen++;
905                                 if (dtlb_seen > 15)
906                                         break;
907                         }
908                 }
909
910                 for (i = 0; i < high; i++) {
911                         unsigned long data;
912
913                         data = cheetah_get_litlb_data(i);
914                         if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
915                                 unsigned long tag;
916
917                                 tag = cheetah_get_litlb_tag(i);
918                                 if (save_p) {
919                                         prom_itlb[itlb_seen].tlb_ent = i;
920                                         prom_itlb[itlb_seen].tlb_tag = tag;
921                                         prom_itlb[itlb_seen].tlb_data = data;
922                                 }
923                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
924                                                      "membar #Sync"
925                                                      : : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
926                                 cheetah_put_litlb_data(i, 0x0UL);
927
928                                 itlb_seen++;
929                                 if (itlb_seen > 15)
930                                         break;
931                         }
932                 }
933         } else {
934                 /* Implement me :-) */
935                 BUG();
936         }
937         if (save_p)
938                 prom_ditlb_set = 1;
939 }
940
941 /* Give PROM back his world, done during reboots... */
942 void prom_reload_locked(void)
943 {
944         int i;
945
946         for (i = 0; i < 16; i++) {
947                 if (prom_dtlb[i].tlb_ent != -1) {
948                         __asm__ __volatile__("stxa %0, [%1] %2\n\t"
949                                              "membar #Sync"
950                                 : : "r" (prom_dtlb[i].tlb_tag), "r" (TLB_TAG_ACCESS),
951                                 "i" (ASI_DMMU));
952                         if (tlb_type == spitfire)
953                                 spitfire_put_dtlb_data(prom_dtlb[i].tlb_ent,
954                                                        prom_dtlb[i].tlb_data);
955                         else if (tlb_type == cheetah || tlb_type == cheetah_plus)
956                                 cheetah_put_ldtlb_data(prom_dtlb[i].tlb_ent,
957                                                       prom_dtlb[i].tlb_data);
958                 }
959
960                 if (prom_itlb[i].tlb_ent != -1) {
961                         __asm__ __volatile__("stxa %0, [%1] %2\n\t"
962                                              "membar #Sync"
963                                              : : "r" (prom_itlb[i].tlb_tag),
964                                              "r" (TLB_TAG_ACCESS),
965                                              "i" (ASI_IMMU));
966                         if (tlb_type == spitfire)
967                                 spitfire_put_itlb_data(prom_itlb[i].tlb_ent,
968                                                        prom_itlb[i].tlb_data);
969                         else
970                                 cheetah_put_litlb_data(prom_itlb[i].tlb_ent,
971                                                        prom_itlb[i].tlb_data);
972                 }
973         }
974 }
975
976 #ifdef DCACHE_ALIASING_POSSIBLE
977 void __flush_dcache_range(unsigned long start, unsigned long end)
978 {
979         unsigned long va;
980
981         if (tlb_type == spitfire) {
982                 int n = 0;
983
984                 for (va = start; va < end; va += 32) {
985                         spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
986                         if (++n >= 512)
987                                 break;
988                 }
989         } else {
990                 start = __pa(start);
991                 end = __pa(end);
992                 for (va = start; va < end; va += 32)
993                         __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
994                                              "membar #Sync"
995                                              : /* no outputs */
996                                              : "r" (va),
997                                                "i" (ASI_DCACHE_INVALIDATE));
998         }
999 }
1000 #endif /* DCACHE_ALIASING_POSSIBLE */
1001
1002 /* If not locked, zap it. */
1003 void __flush_tlb_all(void)
1004 {
1005         unsigned long pstate;
1006         int i;
1007
1008         __asm__ __volatile__("flushw\n\t"
1009                              "rdpr      %%pstate, %0\n\t"
1010                              "wrpr      %0, %1, %%pstate"
1011                              : "=r" (pstate)
1012                              : "i" (PSTATE_IE));
1013         if (tlb_type == spitfire) {
1014                 for (i = 0; i < 64; i++) {
1015                         /* Spitfire Errata #32 workaround */
1016                         /* NOTE: Always runs on spitfire, so no
1017                          *       cheetah+ page size encodings.
1018                          */
1019                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
1020                                              "flush     %%g6"
1021                                              : /* No outputs */
1022                                              : "r" (0),
1023                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1024
1025                         if (!(spitfire_get_dtlb_data(i) & _PAGE_L)) {
1026                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1027                                                      "membar #Sync"
1028                                                      : /* no outputs */
1029                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
1030                                 spitfire_put_dtlb_data(i, 0x0UL);
1031                         }
1032
1033                         /* Spitfire Errata #32 workaround */
1034                         /* NOTE: Always runs on spitfire, so no
1035                          *       cheetah+ page size encodings.
1036                          */
1037                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
1038                                              "flush     %%g6"
1039                                              : /* No outputs */
1040                                              : "r" (0),
1041                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1042
1043                         if (!(spitfire_get_itlb_data(i) & _PAGE_L)) {
1044                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1045                                                      "membar #Sync"
1046                                                      : /* no outputs */
1047                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
1048                                 spitfire_put_itlb_data(i, 0x0UL);
1049                         }
1050                 }
1051         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1052                 cheetah_flush_dtlb_all();
1053                 cheetah_flush_itlb_all();
1054         }
1055         __asm__ __volatile__("wrpr      %0, 0, %%pstate"
1056                              : : "r" (pstate));
1057 }
1058
1059 /* Caller does TLB context flushing on local CPU if necessary.
1060  * The caller also ensures that CTX_VALID(mm->context) is false.
1061  *
1062  * We must be careful about boundary cases so that we never
1063  * let the user have CTX 0 (nucleus) or we ever use a CTX
1064  * version of zero (and thus NO_CONTEXT would not be caught
1065  * by version mis-match tests in mmu_context.h).
1066  */
1067 void get_new_mmu_context(struct mm_struct *mm)
1068 {
1069         unsigned long ctx, new_ctx;
1070         unsigned long orig_pgsz_bits;
1071         
1072
1073         spin_lock(&ctx_alloc_lock);
1074         orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
1075         ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
1076         new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
1077         if (new_ctx >= (1 << CTX_NR_BITS)) {
1078                 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
1079                 if (new_ctx >= ctx) {
1080                         int i;
1081                         new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
1082                                 CTX_FIRST_VERSION;
1083                         if (new_ctx == 1)
1084                                 new_ctx = CTX_FIRST_VERSION;
1085
1086                         /* Don't call memset, for 16 entries that's just
1087                          * plain silly...
1088                          */
1089                         mmu_context_bmap[0] = 3;
1090                         mmu_context_bmap[1] = 0;
1091                         mmu_context_bmap[2] = 0;
1092                         mmu_context_bmap[3] = 0;
1093                         for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
1094                                 mmu_context_bmap[i + 0] = 0;
1095                                 mmu_context_bmap[i + 1] = 0;
1096                                 mmu_context_bmap[i + 2] = 0;
1097                                 mmu_context_bmap[i + 3] = 0;
1098                         }
1099                         goto out;
1100                 }
1101         }
1102         mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
1103         new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
1104 out:
1105         tlb_context_cache = new_ctx;
1106         mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
1107         spin_unlock(&ctx_alloc_lock);
1108 }
1109
1110 #ifndef CONFIG_SMP
1111 struct pgtable_cache_struct pgt_quicklists;
1112 #endif
1113
1114 /* OK, we have to color these pages. The page tables are accessed
1115  * by non-Dcache enabled mapping in the VPTE area by the dtlb_backend.S
1116  * code, as well as by PAGE_OFFSET range direct-mapped addresses by 
1117  * other parts of the kernel. By coloring, we make sure that the tlbmiss 
1118  * fast handlers do not get data from old/garbage dcache lines that 
1119  * correspond to an old/stale virtual address (user/kernel) that 
1120  * previously mapped the pagetable page while accessing vpte range 
1121  * addresses. The idea is that if the vpte color and PAGE_OFFSET range 
1122  * color is the same, then when the kernel initializes the pagetable 
1123  * using the later address range, accesses with the first address
1124  * range will see the newly initialized data rather than the garbage.
1125  */
1126 #ifdef DCACHE_ALIASING_POSSIBLE
1127 #define DC_ALIAS_SHIFT  1
1128 #else
1129 #define DC_ALIAS_SHIFT  0
1130 #endif
1131 pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address)
1132 {
1133         struct page *page;
1134         unsigned long color;
1135
1136         {
1137                 pte_t *ptep = pte_alloc_one_fast(mm, address);
1138
1139                 if (ptep)
1140                         return ptep;
1141         }
1142
1143         color = VPTE_COLOR(address);
1144         page = alloc_pages(GFP_KERNEL|__GFP_REPEAT, DC_ALIAS_SHIFT);
1145         if (page) {
1146                 unsigned long *to_free;
1147                 unsigned long paddr;
1148                 pte_t *pte;
1149
1150 #ifdef DCACHE_ALIASING_POSSIBLE
1151                 set_page_count(page, 1);
1152                 ClearPageCompound(page);
1153
1154                 set_page_count((page + 1), 1);
1155                 ClearPageCompound(page + 1);
1156 #endif
1157                 paddr = (unsigned long) page_address(page);
1158                 memset((char *)paddr, 0, (PAGE_SIZE << DC_ALIAS_SHIFT));
1159
1160                 if (!color) {
1161                         pte = (pte_t *) paddr;
1162                         to_free = (unsigned long *) (paddr + PAGE_SIZE);
1163                 } else {
1164                         pte = (pte_t *) (paddr + PAGE_SIZE);
1165                         to_free = (unsigned long *) paddr;
1166                 }
1167
1168 #ifdef DCACHE_ALIASING_POSSIBLE
1169                 /* Now free the other one up, adjust cache size. */
1170                 preempt_disable();
1171                 *to_free = (unsigned long) pte_quicklist[color ^ 0x1];
1172                 pte_quicklist[color ^ 0x1] = to_free;
1173                 pgtable_cache_size++;
1174                 preempt_enable();
1175 #endif
1176
1177                 return pte;
1178         }
1179         return NULL;
1180 }
1181
1182 void sparc_ultra_dump_itlb(void)
1183 {
1184         int slot;
1185
1186         if (tlb_type == spitfire) {
1187                 printk ("Contents of itlb: ");
1188                 for (slot = 0; slot < 14; slot++) printk ("    ");
1189                 printk ("%2x:%016lx,%016lx\n",
1190                         0,
1191                         spitfire_get_itlb_tag(0), spitfire_get_itlb_data(0));
1192                 for (slot = 1; slot < 64; slot+=3) {
1193                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n", 
1194                                 slot,
1195                                 spitfire_get_itlb_tag(slot), spitfire_get_itlb_data(slot),
1196                                 slot+1,
1197                                 spitfire_get_itlb_tag(slot+1), spitfire_get_itlb_data(slot+1),
1198                                 slot+2,
1199                                 spitfire_get_itlb_tag(slot+2), spitfire_get_itlb_data(slot+2));
1200                 }
1201         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1202                 printk ("Contents of itlb0:\n");
1203                 for (slot = 0; slot < 16; slot+=2) {
1204                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1205                                 slot,
1206                                 cheetah_get_litlb_tag(slot), cheetah_get_litlb_data(slot),
1207                                 slot+1,
1208                                 cheetah_get_litlb_tag(slot+1), cheetah_get_litlb_data(slot+1));
1209                 }
1210                 printk ("Contents of itlb2:\n");
1211                 for (slot = 0; slot < 128; slot+=2) {
1212                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1213                                 slot,
1214                                 cheetah_get_itlb_tag(slot), cheetah_get_itlb_data(slot),
1215                                 slot+1,
1216                                 cheetah_get_itlb_tag(slot+1), cheetah_get_itlb_data(slot+1));
1217                 }
1218         }
1219 }
1220
1221 void sparc_ultra_dump_dtlb(void)
1222 {
1223         int slot;
1224
1225         if (tlb_type == spitfire) {
1226                 printk ("Contents of dtlb: ");
1227                 for (slot = 0; slot < 14; slot++) printk ("    ");
1228                 printk ("%2x:%016lx,%016lx\n", 0,
1229                         spitfire_get_dtlb_tag(0), spitfire_get_dtlb_data(0));
1230                 for (slot = 1; slot < 64; slot+=3) {
1231                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n", 
1232                                 slot,
1233                                 spitfire_get_dtlb_tag(slot), spitfire_get_dtlb_data(slot),
1234                                 slot+1,
1235                                 spitfire_get_dtlb_tag(slot+1), spitfire_get_dtlb_data(slot+1),
1236                                 slot+2,
1237                                 spitfire_get_dtlb_tag(slot+2), spitfire_get_dtlb_data(slot+2));
1238                 }
1239         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1240                 printk ("Contents of dtlb0:\n");
1241                 for (slot = 0; slot < 16; slot+=2) {
1242                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1243                                 slot,
1244                                 cheetah_get_ldtlb_tag(slot), cheetah_get_ldtlb_data(slot),
1245                                 slot+1,
1246                                 cheetah_get_ldtlb_tag(slot+1), cheetah_get_ldtlb_data(slot+1));
1247                 }
1248                 printk ("Contents of dtlb2:\n");
1249                 for (slot = 0; slot < 512; slot+=2) {
1250                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1251                                 slot,
1252                                 cheetah_get_dtlb_tag(slot, 2), cheetah_get_dtlb_data(slot, 2),
1253                                 slot+1,
1254                                 cheetah_get_dtlb_tag(slot+1, 2), cheetah_get_dtlb_data(slot+1, 2));
1255                 }
1256                 if (tlb_type == cheetah_plus) {
1257                         printk ("Contents of dtlb3:\n");
1258                         for (slot = 0; slot < 512; slot+=2) {
1259                                 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1260                                         slot,
1261                                         cheetah_get_dtlb_tag(slot, 3), cheetah_get_dtlb_data(slot, 3),
1262                                         slot+1,
1263                                         cheetah_get_dtlb_tag(slot+1, 3), cheetah_get_dtlb_data(slot+1, 3));
1264                         }
1265                 }
1266         }
1267 }
1268
1269 extern unsigned long cmdline_memory_size;
1270
1271 unsigned long __init bootmem_init(unsigned long *pages_avail)
1272 {
1273         unsigned long bootmap_size, start_pfn, end_pfn;
1274         unsigned long end_of_phys_memory = 0UL;
1275         unsigned long bootmap_pfn, bytes_avail, size;
1276         int i;
1277
1278 #ifdef CONFIG_DEBUG_BOOTMEM
1279         prom_printf("bootmem_init: Scan sp_banks, ");
1280 #endif
1281
1282         bytes_avail = 0UL;
1283         for (i = 0; sp_banks[i].num_bytes != 0; i++) {
1284                 end_of_phys_memory = sp_banks[i].base_addr +
1285                         sp_banks[i].num_bytes;
1286                 bytes_avail += sp_banks[i].num_bytes;
1287                 if (cmdline_memory_size) {
1288                         if (bytes_avail > cmdline_memory_size) {
1289                                 unsigned long slack = bytes_avail - cmdline_memory_size;
1290
1291                                 bytes_avail -= slack;
1292                                 end_of_phys_memory -= slack;
1293
1294                                 sp_banks[i].num_bytes -= slack;
1295                                 if (sp_banks[i].num_bytes == 0) {
1296                                         sp_banks[i].base_addr = 0xdeadbeef;
1297                                 } else {
1298                                         sp_banks[i+1].num_bytes = 0;
1299                                         sp_banks[i+1].base_addr = 0xdeadbeef;
1300                                 }
1301                                 break;
1302                         }
1303                 }
1304         }
1305
1306         *pages_avail = bytes_avail >> PAGE_SHIFT;
1307
1308         /* Start with page aligned address of last symbol in kernel
1309          * image.  The kernel is hard mapped below PAGE_OFFSET in a
1310          * 4MB locked TLB translation.
1311          */
1312         start_pfn = PAGE_ALIGN(kern_base + kern_size) >> PAGE_SHIFT;
1313
1314         bootmap_pfn = start_pfn;
1315
1316         end_pfn = end_of_phys_memory >> PAGE_SHIFT;
1317
1318 #ifdef CONFIG_BLK_DEV_INITRD
1319         /* Now have to check initial ramdisk, so that bootmap does not overwrite it */
1320         if (sparc_ramdisk_image || sparc_ramdisk_image64) {
1321                 unsigned long ramdisk_image = sparc_ramdisk_image ?
1322                         sparc_ramdisk_image : sparc_ramdisk_image64;
1323                 if (ramdisk_image >= (unsigned long)_end - 2 * PAGE_SIZE)
1324                         ramdisk_image -= KERNBASE;
1325                 initrd_start = ramdisk_image + phys_base;
1326                 initrd_end = initrd_start + sparc_ramdisk_size;
1327                 if (initrd_end > end_of_phys_memory) {
1328                         printk(KERN_CRIT "initrd extends beyond end of memory "
1329                                          "(0x%016lx > 0x%016lx)\ndisabling initrd\n",
1330                                initrd_end, end_of_phys_memory);
1331                         initrd_start = 0;
1332                 }
1333                 if (initrd_start) {
1334                         if (initrd_start >= (start_pfn << PAGE_SHIFT) &&
1335                             initrd_start < (start_pfn << PAGE_SHIFT) + 2 * PAGE_SIZE)
1336                                 bootmap_pfn = PAGE_ALIGN (initrd_end) >> PAGE_SHIFT;
1337                 }
1338         }
1339 #endif  
1340         /* Initialize the boot-time allocator. */
1341         max_pfn = max_low_pfn = end_pfn;
1342         min_low_pfn = pfn_base;
1343
1344 #ifdef CONFIG_DEBUG_BOOTMEM
1345         prom_printf("init_bootmem(min[%lx], bootmap[%lx], max[%lx])\n",
1346                     min_low_pfn, bootmap_pfn, max_low_pfn);
1347 #endif
1348         bootmap_size = init_bootmem_node(NODE_DATA(0), bootmap_pfn, pfn_base, end_pfn);
1349
1350         bootmap_base = bootmap_pfn << PAGE_SHIFT;
1351
1352         /* Now register the available physical memory with the
1353          * allocator.
1354          */
1355         for (i = 0; sp_banks[i].num_bytes != 0; i++) {
1356 #ifdef CONFIG_DEBUG_BOOTMEM
1357                 prom_printf("free_bootmem(sp_banks:%d): base[%lx] size[%lx]\n",
1358                             i, sp_banks[i].base_addr, sp_banks[i].num_bytes);
1359 #endif
1360                 free_bootmem(sp_banks[i].base_addr, sp_banks[i].num_bytes);
1361         }
1362
1363 #ifdef CONFIG_BLK_DEV_INITRD
1364         if (initrd_start) {
1365                 size = initrd_end - initrd_start;
1366
1367                 /* Resert the initrd image area. */
1368 #ifdef CONFIG_DEBUG_BOOTMEM
1369                 prom_printf("reserve_bootmem(initrd): base[%llx] size[%lx]\n",
1370                         initrd_start, initrd_end);
1371 #endif
1372                 reserve_bootmem(initrd_start, size);
1373                 *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
1374
1375                 initrd_start += PAGE_OFFSET;
1376                 initrd_end += PAGE_OFFSET;
1377         }
1378 #endif
1379         /* Reserve the kernel text/data/bss. */
1380 #ifdef CONFIG_DEBUG_BOOTMEM
1381         prom_printf("reserve_bootmem(kernel): base[%lx] size[%lx]\n", kern_base, kern_size);
1382 #endif
1383         reserve_bootmem(kern_base, kern_size);
1384         *pages_avail -= PAGE_ALIGN(kern_size) >> PAGE_SHIFT;
1385
1386         /* Reserve the bootmem map.   We do not account for it
1387          * in pages_avail because we will release that memory
1388          * in free_all_bootmem.
1389          */
1390         size = bootmap_size;
1391 #ifdef CONFIG_DEBUG_BOOTMEM
1392         prom_printf("reserve_bootmem(bootmap): base[%lx] size[%lx]\n",
1393                     (bootmap_pfn << PAGE_SHIFT), size);
1394 #endif
1395         reserve_bootmem((bootmap_pfn << PAGE_SHIFT), size);
1396         *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
1397
1398         return end_pfn;
1399 }
1400
1401 /* paging_init() sets up the page tables */
1402
1403 extern void cheetah_ecache_flush_init(void);
1404
1405 static unsigned long last_valid_pfn;
1406
1407 void __init paging_init(void)
1408 {
1409         extern pmd_t swapper_pmd_dir[1024];
1410         extern unsigned int sparc64_vpte_patchme1[1];
1411         extern unsigned int sparc64_vpte_patchme2[1];
1412         unsigned long alias_base = kern_base + PAGE_OFFSET;
1413         unsigned long second_alias_page = 0;
1414         unsigned long pt, flags, end_pfn, pages_avail;
1415         unsigned long shift = alias_base - ((unsigned long)KERNBASE);
1416         unsigned long real_end;
1417
1418         set_bit(0, mmu_context_bmap);
1419
1420         real_end = (unsigned long)_end;
1421         if ((real_end > ((unsigned long)KERNBASE + 0x400000)))
1422                 bigkernel = 1;
1423 #ifdef CONFIG_BLK_DEV_INITRD
1424         if (sparc_ramdisk_image || sparc_ramdisk_image64)
1425                 real_end = (PAGE_ALIGN(real_end) + PAGE_ALIGN(sparc_ramdisk_size));
1426 #endif
1427
1428         /* We assume physical memory starts at some 4mb multiple,
1429          * if this were not true we wouldn't boot up to this point
1430          * anyways.
1431          */
1432         pt  = kern_base | _PAGE_VALID | _PAGE_SZ4MB;
1433         pt |= _PAGE_CP | _PAGE_CV | _PAGE_P | _PAGE_L | _PAGE_W;
1434         local_irq_save(flags);
1435         if (tlb_type == spitfire) {
1436                 __asm__ __volatile__(
1437         "       stxa    %1, [%0] %3\n"
1438         "       stxa    %2, [%5] %4\n"
1439         "       membar  #Sync\n"
1440         "       flush   %%g6\n"
1441         "       nop\n"
1442         "       nop\n"
1443         "       nop\n"
1444                 : /* No outputs */
1445                 : "r" (TLB_TAG_ACCESS), "r" (alias_base), "r" (pt),
1446                   "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS), "r" (61 << 3)
1447                 : "memory");
1448                 if (real_end >= KERNBASE + 0x340000) {
1449                         second_alias_page = alias_base + 0x400000;
1450                         __asm__ __volatile__(
1451                 "       stxa    %1, [%0] %3\n"
1452                 "       stxa    %2, [%5] %4\n"
1453                 "       membar  #Sync\n"
1454                 "       flush   %%g6\n"
1455                 "       nop\n"
1456                 "       nop\n"
1457                 "       nop\n"
1458                         : /* No outputs */
1459                         : "r" (TLB_TAG_ACCESS), "r" (second_alias_page), "r" (pt + 0x400000),
1460                           "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS), "r" (60 << 3)
1461                         : "memory");
1462                 }
1463         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1464                 __asm__ __volatile__(
1465         "       stxa    %1, [%0] %3\n"
1466         "       stxa    %2, [%5] %4\n"
1467         "       membar  #Sync\n"
1468         "       flush   %%g6\n"
1469         "       nop\n"
1470         "       nop\n"
1471         "       nop\n"
1472                 : /* No outputs */
1473                 : "r" (TLB_TAG_ACCESS), "r" (alias_base), "r" (pt),
1474                   "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS), "r" ((0<<16) | (13<<3))
1475                 : "memory");
1476                 if (real_end >= KERNBASE + 0x340000) {
1477                         second_alias_page = alias_base + 0x400000;
1478                         __asm__ __volatile__(
1479                 "       stxa    %1, [%0] %3\n"
1480                 "       stxa    %2, [%5] %4\n"
1481                 "       membar  #Sync\n"
1482                 "       flush   %%g6\n"
1483                 "       nop\n"
1484                 "       nop\n"
1485                 "       nop\n"
1486                         : /* No outputs */
1487                         : "r" (TLB_TAG_ACCESS), "r" (second_alias_page), "r" (pt + 0x400000),
1488                           "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS), "r" ((0<<16) | (12<<3))
1489                         : "memory");
1490                 }
1491         }
1492         local_irq_restore(flags);
1493         
1494         /* Now set kernel pgd to upper alias so physical page computations
1495          * work.
1496          */
1497         init_mm.pgd += ((shift) / (sizeof(pgd_t)));
1498         
1499         memset(swapper_pmd_dir, 0, sizeof(swapper_pmd_dir));
1500
1501         /* Now can init the kernel/bad page tables. */
1502         pud_set(pud_offset(&swapper_pg_dir[0], 0),
1503                 swapper_pmd_dir + (shift / sizeof(pgd_t)));
1504         
1505         sparc64_vpte_patchme1[0] |=
1506                 (((unsigned long)pgd_val(init_mm.pgd[0])) >> 10);
1507         sparc64_vpte_patchme2[0] |=
1508                 (((unsigned long)pgd_val(init_mm.pgd[0])) & 0x3ff);
1509         flushi((long)&sparc64_vpte_patchme1[0]);
1510         
1511         /* Setup bootmem... */
1512         pages_avail = 0;
1513         last_valid_pfn = end_pfn = bootmem_init(&pages_avail);
1514
1515         /* Inherit non-locked OBP mappings. */
1516         inherit_prom_mappings();
1517         
1518         /* Ok, we can use our TLB miss and window trap handlers safely.
1519          * We need to do a quick peek here to see if we are on StarFire
1520          * or not, so setup_tba can setup the IRQ globals correctly (it
1521          * needs to get the hard smp processor id correctly).
1522          */
1523         {
1524                 extern void setup_tba(int);
1525                 setup_tba(this_is_starfire);
1526         }
1527
1528         inherit_locked_prom_mappings(1);
1529
1530         /* We only created DTLB mapping of this stuff. */
1531         spitfire_flush_dtlb_nucleus_page(alias_base);
1532         if (second_alias_page)
1533                 spitfire_flush_dtlb_nucleus_page(second_alias_page);
1534
1535         __flush_tlb_all();
1536
1537         {
1538                 unsigned long zones_size[MAX_NR_ZONES];
1539                 unsigned long zholes_size[MAX_NR_ZONES];
1540                 unsigned long npages;
1541                 int znum;
1542
1543                 for (znum = 0; znum < MAX_NR_ZONES; znum++)
1544                         zones_size[znum] = zholes_size[znum] = 0;
1545
1546                 npages = end_pfn - pfn_base;
1547                 zones_size[ZONE_DMA] = npages;
1548                 zholes_size[ZONE_DMA] = npages - pages_avail;
1549
1550                 free_area_init_node(0, &contig_page_data, zones_size,
1551                                     phys_base >> PAGE_SHIFT, zholes_size);
1552         }
1553
1554         device_scan();
1555 }
1556
1557 /* Ok, it seems that the prom can allocate some more memory chunks
1558  * as a side effect of some prom calls we perform during the
1559  * boot sequence.  My most likely theory is that it is from the
1560  * prom_set_traptable() call, and OBP is allocating a scratchpad
1561  * for saving client program register state etc.
1562  */
1563 static void __init sort_memlist(struct linux_mlist_p1275 *thislist)
1564 {
1565         int swapi = 0;
1566         int i, mitr;
1567         unsigned long tmpaddr, tmpsize;
1568         unsigned long lowest;
1569
1570         for (i = 0; thislist[i].theres_more != 0; i++) {
1571                 lowest = thislist[i].start_adr;
1572                 for (mitr = i+1; thislist[mitr-1].theres_more != 0; mitr++)
1573                         if (thislist[mitr].start_adr < lowest) {
1574                                 lowest = thislist[mitr].start_adr;
1575                                 swapi = mitr;
1576                         }
1577                 if (lowest == thislist[i].start_adr)
1578                         continue;
1579                 tmpaddr = thislist[swapi].start_adr;
1580                 tmpsize = thislist[swapi].num_bytes;
1581                 for (mitr = swapi; mitr > i; mitr--) {
1582                         thislist[mitr].start_adr = thislist[mitr-1].start_adr;
1583                         thislist[mitr].num_bytes = thislist[mitr-1].num_bytes;
1584                 }
1585                 thislist[i].start_adr = tmpaddr;
1586                 thislist[i].num_bytes = tmpsize;
1587         }
1588 }
1589
1590 void __init rescan_sp_banks(void)
1591 {
1592         struct linux_prom64_registers memlist[64];
1593         struct linux_mlist_p1275 avail[64], *mlist;
1594         unsigned long bytes, base_paddr;
1595         int num_regs, node = prom_finddevice("/memory");
1596         int i;
1597
1598         num_regs = prom_getproperty(node, "available",
1599                                     (char *) memlist, sizeof(memlist));
1600         num_regs = (num_regs / sizeof(struct linux_prom64_registers));
1601         for (i = 0; i < num_regs; i++) {
1602                 avail[i].start_adr = memlist[i].phys_addr;
1603                 avail[i].num_bytes = memlist[i].reg_size;
1604                 avail[i].theres_more = &avail[i + 1];
1605         }
1606         avail[i - 1].theres_more = NULL;
1607         sort_memlist(avail);
1608
1609         mlist = &avail[0];
1610         i = 0;
1611         bytes = mlist->num_bytes;
1612         base_paddr = mlist->start_adr;
1613   
1614         sp_banks[0].base_addr = base_paddr;
1615         sp_banks[0].num_bytes = bytes;
1616
1617         while (mlist->theres_more != NULL){
1618                 i++;
1619                 mlist = mlist->theres_more;
1620                 bytes = mlist->num_bytes;
1621                 if (i >= SPARC_PHYS_BANKS-1) {
1622                         printk ("The machine has more banks than "
1623                                 "this kernel can support\n"
1624                                 "Increase the SPARC_PHYS_BANKS "
1625                                 "setting (currently %d)\n",
1626                                 SPARC_PHYS_BANKS);
1627                         i = SPARC_PHYS_BANKS-1;
1628                         break;
1629                 }
1630     
1631                 sp_banks[i].base_addr = mlist->start_adr;
1632                 sp_banks[i].num_bytes = mlist->num_bytes;
1633         }
1634
1635         i++;
1636         sp_banks[i].base_addr = 0xdeadbeefbeefdeadUL;
1637         sp_banks[i].num_bytes = 0;
1638
1639         for (i = 0; sp_banks[i].num_bytes != 0; i++)
1640                 sp_banks[i].num_bytes &= PAGE_MASK;
1641 }
1642
1643 static void __init taint_real_pages(void)
1644 {
1645         struct sparc_phys_banks saved_sp_banks[SPARC_PHYS_BANKS];
1646         int i;
1647
1648         for (i = 0; i < SPARC_PHYS_BANKS; i++) {
1649                 saved_sp_banks[i].base_addr =
1650                         sp_banks[i].base_addr;
1651                 saved_sp_banks[i].num_bytes =
1652                         sp_banks[i].num_bytes;
1653         }
1654
1655         rescan_sp_banks();
1656
1657         /* Find changes discovered in the sp_bank rescan and
1658          * reserve the lost portions in the bootmem maps.
1659          */
1660         for (i = 0; saved_sp_banks[i].num_bytes; i++) {
1661                 unsigned long old_start, old_end;
1662
1663                 old_start = saved_sp_banks[i].base_addr;
1664                 old_end = old_start +
1665                         saved_sp_banks[i].num_bytes;
1666                 while (old_start < old_end) {
1667                         int n;
1668
1669                         for (n = 0; sp_banks[n].num_bytes; n++) {
1670                                 unsigned long new_start, new_end;
1671
1672                                 new_start = sp_banks[n].base_addr;
1673                                 new_end = new_start + sp_banks[n].num_bytes;
1674
1675                                 if (new_start <= old_start &&
1676                                     new_end >= (old_start + PAGE_SIZE)) {
1677                                         set_bit (old_start >> 22,
1678                                                  sparc64_valid_addr_bitmap);
1679                                         goto do_next_page;
1680                                 }
1681                         }
1682                         reserve_bootmem(old_start, PAGE_SIZE);
1683
1684                 do_next_page:
1685                         old_start += PAGE_SIZE;
1686                 }
1687         }
1688 }
1689
1690 void __init mem_init(void)
1691 {
1692         unsigned long codepages, datapages, initpages;
1693         unsigned long addr, last;
1694         int i;
1695
1696         i = last_valid_pfn >> ((22 - PAGE_SHIFT) + 6);
1697         i += 1;
1698         sparc64_valid_addr_bitmap = (unsigned long *)
1699                 __alloc_bootmem(i << 3, SMP_CACHE_BYTES, bootmap_base);
1700         if (sparc64_valid_addr_bitmap == NULL) {
1701                 prom_printf("mem_init: Cannot alloc valid_addr_bitmap.\n");
1702                 prom_halt();
1703         }
1704         memset(sparc64_valid_addr_bitmap, 0, i << 3);
1705
1706         addr = PAGE_OFFSET + kern_base;
1707         last = PAGE_ALIGN(kern_size) + addr;
1708         while (addr < last) {
1709                 set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap);
1710                 addr += PAGE_SIZE;
1711         }
1712
1713         taint_real_pages();
1714
1715         max_mapnr = last_valid_pfn - pfn_base;
1716         high_memory = __va(last_valid_pfn << PAGE_SHIFT);
1717
1718 #ifdef CONFIG_DEBUG_BOOTMEM
1719         prom_printf("mem_init: Calling free_all_bootmem().\n");
1720 #endif
1721         totalram_pages = num_physpages = free_all_bootmem() - 1;
1722
1723         /*
1724          * Set up the zero page, mark it reserved, so that page count
1725          * is not manipulated when freeing the page from user ptes.
1726          */
1727         mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
1728         if (mem_map_zero == NULL) {
1729                 prom_printf("paging_init: Cannot alloc zero page.\n");
1730                 prom_halt();
1731         }
1732         SetPageReserved(mem_map_zero);
1733
1734         codepages = (((unsigned long) _etext) - ((unsigned long) _start));
1735         codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT;
1736         datapages = (((unsigned long) _edata) - ((unsigned long) _etext));
1737         datapages = PAGE_ALIGN(datapages) >> PAGE_SHIFT;
1738         initpages = (((unsigned long) __init_end) - ((unsigned long) __init_begin));
1739         initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT;
1740
1741         printk("Memory: %uk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n",
1742                nr_free_pages() << (PAGE_SHIFT-10),
1743                codepages << (PAGE_SHIFT-10),
1744                datapages << (PAGE_SHIFT-10), 
1745                initpages << (PAGE_SHIFT-10), 
1746                PAGE_OFFSET, (last_valid_pfn << PAGE_SHIFT));
1747
1748         if (tlb_type == cheetah || tlb_type == cheetah_plus)
1749                 cheetah_ecache_flush_init();
1750 }
1751
1752 void free_initmem (void)
1753 {
1754         unsigned long addr, initend;
1755
1756         /*
1757          * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
1758          */
1759         addr = PAGE_ALIGN((unsigned long)(__init_begin));
1760         initend = (unsigned long)(__init_end) & PAGE_MASK;
1761         for (; addr < initend; addr += PAGE_SIZE) {
1762                 unsigned long page;
1763                 struct page *p;
1764
1765                 page = (addr +
1766                         ((unsigned long) __va(kern_base)) -
1767                         ((unsigned long) KERNBASE));
1768                 memset((void *)addr, 0xcc, PAGE_SIZE);
1769                 p = virt_to_page(page);
1770
1771                 ClearPageReserved(p);
1772                 set_page_count(p, 1);
1773                 __free_page(p);
1774                 num_physpages++;
1775                 totalram_pages++;
1776         }
1777 }
1778
1779 #ifdef CONFIG_BLK_DEV_INITRD
1780 void free_initrd_mem(unsigned long start, unsigned long end)
1781 {
1782         if (start < end)
1783                 printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
1784         for (; start < end; start += PAGE_SIZE) {
1785                 struct page *p = virt_to_page(start);
1786
1787                 ClearPageReserved(p);
1788                 set_page_count(p, 1);
1789                 __free_page(p);
1790                 num_physpages++;
1791                 totalram_pages++;
1792         }
1793 }
1794 #endif