x86: remove pointless comments
[linux-2.6.git] / arch / sparc64 / mm / init.c
1 /*  $Id: init.c,v 1.209 2002/02/09 19:49:31 davem Exp $
2  *  arch/sparc64/mm/init.c
3  *
4  *  Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
5  *  Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
6  */
7  
8 #include <linux/module.h>
9 #include <linux/kernel.h>
10 #include <linux/sched.h>
11 #include <linux/string.h>
12 #include <linux/init.h>
13 #include <linux/bootmem.h>
14 #include <linux/mm.h>
15 #include <linux/hugetlb.h>
16 #include <linux/slab.h>
17 #include <linux/initrd.h>
18 #include <linux/swap.h>
19 #include <linux/pagemap.h>
20 #include <linux/poison.h>
21 #include <linux/fs.h>
22 #include <linux/seq_file.h>
23 #include <linux/kprobes.h>
24 #include <linux/cache.h>
25 #include <linux/sort.h>
26 #include <linux/percpu.h>
27
28 #include <asm/head.h>
29 #include <asm/system.h>
30 #include <asm/page.h>
31 #include <asm/pgalloc.h>
32 #include <asm/pgtable.h>
33 #include <asm/oplib.h>
34 #include <asm/iommu.h>
35 #include <asm/io.h>
36 #include <asm/uaccess.h>
37 #include <asm/mmu_context.h>
38 #include <asm/tlbflush.h>
39 #include <asm/dma.h>
40 #include <asm/starfire.h>
41 #include <asm/tlb.h>
42 #include <asm/spitfire.h>
43 #include <asm/sections.h>
44 #include <asm/tsb.h>
45 #include <asm/hypervisor.h>
46 #include <asm/prom.h>
47 #include <asm/sstate.h>
48 #include <asm/mdesc.h>
49 #include <asm/cpudata.h>
50
51 #define MAX_PHYS_ADDRESS        (1UL << 42UL)
52 #define KPTE_BITMAP_CHUNK_SZ    (256UL * 1024UL * 1024UL)
53 #define KPTE_BITMAP_BYTES       \
54         ((MAX_PHYS_ADDRESS / KPTE_BITMAP_CHUNK_SZ) / 8)
55
56 unsigned long kern_linear_pte_xor[2] __read_mostly;
57
58 /* A bitmap, one bit for every 256MB of physical memory.  If the bit
59  * is clear, we should use a 4MB page (via kern_linear_pte_xor[0]) else
60  * if set we should use a 256MB page (via kern_linear_pte_xor[1]).
61  */
62 unsigned long kpte_linear_bitmap[KPTE_BITMAP_BYTES / sizeof(unsigned long)];
63
64 #ifndef CONFIG_DEBUG_PAGEALLOC
65 /* A special kernel TSB for 4MB and 256MB linear mappings.
66  * Space is allocated for this right after the trap table
67  * in arch/sparc64/kernel/head.S
68  */
69 extern struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES];
70 #endif
71
72 #define MAX_BANKS       32
73
74 static struct linux_prom64_registers pavail[MAX_BANKS] __initdata;
75 static struct linux_prom64_registers pavail_rescan[MAX_BANKS] __initdata;
76 static int pavail_ents __initdata;
77 static int pavail_rescan_ents __initdata;
78
79 static int cmp_p64(const void *a, const void *b)
80 {
81         const struct linux_prom64_registers *x = a, *y = b;
82
83         if (x->phys_addr > y->phys_addr)
84                 return 1;
85         if (x->phys_addr < y->phys_addr)
86                 return -1;
87         return 0;
88 }
89
90 static void __init read_obp_memory(const char *property,
91                                    struct linux_prom64_registers *regs,
92                                    int *num_ents)
93 {
94         int node = prom_finddevice("/memory");
95         int prop_size = prom_getproplen(node, property);
96         int ents, ret, i;
97
98         ents = prop_size / sizeof(struct linux_prom64_registers);
99         if (ents > MAX_BANKS) {
100                 prom_printf("The machine has more %s property entries than "
101                             "this kernel can support (%d).\n",
102                             property, MAX_BANKS);
103                 prom_halt();
104         }
105
106         ret = prom_getproperty(node, property, (char *) regs, prop_size);
107         if (ret == -1) {
108                 prom_printf("Couldn't get %s property from /memory.\n");
109                 prom_halt();
110         }
111
112         /* Sanitize what we got from the firmware, by page aligning
113          * everything.
114          */
115         for (i = 0; i < ents; i++) {
116                 unsigned long base, size;
117
118                 base = regs[i].phys_addr;
119                 size = regs[i].reg_size;
120
121                 size &= PAGE_MASK;
122                 if (base & ~PAGE_MASK) {
123                         unsigned long new_base = PAGE_ALIGN(base);
124
125                         size -= new_base - base;
126                         if ((long) size < 0L)
127                                 size = 0UL;
128                         base = new_base;
129                 }
130                 if (size == 0UL) {
131                         /* If it is empty, simply get rid of it.
132                          * This simplifies the logic of the other
133                          * functions that process these arrays.
134                          */
135                         memmove(&regs[i], &regs[i + 1],
136                                 (ents - i - 1) * sizeof(regs[0]));
137                         i--;
138                         ents--;
139                         continue;
140                 }
141                 regs[i].phys_addr = base;
142                 regs[i].reg_size = size;
143         }
144
145         *num_ents = ents;
146
147         sort(regs, ents, sizeof(struct linux_prom64_registers),
148              cmp_p64, NULL);
149 }
150
151 unsigned long *sparc64_valid_addr_bitmap __read_mostly;
152
153 /* Kernel physical address base and size in bytes.  */
154 unsigned long kern_base __read_mostly;
155 unsigned long kern_size __read_mostly;
156
157 /* Initial ramdisk setup */
158 extern unsigned long sparc_ramdisk_image64;
159 extern unsigned int sparc_ramdisk_image;
160 extern unsigned int sparc_ramdisk_size;
161
162 struct page *mem_map_zero __read_mostly;
163
164 unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
165
166 unsigned long sparc64_kern_pri_context __read_mostly;
167 unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
168 unsigned long sparc64_kern_sec_context __read_mostly;
169
170 int num_kernel_image_mappings;
171
172 #ifdef CONFIG_DEBUG_DCFLUSH
173 atomic_t dcpage_flushes = ATOMIC_INIT(0);
174 #ifdef CONFIG_SMP
175 atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
176 #endif
177 #endif
178
179 inline void flush_dcache_page_impl(struct page *page)
180 {
181         BUG_ON(tlb_type == hypervisor);
182 #ifdef CONFIG_DEBUG_DCFLUSH
183         atomic_inc(&dcpage_flushes);
184 #endif
185
186 #ifdef DCACHE_ALIASING_POSSIBLE
187         __flush_dcache_page(page_address(page),
188                             ((tlb_type == spitfire) &&
189                              page_mapping(page) != NULL));
190 #else
191         if (page_mapping(page) != NULL &&
192             tlb_type == spitfire)
193                 __flush_icache_page(__pa(page_address(page)));
194 #endif
195 }
196
197 #define PG_dcache_dirty         PG_arch_1
198 #define PG_dcache_cpu_shift     32UL
199 #define PG_dcache_cpu_mask      \
200         ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL)
201
202 #define dcache_dirty_cpu(page) \
203         (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
204
205 static inline void set_dcache_dirty(struct page *page, int this_cpu)
206 {
207         unsigned long mask = this_cpu;
208         unsigned long non_cpu_bits;
209
210         non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
211         mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
212
213         __asm__ __volatile__("1:\n\t"
214                              "ldx       [%2], %%g7\n\t"
215                              "and       %%g7, %1, %%g1\n\t"
216                              "or        %%g1, %0, %%g1\n\t"
217                              "casx      [%2], %%g7, %%g1\n\t"
218                              "cmp       %%g7, %%g1\n\t"
219                              "membar    #StoreLoad | #StoreStore\n\t"
220                              "bne,pn    %%xcc, 1b\n\t"
221                              " nop"
222                              : /* no outputs */
223                              : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
224                              : "g1", "g7");
225 }
226
227 static inline void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
228 {
229         unsigned long mask = (1UL << PG_dcache_dirty);
230
231         __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
232                              "1:\n\t"
233                              "ldx       [%2], %%g7\n\t"
234                              "srlx      %%g7, %4, %%g1\n\t"
235                              "and       %%g1, %3, %%g1\n\t"
236                              "cmp       %%g1, %0\n\t"
237                              "bne,pn    %%icc, 2f\n\t"
238                              " andn     %%g7, %1, %%g1\n\t"
239                              "casx      [%2], %%g7, %%g1\n\t"
240                              "cmp       %%g7, %%g1\n\t"
241                              "membar    #StoreLoad | #StoreStore\n\t"
242                              "bne,pn    %%xcc, 1b\n\t"
243                              " nop\n"
244                              "2:"
245                              : /* no outputs */
246                              : "r" (cpu), "r" (mask), "r" (&page->flags),
247                                "i" (PG_dcache_cpu_mask),
248                                "i" (PG_dcache_cpu_shift)
249                              : "g1", "g7");
250 }
251
252 static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
253 {
254         unsigned long tsb_addr = (unsigned long) ent;
255
256         if (tlb_type == cheetah_plus || tlb_type == hypervisor)
257                 tsb_addr = __pa(tsb_addr);
258
259         __tsb_insert(tsb_addr, tag, pte);
260 }
261
262 unsigned long _PAGE_ALL_SZ_BITS __read_mostly;
263 unsigned long _PAGE_SZBITS __read_mostly;
264
265 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
266 {
267         struct mm_struct *mm;
268         struct tsb *tsb;
269         unsigned long tag, flags;
270         unsigned long tsb_index, tsb_hash_shift;
271
272         if (tlb_type != hypervisor) {
273                 unsigned long pfn = pte_pfn(pte);
274                 unsigned long pg_flags;
275                 struct page *page;
276
277                 if (pfn_valid(pfn) &&
278                     (page = pfn_to_page(pfn), page_mapping(page)) &&
279                     ((pg_flags = page->flags) & (1UL << PG_dcache_dirty))) {
280                         int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
281                                    PG_dcache_cpu_mask);
282                         int this_cpu = get_cpu();
283
284                         /* This is just to optimize away some function calls
285                          * in the SMP case.
286                          */
287                         if (cpu == this_cpu)
288                                 flush_dcache_page_impl(page);
289                         else
290                                 smp_flush_dcache_page_impl(page, cpu);
291
292                         clear_dcache_dirty_cpu(page, cpu);
293
294                         put_cpu();
295                 }
296         }
297
298         mm = vma->vm_mm;
299
300         tsb_index = MM_TSB_BASE;
301         tsb_hash_shift = PAGE_SHIFT;
302
303         spin_lock_irqsave(&mm->context.lock, flags);
304
305 #ifdef CONFIG_HUGETLB_PAGE
306         if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL) {
307                 if ((tlb_type == hypervisor &&
308                      (pte_val(pte) & _PAGE_SZALL_4V) == _PAGE_SZHUGE_4V) ||
309                     (tlb_type != hypervisor &&
310                      (pte_val(pte) & _PAGE_SZALL_4U) == _PAGE_SZHUGE_4U)) {
311                         tsb_index = MM_TSB_HUGE;
312                         tsb_hash_shift = HPAGE_SHIFT;
313                 }
314         }
315 #endif
316
317         tsb = mm->context.tsb_block[tsb_index].tsb;
318         tsb += ((address >> tsb_hash_shift) &
319                 (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL));
320         tag = (address >> 22UL);
321         tsb_insert(tsb, tag, pte_val(pte));
322
323         spin_unlock_irqrestore(&mm->context.lock, flags);
324 }
325
326 void flush_dcache_page(struct page *page)
327 {
328         struct address_space *mapping;
329         int this_cpu;
330
331         if (tlb_type == hypervisor)
332                 return;
333
334         /* Do not bother with the expensive D-cache flush if it
335          * is merely the zero page.  The 'bigcore' testcase in GDB
336          * causes this case to run millions of times.
337          */
338         if (page == ZERO_PAGE(0))
339                 return;
340
341         this_cpu = get_cpu();
342
343         mapping = page_mapping(page);
344         if (mapping && !mapping_mapped(mapping)) {
345                 int dirty = test_bit(PG_dcache_dirty, &page->flags);
346                 if (dirty) {
347                         int dirty_cpu = dcache_dirty_cpu(page);
348
349                         if (dirty_cpu == this_cpu)
350                                 goto out;
351                         smp_flush_dcache_page_impl(page, dirty_cpu);
352                 }
353                 set_dcache_dirty(page, this_cpu);
354         } else {
355                 /* We could delay the flush for the !page_mapping
356                  * case too.  But that case is for exec env/arg
357                  * pages and those are %99 certainly going to get
358                  * faulted into the tlb (and thus flushed) anyways.
359                  */
360                 flush_dcache_page_impl(page);
361         }
362
363 out:
364         put_cpu();
365 }
366
367 void __kprobes flush_icache_range(unsigned long start, unsigned long end)
368 {
369         /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
370         if (tlb_type == spitfire) {
371                 unsigned long kaddr;
372
373                 /* This code only runs on Spitfire cpus so this is
374                  * why we can assume _PAGE_PADDR_4U.
375                  */
376                 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE) {
377                         unsigned long paddr, mask = _PAGE_PADDR_4U;
378
379                         if (kaddr >= PAGE_OFFSET)
380                                 paddr = kaddr & mask;
381                         else {
382                                 pgd_t *pgdp = pgd_offset_k(kaddr);
383                                 pud_t *pudp = pud_offset(pgdp, kaddr);
384                                 pmd_t *pmdp = pmd_offset(pudp, kaddr);
385                                 pte_t *ptep = pte_offset_kernel(pmdp, kaddr);
386
387                                 paddr = pte_val(*ptep) & mask;
388                         }
389                         __flush_icache_page(paddr);
390                 }
391         }
392 }
393
394 void show_mem(void)
395 {
396         unsigned long total = 0, reserved = 0;
397         unsigned long shared = 0, cached = 0;
398         pg_data_t *pgdat;
399
400         printk(KERN_INFO "Mem-info:\n");
401         show_free_areas();
402         printk(KERN_INFO "Free swap:       %6ldkB\n",
403                nr_swap_pages << (PAGE_SHIFT-10));
404         for_each_online_pgdat(pgdat) {
405                 unsigned long i, flags;
406
407                 pgdat_resize_lock(pgdat, &flags);
408                 for (i = 0; i < pgdat->node_spanned_pages; i++) {
409                         struct page *page = pgdat_page_nr(pgdat, i);
410                         total++;
411                         if (PageReserved(page))
412                                 reserved++;
413                         else if (PageSwapCache(page))
414                                 cached++;
415                         else if (page_count(page))
416                                 shared += page_count(page) - 1;
417                 }
418                 pgdat_resize_unlock(pgdat, &flags);
419         }
420
421         printk(KERN_INFO "%lu pages of RAM\n", total);
422         printk(KERN_INFO "%lu reserved pages\n", reserved);
423         printk(KERN_INFO "%lu pages shared\n", shared);
424         printk(KERN_INFO "%lu pages swap cached\n", cached);
425
426         printk(KERN_INFO "%lu pages dirty\n",
427                global_page_state(NR_FILE_DIRTY));
428         printk(KERN_INFO "%lu pages writeback\n",
429                global_page_state(NR_WRITEBACK));
430         printk(KERN_INFO "%lu pages mapped\n",
431                global_page_state(NR_FILE_MAPPED));
432         printk(KERN_INFO "%lu pages slab\n",
433                 global_page_state(NR_SLAB_RECLAIMABLE) +
434                 global_page_state(NR_SLAB_UNRECLAIMABLE));
435         printk(KERN_INFO "%lu pages pagetables\n",
436                global_page_state(NR_PAGETABLE));
437 }
438
439 void mmu_info(struct seq_file *m)
440 {
441         if (tlb_type == cheetah)
442                 seq_printf(m, "MMU Type\t: Cheetah\n");
443         else if (tlb_type == cheetah_plus)
444                 seq_printf(m, "MMU Type\t: Cheetah+\n");
445         else if (tlb_type == spitfire)
446                 seq_printf(m, "MMU Type\t: Spitfire\n");
447         else if (tlb_type == hypervisor)
448                 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
449         else
450                 seq_printf(m, "MMU Type\t: ???\n");
451
452 #ifdef CONFIG_DEBUG_DCFLUSH
453         seq_printf(m, "DCPageFlushes\t: %d\n",
454                    atomic_read(&dcpage_flushes));
455 #ifdef CONFIG_SMP
456         seq_printf(m, "DCPageFlushesXC\t: %d\n",
457                    atomic_read(&dcpage_flushes_xcall));
458 #endif /* CONFIG_SMP */
459 #endif /* CONFIG_DEBUG_DCFLUSH */
460 }
461
462 struct linux_prom_translation {
463         unsigned long virt;
464         unsigned long size;
465         unsigned long data;
466 };
467
468 /* Exported for kernel TLB miss handling in ktlb.S */
469 struct linux_prom_translation prom_trans[512] __read_mostly;
470 unsigned int prom_trans_ents __read_mostly;
471
472 /* Exported for SMP bootup purposes. */
473 unsigned long kern_locked_tte_data;
474
475 /* The obp translations are saved based on 8k pagesize, since obp can
476  * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
477  * HI_OBP_ADDRESS range are handled in ktlb.S.
478  */
479 static inline int in_obp_range(unsigned long vaddr)
480 {
481         return (vaddr >= LOW_OBP_ADDRESS &&
482                 vaddr < HI_OBP_ADDRESS);
483 }
484
485 static int cmp_ptrans(const void *a, const void *b)
486 {
487         const struct linux_prom_translation *x = a, *y = b;
488
489         if (x->virt > y->virt)
490                 return 1;
491         if (x->virt < y->virt)
492                 return -1;
493         return 0;
494 }
495
496 /* Read OBP translations property into 'prom_trans[]'.  */
497 static void __init read_obp_translations(void)
498 {
499         int n, node, ents, first, last, i;
500
501         node = prom_finddevice("/virtual-memory");
502         n = prom_getproplen(node, "translations");
503         if (unlikely(n == 0 || n == -1)) {
504                 prom_printf("prom_mappings: Couldn't get size.\n");
505                 prom_halt();
506         }
507         if (unlikely(n > sizeof(prom_trans))) {
508                 prom_printf("prom_mappings: Size %Zd is too big.\n", n);
509                 prom_halt();
510         }
511
512         if ((n = prom_getproperty(node, "translations",
513                                   (char *)&prom_trans[0],
514                                   sizeof(prom_trans))) == -1) {
515                 prom_printf("prom_mappings: Couldn't get property.\n");
516                 prom_halt();
517         }
518
519         n = n / sizeof(struct linux_prom_translation);
520
521         ents = n;
522
523         sort(prom_trans, ents, sizeof(struct linux_prom_translation),
524              cmp_ptrans, NULL);
525
526         /* Now kick out all the non-OBP entries.  */
527         for (i = 0; i < ents; i++) {
528                 if (in_obp_range(prom_trans[i].virt))
529                         break;
530         }
531         first = i;
532         for (; i < ents; i++) {
533                 if (!in_obp_range(prom_trans[i].virt))
534                         break;
535         }
536         last = i;
537
538         for (i = 0; i < (last - first); i++) {
539                 struct linux_prom_translation *src = &prom_trans[i + first];
540                 struct linux_prom_translation *dest = &prom_trans[i];
541
542                 *dest = *src;
543         }
544         for (; i < ents; i++) {
545                 struct linux_prom_translation *dest = &prom_trans[i];
546                 dest->virt = dest->size = dest->data = 0x0UL;
547         }
548
549         prom_trans_ents = last - first;
550
551         if (tlb_type == spitfire) {
552                 /* Clear diag TTE bits. */
553                 for (i = 0; i < prom_trans_ents; i++)
554                         prom_trans[i].data &= ~0x0003fe0000000000UL;
555         }
556 }
557
558 static void __init hypervisor_tlb_lock(unsigned long vaddr,
559                                        unsigned long pte,
560                                        unsigned long mmu)
561 {
562         unsigned long ret = sun4v_mmu_map_perm_addr(vaddr, 0, pte, mmu);
563
564         if (ret != 0) {
565                 prom_printf("hypervisor_tlb_lock[%lx:%lx:%lx:%lx]: "
566                             "errors with %lx\n", vaddr, 0, pte, mmu, ret);
567                 prom_halt();
568         }
569 }
570
571 static unsigned long kern_large_tte(unsigned long paddr);
572
573 static void __init remap_kernel(void)
574 {
575         unsigned long phys_page, tte_vaddr, tte_data;
576         int i, tlb_ent = sparc64_highest_locked_tlbent();
577
578         tte_vaddr = (unsigned long) KERNBASE;
579         phys_page = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
580         tte_data = kern_large_tte(phys_page);
581
582         kern_locked_tte_data = tte_data;
583
584         /* Now lock us into the TLBs via Hypervisor or OBP. */
585         if (tlb_type == hypervisor) {
586                 for (i = 0; i < num_kernel_image_mappings; i++) {
587                         hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
588                         hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
589                         tte_vaddr += 0x400000;
590                         tte_data += 0x400000;
591                 }
592         } else {
593                 for (i = 0; i < num_kernel_image_mappings; i++) {
594                         prom_dtlb_load(tlb_ent - i, tte_data, tte_vaddr);
595                         prom_itlb_load(tlb_ent - i, tte_data, tte_vaddr);
596                         tte_vaddr += 0x400000;
597                         tte_data += 0x400000;
598                 }
599                 sparc64_highest_unlocked_tlb_ent = tlb_ent - i;
600         }
601         if (tlb_type == cheetah_plus) {
602                 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
603                                             CTX_CHEETAH_PLUS_NUC);
604                 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
605                 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
606         }
607 }
608
609
610 static void __init inherit_prom_mappings(void)
611 {
612         read_obp_translations();
613
614         /* Now fixup OBP's idea about where we really are mapped. */
615         printk("Remapping the kernel... ");
616         remap_kernel();
617         printk("done.\n");
618 }
619
620 void prom_world(int enter)
621 {
622         if (!enter)
623                 set_fs((mm_segment_t) { get_thread_current_ds() });
624
625         __asm__ __volatile__("flushw");
626 }
627
628 void __flush_dcache_range(unsigned long start, unsigned long end)
629 {
630         unsigned long va;
631
632         if (tlb_type == spitfire) {
633                 int n = 0;
634
635                 for (va = start; va < end; va += 32) {
636                         spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
637                         if (++n >= 512)
638                                 break;
639                 }
640         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
641                 start = __pa(start);
642                 end = __pa(end);
643                 for (va = start; va < end; va += 32)
644                         __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
645                                              "membar #Sync"
646                                              : /* no outputs */
647                                              : "r" (va),
648                                                "i" (ASI_DCACHE_INVALIDATE));
649         }
650 }
651
652 /* get_new_mmu_context() uses "cache + 1".  */
653 DEFINE_SPINLOCK(ctx_alloc_lock);
654 unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
655 #define MAX_CTX_NR      (1UL << CTX_NR_BITS)
656 #define CTX_BMAP_SLOTS  BITS_TO_LONGS(MAX_CTX_NR)
657 DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR);
658
659 /* Caller does TLB context flushing on local CPU if necessary.
660  * The caller also ensures that CTX_VALID(mm->context) is false.
661  *
662  * We must be careful about boundary cases so that we never
663  * let the user have CTX 0 (nucleus) or we ever use a CTX
664  * version of zero (and thus NO_CONTEXT would not be caught
665  * by version mis-match tests in mmu_context.h).
666  *
667  * Always invoked with interrupts disabled.
668  */
669 void get_new_mmu_context(struct mm_struct *mm)
670 {
671         unsigned long ctx, new_ctx;
672         unsigned long orig_pgsz_bits;
673         unsigned long flags;
674         int new_version;
675
676         spin_lock_irqsave(&ctx_alloc_lock, flags);
677         orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
678         ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
679         new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
680         new_version = 0;
681         if (new_ctx >= (1 << CTX_NR_BITS)) {
682                 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
683                 if (new_ctx >= ctx) {
684                         int i;
685                         new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
686                                 CTX_FIRST_VERSION;
687                         if (new_ctx == 1)
688                                 new_ctx = CTX_FIRST_VERSION;
689
690                         /* Don't call memset, for 16 entries that's just
691                          * plain silly...
692                          */
693                         mmu_context_bmap[0] = 3;
694                         mmu_context_bmap[1] = 0;
695                         mmu_context_bmap[2] = 0;
696                         mmu_context_bmap[3] = 0;
697                         for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
698                                 mmu_context_bmap[i + 0] = 0;
699                                 mmu_context_bmap[i + 1] = 0;
700                                 mmu_context_bmap[i + 2] = 0;
701                                 mmu_context_bmap[i + 3] = 0;
702                         }
703                         new_version = 1;
704                         goto out;
705                 }
706         }
707         mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
708         new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
709 out:
710         tlb_context_cache = new_ctx;
711         mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
712         spin_unlock_irqrestore(&ctx_alloc_lock, flags);
713
714         if (unlikely(new_version))
715                 smp_new_mmu_context_version();
716 }
717
718 /* Find a free area for the bootmem map, avoiding the kernel image
719  * and the initial ramdisk.
720  */
721 static unsigned long __init choose_bootmap_pfn(unsigned long start_pfn,
722                                                unsigned long end_pfn)
723 {
724         unsigned long avoid_start, avoid_end, bootmap_size;
725         int i;
726
727         bootmap_size = bootmem_bootmap_pages(end_pfn - start_pfn);
728         bootmap_size <<= PAGE_SHIFT;
729
730         avoid_start = avoid_end = 0;
731 #ifdef CONFIG_BLK_DEV_INITRD
732         avoid_start = initrd_start;
733         avoid_end = PAGE_ALIGN(initrd_end);
734 #endif
735
736         for (i = 0; i < pavail_ents; i++) {
737                 unsigned long start, end;
738
739                 start = pavail[i].phys_addr;
740                 end = start + pavail[i].reg_size;
741
742                 while (start < end) {
743                         if (start >= kern_base &&
744                             start < PAGE_ALIGN(kern_base + kern_size)) {
745                                 start = PAGE_ALIGN(kern_base + kern_size);
746                                 continue;
747                         }
748                         if (start >= avoid_start && start < avoid_end) {
749                                 start = avoid_end;
750                                 continue;
751                         }
752
753                         if ((end - start) < bootmap_size)
754                                 break;
755
756                         if (start < kern_base &&
757                             (start + bootmap_size) > kern_base) {
758                                 start = PAGE_ALIGN(kern_base + kern_size);
759                                 continue;
760                         }
761
762                         if (start < avoid_start &&
763                             (start + bootmap_size) > avoid_start) {
764                                 start = avoid_end;
765                                 continue;
766                         }
767
768                         /* OK, it doesn't overlap anything, use it.  */
769                         return start >> PAGE_SHIFT;
770                 }
771         }
772
773         prom_printf("Cannot find free area for bootmap, aborting.\n");
774         prom_halt();
775 }
776
777 static void __init trim_pavail(unsigned long *cur_size_p,
778                                unsigned long *end_of_phys_p)
779 {
780         unsigned long to_trim = *cur_size_p - cmdline_memory_size;
781         unsigned long avoid_start, avoid_end;
782         int i;
783
784         to_trim = PAGE_ALIGN(to_trim);
785
786         avoid_start = avoid_end = 0;
787 #ifdef CONFIG_BLK_DEV_INITRD
788         avoid_start = initrd_start;
789         avoid_end = PAGE_ALIGN(initrd_end);
790 #endif
791
792         /* Trim some pavail[] entries in order to satisfy the
793          * requested "mem=xxx" kernel command line specification.
794          *
795          * We must not trim off the kernel image area nor the
796          * initial ramdisk range (if any).  Also, we must not trim
797          * any pavail[] entry down to zero in order to preserve
798          * the invariant that all pavail[] entries have a non-zero
799          * size which is assumed by all of the code in here.
800          */
801         for (i = 0; i < pavail_ents; i++) {
802                 unsigned long start, end, kern_end;
803                 unsigned long trim_low, trim_high, n;
804
805                 kern_end = PAGE_ALIGN(kern_base + kern_size);
806
807                 trim_low = start = pavail[i].phys_addr;
808                 trim_high = end = start + pavail[i].reg_size;
809
810                 if (kern_base >= start &&
811                     kern_base < end) {
812                         trim_low = kern_base;
813                         if (kern_end >= end)
814                                 continue;
815                 }
816                 if (kern_end >= start &&
817                     kern_end < end) {
818                         trim_high = kern_end;
819                 }
820                 if (avoid_start &&
821                     avoid_start >= start &&
822                     avoid_start < end) {
823                         if (trim_low > avoid_start)
824                                 trim_low = avoid_start;
825                         if (avoid_end >= end)
826                                 continue;
827                 }
828                 if (avoid_end &&
829                     avoid_end >= start &&
830                     avoid_end < end) {
831                         if (trim_high < avoid_end)
832                                 trim_high = avoid_end;
833                 }
834
835                 if (trim_high <= trim_low)
836                         continue;
837
838                 if (trim_low == start && trim_high == end) {
839                         /* Whole chunk is available for trimming.
840                          * Trim all except one page, in order to keep
841                          * entry non-empty.
842                          */
843                         n = (end - start) - PAGE_SIZE;
844                         if (n > to_trim)
845                                 n = to_trim;
846
847                         if (n) {
848                                 pavail[i].phys_addr += n;
849                                 pavail[i].reg_size -= n;
850                                 to_trim -= n;
851                         }
852                 } else {
853                         n = (trim_low - start);
854                         if (n > to_trim)
855                                 n = to_trim;
856
857                         if (n) {
858                                 pavail[i].phys_addr += n;
859                                 pavail[i].reg_size -= n;
860                                 to_trim -= n;
861                         }
862                         if (to_trim) {
863                                 n = end - trim_high;
864                                 if (n > to_trim)
865                                         n = to_trim;
866                                 if (n) {
867                                         pavail[i].reg_size -= n;
868                                         to_trim -= n;
869                                 }
870                         }
871                 }
872
873                 if (!to_trim)
874                         break;
875         }
876
877         /* Recalculate.  */
878         *cur_size_p = 0UL;
879         for (i = 0; i < pavail_ents; i++) {
880                 *end_of_phys_p = pavail[i].phys_addr +
881                         pavail[i].reg_size;
882                 *cur_size_p += pavail[i].reg_size;
883         }
884 }
885
886 /* About pages_avail, this is the value we will use to calculate
887  * the zholes_size[] argument given to free_area_init_node().  The
888  * page allocator uses this to calculate nr_kernel_pages,
889  * nr_all_pages and zone->present_pages.  On NUMA it is used
890  * to calculate zone->min_unmapped_pages and zone->min_slab_pages.
891  *
892  * So this number should really be set to what the page allocator
893  * actually ends up with.  This means:
894  * 1) It should include bootmem map pages, we'll release those.
895  * 2) It should not include the kernel image, except for the
896  *    __init sections which we will also release.
897  * 3) It should include the initrd image, since we'll release
898  *    that too.
899  */
900 static unsigned long __init bootmem_init(unsigned long *pages_avail,
901                                          unsigned long phys_base)
902 {
903         unsigned long bootmap_size, end_pfn;
904         unsigned long end_of_phys_memory = 0UL;
905         unsigned long bootmap_pfn, bytes_avail, size;
906         int i;
907
908         bytes_avail = 0UL;
909         for (i = 0; i < pavail_ents; i++) {
910                 end_of_phys_memory = pavail[i].phys_addr +
911                         pavail[i].reg_size;
912                 bytes_avail += pavail[i].reg_size;
913         }
914
915         /* Determine the location of the initial ramdisk before trying
916          * to honor the "mem=xxx" command line argument.  We must know
917          * where the kernel image and the ramdisk image are so that we
918          * do not trim those two areas from the physical memory map.
919          */
920
921 #ifdef CONFIG_BLK_DEV_INITRD
922         /* Now have to check initial ramdisk, so that bootmap does not overwrite it */
923         if (sparc_ramdisk_image || sparc_ramdisk_image64) {
924                 unsigned long ramdisk_image = sparc_ramdisk_image ?
925                         sparc_ramdisk_image : sparc_ramdisk_image64;
926                 ramdisk_image -= KERNBASE;
927                 initrd_start = ramdisk_image + phys_base;
928                 initrd_end = initrd_start + sparc_ramdisk_size;
929                 if (initrd_end > end_of_phys_memory) {
930                         printk(KERN_CRIT "initrd extends beyond end of memory "
931                                          "(0x%016lx > 0x%016lx)\ndisabling initrd\n",
932                                initrd_end, end_of_phys_memory);
933                         initrd_start = 0;
934                         initrd_end = 0;
935                 }
936         }
937 #endif  
938
939         if (cmdline_memory_size &&
940             bytes_avail > cmdline_memory_size)
941                 trim_pavail(&bytes_avail,
942                             &end_of_phys_memory);
943
944         *pages_avail = bytes_avail >> PAGE_SHIFT;
945
946         end_pfn = end_of_phys_memory >> PAGE_SHIFT;
947
948         /* Initialize the boot-time allocator. */
949         max_pfn = max_low_pfn = end_pfn;
950         min_low_pfn = (phys_base >> PAGE_SHIFT);
951
952         bootmap_pfn = choose_bootmap_pfn(min_low_pfn, end_pfn);
953
954         bootmap_size = init_bootmem_node(NODE_DATA(0), bootmap_pfn,
955                                          min_low_pfn, end_pfn);
956
957         /* Now register the available physical memory with the
958          * allocator.
959          */
960         for (i = 0; i < pavail_ents; i++)
961                 free_bootmem(pavail[i].phys_addr, pavail[i].reg_size);
962
963 #ifdef CONFIG_BLK_DEV_INITRD
964         if (initrd_start) {
965                 size = initrd_end - initrd_start;
966
967                 /* Reserve the initrd image area. */
968                 reserve_bootmem(initrd_start, size, BOOTMEM_DEFAULT);
969
970                 initrd_start += PAGE_OFFSET;
971                 initrd_end += PAGE_OFFSET;
972         }
973 #endif
974         /* Reserve the kernel text/data/bss. */
975         reserve_bootmem(kern_base, kern_size, BOOTMEM_DEFAULT);
976         *pages_avail -= PAGE_ALIGN(kern_size) >> PAGE_SHIFT;
977
978         /* Add back in the initmem pages. */
979         size = ((unsigned long)(__init_end) & PAGE_MASK) -
980                 PAGE_ALIGN((unsigned long)__init_begin);
981         *pages_avail += size >> PAGE_SHIFT;
982
983         /* Reserve the bootmem map.   We do not account for it
984          * in pages_avail because we will release that memory
985          * in free_all_bootmem.
986          */
987         size = bootmap_size;
988         reserve_bootmem((bootmap_pfn << PAGE_SHIFT), size, BOOTMEM_DEFAULT);
989
990         for (i = 0; i < pavail_ents; i++) {
991                 unsigned long start_pfn, end_pfn;
992
993                 start_pfn = pavail[i].phys_addr >> PAGE_SHIFT;
994                 end_pfn = (start_pfn + (pavail[i].reg_size >> PAGE_SHIFT));
995                 memory_present(0, start_pfn, end_pfn);
996         }
997
998         sparse_init();
999
1000         return end_pfn;
1001 }
1002
1003 static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
1004 static int pall_ents __initdata;
1005
1006 #ifdef CONFIG_DEBUG_PAGEALLOC
1007 static unsigned long __ref kernel_map_range(unsigned long pstart,
1008                                             unsigned long pend, pgprot_t prot)
1009 {
1010         unsigned long vstart = PAGE_OFFSET + pstart;
1011         unsigned long vend = PAGE_OFFSET + pend;
1012         unsigned long alloc_bytes = 0UL;
1013
1014         if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
1015                 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
1016                             vstart, vend);
1017                 prom_halt();
1018         }
1019
1020         while (vstart < vend) {
1021                 unsigned long this_end, paddr = __pa(vstart);
1022                 pgd_t *pgd = pgd_offset_k(vstart);
1023                 pud_t *pud;
1024                 pmd_t *pmd;
1025                 pte_t *pte;
1026
1027                 pud = pud_offset(pgd, vstart);
1028                 if (pud_none(*pud)) {
1029                         pmd_t *new;
1030
1031                         new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1032                         alloc_bytes += PAGE_SIZE;
1033                         pud_populate(&init_mm, pud, new);
1034                 }
1035
1036                 pmd = pmd_offset(pud, vstart);
1037                 if (!pmd_present(*pmd)) {
1038                         pte_t *new;
1039
1040                         new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1041                         alloc_bytes += PAGE_SIZE;
1042                         pmd_populate_kernel(&init_mm, pmd, new);
1043                 }
1044
1045                 pte = pte_offset_kernel(pmd, vstart);
1046                 this_end = (vstart + PMD_SIZE) & PMD_MASK;
1047                 if (this_end > vend)
1048                         this_end = vend;
1049
1050                 while (vstart < this_end) {
1051                         pte_val(*pte) = (paddr | pgprot_val(prot));
1052
1053                         vstart += PAGE_SIZE;
1054                         paddr += PAGE_SIZE;
1055                         pte++;
1056                 }
1057         }
1058
1059         return alloc_bytes;
1060 }
1061
1062 extern unsigned int kvmap_linear_patch[1];
1063 #endif /* CONFIG_DEBUG_PAGEALLOC */
1064
1065 static void __init mark_kpte_bitmap(unsigned long start, unsigned long end)
1066 {
1067         const unsigned long shift_256MB = 28;
1068         const unsigned long mask_256MB = ((1UL << shift_256MB) - 1UL);
1069         const unsigned long size_256MB = (1UL << shift_256MB);
1070
1071         while (start < end) {
1072                 long remains;
1073
1074                 remains = end - start;
1075                 if (remains < size_256MB)
1076                         break;
1077
1078                 if (start & mask_256MB) {
1079                         start = (start + size_256MB) & ~mask_256MB;
1080                         continue;
1081                 }
1082
1083                 while (remains >= size_256MB) {
1084                         unsigned long index = start >> shift_256MB;
1085
1086                         __set_bit(index, kpte_linear_bitmap);
1087
1088                         start += size_256MB;
1089                         remains -= size_256MB;
1090                 }
1091         }
1092 }
1093
1094 static void __init init_kpte_bitmap(void)
1095 {
1096         unsigned long i;
1097
1098         for (i = 0; i < pall_ents; i++) {
1099                 unsigned long phys_start, phys_end;
1100
1101                 phys_start = pall[i].phys_addr;
1102                 phys_end = phys_start + pall[i].reg_size;
1103
1104                 mark_kpte_bitmap(phys_start, phys_end);
1105         }
1106 }
1107
1108 static void __init kernel_physical_mapping_init(void)
1109 {
1110 #ifdef CONFIG_DEBUG_PAGEALLOC
1111         unsigned long i, mem_alloced = 0UL;
1112
1113         for (i = 0; i < pall_ents; i++) {
1114                 unsigned long phys_start, phys_end;
1115
1116                 phys_start = pall[i].phys_addr;
1117                 phys_end = phys_start + pall[i].reg_size;
1118
1119                 mem_alloced += kernel_map_range(phys_start, phys_end,
1120                                                 PAGE_KERNEL);
1121         }
1122
1123         printk("Allocated %ld bytes for kernel page tables.\n",
1124                mem_alloced);
1125
1126         kvmap_linear_patch[0] = 0x01000000; /* nop */
1127         flushi(&kvmap_linear_patch[0]);
1128
1129         __flush_tlb_all();
1130 #endif
1131 }
1132
1133 #ifdef CONFIG_DEBUG_PAGEALLOC
1134 void kernel_map_pages(struct page *page, int numpages, int enable)
1135 {
1136         unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1137         unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1138
1139         kernel_map_range(phys_start, phys_end,
1140                          (enable ? PAGE_KERNEL : __pgprot(0)));
1141
1142         flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1143                                PAGE_OFFSET + phys_end);
1144
1145         /* we should perform an IPI and flush all tlbs,
1146          * but that can deadlock->flush only current cpu.
1147          */
1148         __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1149                                  PAGE_OFFSET + phys_end);
1150 }
1151 #endif
1152
1153 unsigned long __init find_ecache_flush_span(unsigned long size)
1154 {
1155         int i;
1156
1157         for (i = 0; i < pavail_ents; i++) {
1158                 if (pavail[i].reg_size >= size)
1159                         return pavail[i].phys_addr;
1160         }
1161
1162         return ~0UL;
1163 }
1164
1165 static void __init tsb_phys_patch(void)
1166 {
1167         struct tsb_ldquad_phys_patch_entry *pquad;
1168         struct tsb_phys_patch_entry *p;
1169
1170         pquad = &__tsb_ldquad_phys_patch;
1171         while (pquad < &__tsb_ldquad_phys_patch_end) {
1172                 unsigned long addr = pquad->addr;
1173
1174                 if (tlb_type == hypervisor)
1175                         *(unsigned int *) addr = pquad->sun4v_insn;
1176                 else
1177                         *(unsigned int *) addr = pquad->sun4u_insn;
1178                 wmb();
1179                 __asm__ __volatile__("flush     %0"
1180                                      : /* no outputs */
1181                                      : "r" (addr));
1182
1183                 pquad++;
1184         }
1185
1186         p = &__tsb_phys_patch;
1187         while (p < &__tsb_phys_patch_end) {
1188                 unsigned long addr = p->addr;
1189
1190                 *(unsigned int *) addr = p->insn;
1191                 wmb();
1192                 __asm__ __volatile__("flush     %0"
1193                                      : /* no outputs */
1194                                      : "r" (addr));
1195
1196                 p++;
1197         }
1198 }
1199
1200 /* Don't mark as init, we give this to the Hypervisor.  */
1201 #ifndef CONFIG_DEBUG_PAGEALLOC
1202 #define NUM_KTSB_DESCR  2
1203 #else
1204 #define NUM_KTSB_DESCR  1
1205 #endif
1206 static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR];
1207 extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
1208
1209 static void __init sun4v_ktsb_init(void)
1210 {
1211         unsigned long ktsb_pa;
1212
1213         /* First KTSB for PAGE_SIZE mappings.  */
1214         ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1215
1216         switch (PAGE_SIZE) {
1217         case 8 * 1024:
1218         default:
1219                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
1220                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
1221                 break;
1222
1223         case 64 * 1024:
1224                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
1225                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
1226                 break;
1227
1228         case 512 * 1024:
1229                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
1230                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
1231                 break;
1232
1233         case 4 * 1024 * 1024:
1234                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
1235                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
1236                 break;
1237         };
1238
1239         ktsb_descr[0].assoc = 1;
1240         ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
1241         ktsb_descr[0].ctx_idx = 0;
1242         ktsb_descr[0].tsb_base = ktsb_pa;
1243         ktsb_descr[0].resv = 0;
1244
1245 #ifndef CONFIG_DEBUG_PAGEALLOC
1246         /* Second KTSB for 4MB/256MB mappings.  */
1247         ktsb_pa = (kern_base +
1248                    ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1249
1250         ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB;
1251         ktsb_descr[1].pgsz_mask = (HV_PGSZ_MASK_4MB |
1252                                    HV_PGSZ_MASK_256MB);
1253         ktsb_descr[1].assoc = 1;
1254         ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES;
1255         ktsb_descr[1].ctx_idx = 0;
1256         ktsb_descr[1].tsb_base = ktsb_pa;
1257         ktsb_descr[1].resv = 0;
1258 #endif
1259 }
1260
1261 void __cpuinit sun4v_ktsb_register(void)
1262 {
1263         unsigned long pa, ret;
1264
1265         pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);
1266
1267         ret = sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR, pa);
1268         if (ret != 0) {
1269                 prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: "
1270                             "errors with %lx\n", pa, ret);
1271                 prom_halt();
1272         }
1273 }
1274
1275 /* paging_init() sets up the page tables */
1276
1277 extern void central_probe(void);
1278
1279 static unsigned long last_valid_pfn;
1280 pgd_t swapper_pg_dir[2048];
1281
1282 static void sun4u_pgprot_init(void);
1283 static void sun4v_pgprot_init(void);
1284
1285 /* Dummy function */
1286 void __init setup_per_cpu_areas(void)
1287 {
1288 }
1289
1290 void __init paging_init(void)
1291 {
1292         unsigned long end_pfn, pages_avail, shift, phys_base;
1293         unsigned long real_end, i;
1294
1295         /* These build time checkes make sure that the dcache_dirty_cpu()
1296          * page->flags usage will work.
1297          *
1298          * When a page gets marked as dcache-dirty, we store the
1299          * cpu number starting at bit 32 in the page->flags.  Also,
1300          * functions like clear_dcache_dirty_cpu use the cpu mask
1301          * in 13-bit signed-immediate instruction fields.
1302          */
1303         BUILD_BUG_ON(FLAGS_RESERVED != 32);
1304         BUILD_BUG_ON(SECTIONS_WIDTH + NODES_WIDTH + ZONES_WIDTH +
1305                      ilog2(roundup_pow_of_two(NR_CPUS)) > FLAGS_RESERVED);
1306         BUILD_BUG_ON(NR_CPUS > 4096);
1307
1308         kern_base = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
1309         kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
1310
1311         sstate_booting();
1312
1313         /* Invalidate both kernel TSBs.  */
1314         memset(swapper_tsb, 0x40, sizeof(swapper_tsb));
1315 #ifndef CONFIG_DEBUG_PAGEALLOC
1316         memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
1317 #endif
1318
1319         if (tlb_type == hypervisor)
1320                 sun4v_pgprot_init();
1321         else
1322                 sun4u_pgprot_init();
1323
1324         if (tlb_type == cheetah_plus ||
1325             tlb_type == hypervisor)
1326                 tsb_phys_patch();
1327
1328         if (tlb_type == hypervisor) {
1329                 sun4v_patch_tlb_handlers();
1330                 sun4v_ktsb_init();
1331         }
1332
1333         /* Find available physical memory... */
1334         read_obp_memory("available", &pavail[0], &pavail_ents);
1335
1336         phys_base = 0xffffffffffffffffUL;
1337         for (i = 0; i < pavail_ents; i++)
1338                 phys_base = min(phys_base, pavail[i].phys_addr);
1339
1340         set_bit(0, mmu_context_bmap);
1341
1342         shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
1343
1344         real_end = (unsigned long)_end;
1345         num_kernel_image_mappings = DIV_ROUND_UP(real_end - KERNBASE, 1 << 22);
1346         printk("Kernel: Using %d locked TLB entries for main kernel image.\n",
1347                num_kernel_image_mappings);
1348
1349         /* Set kernel pgd to upper alias so physical page computations
1350          * work.
1351          */
1352         init_mm.pgd += ((shift) / (sizeof(pgd_t)));
1353         
1354         memset(swapper_low_pmd_dir, 0, sizeof(swapper_low_pmd_dir));
1355
1356         /* Now can init the kernel/bad page tables. */
1357         pud_set(pud_offset(&swapper_pg_dir[0], 0),
1358                 swapper_low_pmd_dir + (shift / sizeof(pgd_t)));
1359         
1360         inherit_prom_mappings();
1361         
1362         read_obp_memory("reg", &pall[0], &pall_ents);
1363
1364         init_kpte_bitmap();
1365
1366         /* Ok, we can use our TLB miss and window trap handlers safely.  */
1367         setup_tba();
1368
1369         __flush_tlb_all();
1370
1371         if (tlb_type == hypervisor)
1372                 sun4v_ktsb_register();
1373
1374         /* Setup bootmem... */
1375         pages_avail = 0;
1376         last_valid_pfn = end_pfn = bootmem_init(&pages_avail, phys_base);
1377
1378         max_mapnr = last_valid_pfn;
1379
1380         kernel_physical_mapping_init();
1381
1382         real_setup_per_cpu_areas();
1383
1384         prom_build_devicetree();
1385
1386         if (tlb_type == hypervisor)
1387                 sun4v_mdesc_init();
1388
1389         {
1390                 unsigned long zones_size[MAX_NR_ZONES];
1391                 unsigned long zholes_size[MAX_NR_ZONES];
1392                 int znum;
1393
1394                 for (znum = 0; znum < MAX_NR_ZONES; znum++)
1395                         zones_size[znum] = zholes_size[znum] = 0;
1396
1397                 zones_size[ZONE_NORMAL] = end_pfn;
1398                 zholes_size[ZONE_NORMAL] = end_pfn - pages_avail;
1399
1400                 free_area_init_node(0, &contig_page_data, zones_size,
1401                                     __pa(PAGE_OFFSET) >> PAGE_SHIFT,
1402                                     zholes_size);
1403         }
1404
1405         printk("Booting Linux...\n");
1406
1407         central_probe();
1408         cpu_probe();
1409 }
1410
1411 static void __init taint_real_pages(void)
1412 {
1413         int i;
1414
1415         read_obp_memory("available", &pavail_rescan[0], &pavail_rescan_ents);
1416
1417         /* Find changes discovered in the physmem available rescan and
1418          * reserve the lost portions in the bootmem maps.
1419          */
1420         for (i = 0; i < pavail_ents; i++) {
1421                 unsigned long old_start, old_end;
1422
1423                 old_start = pavail[i].phys_addr;
1424                 old_end = old_start +
1425                         pavail[i].reg_size;
1426                 while (old_start < old_end) {
1427                         int n;
1428
1429                         for (n = 0; n < pavail_rescan_ents; n++) {
1430                                 unsigned long new_start, new_end;
1431
1432                                 new_start = pavail_rescan[n].phys_addr;
1433                                 new_end = new_start +
1434                                         pavail_rescan[n].reg_size;
1435
1436                                 if (new_start <= old_start &&
1437                                     new_end >= (old_start + PAGE_SIZE)) {
1438                                         set_bit(old_start >> 22,
1439                                                 sparc64_valid_addr_bitmap);
1440                                         goto do_next_page;
1441                                 }
1442                         }
1443                         reserve_bootmem(old_start, PAGE_SIZE, BOOTMEM_DEFAULT);
1444
1445                 do_next_page:
1446                         old_start += PAGE_SIZE;
1447                 }
1448         }
1449 }
1450
1451 int __init page_in_phys_avail(unsigned long paddr)
1452 {
1453         int i;
1454
1455         paddr &= PAGE_MASK;
1456
1457         for (i = 0; i < pavail_rescan_ents; i++) {
1458                 unsigned long start, end;
1459
1460                 start = pavail_rescan[i].phys_addr;
1461                 end = start + pavail_rescan[i].reg_size;
1462
1463                 if (paddr >= start && paddr < end)
1464                         return 1;
1465         }
1466         if (paddr >= kern_base && paddr < (kern_base + kern_size))
1467                 return 1;
1468 #ifdef CONFIG_BLK_DEV_INITRD
1469         if (paddr >= __pa(initrd_start) &&
1470             paddr < __pa(PAGE_ALIGN(initrd_end)))
1471                 return 1;
1472 #endif
1473
1474         return 0;
1475 }
1476
1477 void __init mem_init(void)
1478 {
1479         unsigned long codepages, datapages, initpages;
1480         unsigned long addr, last;
1481         int i;
1482
1483         i = last_valid_pfn >> ((22 - PAGE_SHIFT) + 6);
1484         i += 1;
1485         sparc64_valid_addr_bitmap = (unsigned long *) alloc_bootmem(i << 3);
1486         if (sparc64_valid_addr_bitmap == NULL) {
1487                 prom_printf("mem_init: Cannot alloc valid_addr_bitmap.\n");
1488                 prom_halt();
1489         }
1490         memset(sparc64_valid_addr_bitmap, 0, i << 3);
1491
1492         addr = PAGE_OFFSET + kern_base;
1493         last = PAGE_ALIGN(kern_size) + addr;
1494         while (addr < last) {
1495                 set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap);
1496                 addr += PAGE_SIZE;
1497         }
1498
1499         taint_real_pages();
1500
1501         high_memory = __va(last_valid_pfn << PAGE_SHIFT);
1502
1503         /* We subtract one to account for the mem_map_zero page
1504          * allocated below.
1505          */
1506         totalram_pages = num_physpages = free_all_bootmem() - 1;
1507
1508         /*
1509          * Set up the zero page, mark it reserved, so that page count
1510          * is not manipulated when freeing the page from user ptes.
1511          */
1512         mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
1513         if (mem_map_zero == NULL) {
1514                 prom_printf("paging_init: Cannot alloc zero page.\n");
1515                 prom_halt();
1516         }
1517         SetPageReserved(mem_map_zero);
1518
1519         codepages = (((unsigned long) _etext) - ((unsigned long) _start));
1520         codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT;
1521         datapages = (((unsigned long) _edata) - ((unsigned long) _etext));
1522         datapages = PAGE_ALIGN(datapages) >> PAGE_SHIFT;
1523         initpages = (((unsigned long) __init_end) - ((unsigned long) __init_begin));
1524         initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT;
1525
1526         printk("Memory: %luk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n",
1527                nr_free_pages() << (PAGE_SHIFT-10),
1528                codepages << (PAGE_SHIFT-10),
1529                datapages << (PAGE_SHIFT-10), 
1530                initpages << (PAGE_SHIFT-10), 
1531                PAGE_OFFSET, (last_valid_pfn << PAGE_SHIFT));
1532
1533         if (tlb_type == cheetah || tlb_type == cheetah_plus)
1534                 cheetah_ecache_flush_init();
1535 }
1536
1537 void free_initmem(void)
1538 {
1539         unsigned long addr, initend;
1540
1541         /*
1542          * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
1543          */
1544         addr = PAGE_ALIGN((unsigned long)(__init_begin));
1545         initend = (unsigned long)(__init_end) & PAGE_MASK;
1546         for (; addr < initend; addr += PAGE_SIZE) {
1547                 unsigned long page;
1548                 struct page *p;
1549
1550                 page = (addr +
1551                         ((unsigned long) __va(kern_base)) -
1552                         ((unsigned long) KERNBASE));
1553                 memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
1554                 p = virt_to_page(page);
1555
1556                 ClearPageReserved(p);
1557                 init_page_count(p);
1558                 __free_page(p);
1559                 num_physpages++;
1560                 totalram_pages++;
1561         }
1562 }
1563
1564 #ifdef CONFIG_BLK_DEV_INITRD
1565 void free_initrd_mem(unsigned long start, unsigned long end)
1566 {
1567         if (start < end)
1568                 printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
1569         for (; start < end; start += PAGE_SIZE) {
1570                 struct page *p = virt_to_page(start);
1571
1572                 ClearPageReserved(p);
1573                 init_page_count(p);
1574                 __free_page(p);
1575                 num_physpages++;
1576                 totalram_pages++;
1577         }
1578 }
1579 #endif
1580
1581 #define _PAGE_CACHE_4U  (_PAGE_CP_4U | _PAGE_CV_4U)
1582 #define _PAGE_CACHE_4V  (_PAGE_CP_4V | _PAGE_CV_4V)
1583 #define __DIRTY_BITS_4U  (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
1584 #define __DIRTY_BITS_4V  (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
1585 #define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
1586 #define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
1587
1588 pgprot_t PAGE_KERNEL __read_mostly;
1589 EXPORT_SYMBOL(PAGE_KERNEL);
1590
1591 pgprot_t PAGE_KERNEL_LOCKED __read_mostly;
1592 pgprot_t PAGE_COPY __read_mostly;
1593
1594 pgprot_t PAGE_SHARED __read_mostly;
1595 EXPORT_SYMBOL(PAGE_SHARED);
1596
1597 pgprot_t PAGE_EXEC __read_mostly;
1598 unsigned long pg_iobits __read_mostly;
1599
1600 unsigned long _PAGE_IE __read_mostly;
1601 EXPORT_SYMBOL(_PAGE_IE);
1602
1603 unsigned long _PAGE_E __read_mostly;
1604 EXPORT_SYMBOL(_PAGE_E);
1605
1606 unsigned long _PAGE_CACHE __read_mostly;
1607 EXPORT_SYMBOL(_PAGE_CACHE);
1608
1609 #ifdef CONFIG_SPARSEMEM_VMEMMAP
1610
1611 #define VMEMMAP_CHUNK_SHIFT     22
1612 #define VMEMMAP_CHUNK           (1UL << VMEMMAP_CHUNK_SHIFT)
1613 #define VMEMMAP_CHUNK_MASK      ~(VMEMMAP_CHUNK - 1UL)
1614 #define VMEMMAP_ALIGN(x)        (((x)+VMEMMAP_CHUNK-1UL)&VMEMMAP_CHUNK_MASK)
1615
1616 #define VMEMMAP_SIZE    ((((1UL << MAX_PHYSADDR_BITS) >> PAGE_SHIFT) * \
1617                           sizeof(struct page *)) >> VMEMMAP_CHUNK_SHIFT)
1618 unsigned long vmemmap_table[VMEMMAP_SIZE];
1619
1620 int __meminit vmemmap_populate(struct page *start, unsigned long nr, int node)
1621 {
1622         unsigned long vstart = (unsigned long) start;
1623         unsigned long vend = (unsigned long) (start + nr);
1624         unsigned long phys_start = (vstart - VMEMMAP_BASE);
1625         unsigned long phys_end = (vend - VMEMMAP_BASE);
1626         unsigned long addr = phys_start & VMEMMAP_CHUNK_MASK;
1627         unsigned long end = VMEMMAP_ALIGN(phys_end);
1628         unsigned long pte_base;
1629
1630         pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4U |
1631                     _PAGE_CP_4U | _PAGE_CV_4U |
1632                     _PAGE_P_4U | _PAGE_W_4U);
1633         if (tlb_type == hypervisor)
1634                 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4V |
1635                             _PAGE_CP_4V | _PAGE_CV_4V |
1636                             _PAGE_P_4V | _PAGE_W_4V);
1637
1638         for (; addr < end; addr += VMEMMAP_CHUNK) {
1639                 unsigned long *vmem_pp =
1640                         vmemmap_table + (addr >> VMEMMAP_CHUNK_SHIFT);
1641                 void *block;
1642
1643                 if (!(*vmem_pp & _PAGE_VALID)) {
1644                         block = vmemmap_alloc_block(1UL << 22, node);
1645                         if (!block)
1646                                 return -ENOMEM;
1647
1648                         *vmem_pp = pte_base | __pa(block);
1649
1650                         printk(KERN_INFO "[%p-%p] page_structs=%lu "
1651                                "node=%d entry=%lu/%lu\n", start, block, nr,
1652                                node,
1653                                addr >> VMEMMAP_CHUNK_SHIFT,
1654                                VMEMMAP_SIZE >> VMEMMAP_CHUNK_SHIFT);
1655                 }
1656         }
1657         return 0;
1658 }
1659 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
1660
1661 static void prot_init_common(unsigned long page_none,
1662                              unsigned long page_shared,
1663                              unsigned long page_copy,
1664                              unsigned long page_readonly,
1665                              unsigned long page_exec_bit)
1666 {
1667         PAGE_COPY = __pgprot(page_copy);
1668         PAGE_SHARED = __pgprot(page_shared);
1669
1670         protection_map[0x0] = __pgprot(page_none);
1671         protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit);
1672         protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit);
1673         protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit);
1674         protection_map[0x4] = __pgprot(page_readonly);
1675         protection_map[0x5] = __pgprot(page_readonly);
1676         protection_map[0x6] = __pgprot(page_copy);
1677         protection_map[0x7] = __pgprot(page_copy);
1678         protection_map[0x8] = __pgprot(page_none);
1679         protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit);
1680         protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit);
1681         protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit);
1682         protection_map[0xc] = __pgprot(page_readonly);
1683         protection_map[0xd] = __pgprot(page_readonly);
1684         protection_map[0xe] = __pgprot(page_shared);
1685         protection_map[0xf] = __pgprot(page_shared);
1686 }
1687
1688 static void __init sun4u_pgprot_init(void)
1689 {
1690         unsigned long page_none, page_shared, page_copy, page_readonly;
1691         unsigned long page_exec_bit;
1692
1693         PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
1694                                 _PAGE_CACHE_4U | _PAGE_P_4U |
1695                                 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
1696                                 _PAGE_EXEC_4U);
1697         PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
1698                                        _PAGE_CACHE_4U | _PAGE_P_4U |
1699                                        __ACCESS_BITS_4U | __DIRTY_BITS_4U |
1700                                        _PAGE_EXEC_4U | _PAGE_L_4U);
1701         PAGE_EXEC = __pgprot(_PAGE_EXEC_4U);
1702
1703         _PAGE_IE = _PAGE_IE_4U;
1704         _PAGE_E = _PAGE_E_4U;
1705         _PAGE_CACHE = _PAGE_CACHE_4U;
1706
1707         pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U |
1708                      __ACCESS_BITS_4U | _PAGE_E_4U);
1709
1710 #ifdef CONFIG_DEBUG_PAGEALLOC
1711         kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZBITS_4U) ^
1712                 0xfffff80000000000;
1713 #else
1714         kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
1715                 0xfffff80000000000;
1716 #endif
1717         kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U |
1718                                    _PAGE_P_4U | _PAGE_W_4U);
1719
1720         /* XXX Should use 256MB on Panther. XXX */
1721         kern_linear_pte_xor[1] = kern_linear_pte_xor[0];
1722
1723         _PAGE_SZBITS = _PAGE_SZBITS_4U;
1724         _PAGE_ALL_SZ_BITS =  (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
1725                               _PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
1726                               _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);
1727
1728
1729         page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U;
1730         page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1731                        __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U);
1732         page_copy   = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1733                        __ACCESS_BITS_4U | _PAGE_EXEC_4U);
1734         page_readonly   = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1735                            __ACCESS_BITS_4U | _PAGE_EXEC_4U);
1736
1737         page_exec_bit = _PAGE_EXEC_4U;
1738
1739         prot_init_common(page_none, page_shared, page_copy, page_readonly,
1740                          page_exec_bit);
1741 }
1742
1743 static void __init sun4v_pgprot_init(void)
1744 {
1745         unsigned long page_none, page_shared, page_copy, page_readonly;
1746         unsigned long page_exec_bit;
1747
1748         PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
1749                                 _PAGE_CACHE_4V | _PAGE_P_4V |
1750                                 __ACCESS_BITS_4V | __DIRTY_BITS_4V |
1751                                 _PAGE_EXEC_4V);
1752         PAGE_KERNEL_LOCKED = PAGE_KERNEL;
1753         PAGE_EXEC = __pgprot(_PAGE_EXEC_4V);
1754
1755         _PAGE_IE = _PAGE_IE_4V;
1756         _PAGE_E = _PAGE_E_4V;
1757         _PAGE_CACHE = _PAGE_CACHE_4V;
1758
1759 #ifdef CONFIG_DEBUG_PAGEALLOC
1760         kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZBITS_4V) ^
1761                 0xfffff80000000000;
1762 #else
1763         kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
1764                 0xfffff80000000000;
1765 #endif
1766         kern_linear_pte_xor[0] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1767                                    _PAGE_P_4V | _PAGE_W_4V);
1768
1769 #ifdef CONFIG_DEBUG_PAGEALLOC
1770         kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZBITS_4V) ^
1771                 0xfffff80000000000;
1772 #else
1773         kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^
1774                 0xfffff80000000000;
1775 #endif
1776         kern_linear_pte_xor[1] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1777                                    _PAGE_P_4V | _PAGE_W_4V);
1778
1779         pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
1780                      __ACCESS_BITS_4V | _PAGE_E_4V);
1781
1782         _PAGE_SZBITS = _PAGE_SZBITS_4V;
1783         _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
1784                              _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
1785                              _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
1786                              _PAGE_SZ64K_4V | _PAGE_SZ8K_4V);
1787
1788         page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | _PAGE_CACHE_4V;
1789         page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1790                        __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V);
1791         page_copy   = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1792                        __ACCESS_BITS_4V | _PAGE_EXEC_4V);
1793         page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1794                          __ACCESS_BITS_4V | _PAGE_EXEC_4V);
1795
1796         page_exec_bit = _PAGE_EXEC_4V;
1797
1798         prot_init_common(page_none, page_shared, page_copy, page_readonly,
1799                          page_exec_bit);
1800 }
1801
1802 unsigned long pte_sz_bits(unsigned long sz)
1803 {
1804         if (tlb_type == hypervisor) {
1805                 switch (sz) {
1806                 case 8 * 1024:
1807                 default:
1808                         return _PAGE_SZ8K_4V;
1809                 case 64 * 1024:
1810                         return _PAGE_SZ64K_4V;
1811                 case 512 * 1024:
1812                         return _PAGE_SZ512K_4V;
1813                 case 4 * 1024 * 1024:
1814                         return _PAGE_SZ4MB_4V;
1815                 };
1816         } else {
1817                 switch (sz) {
1818                 case 8 * 1024:
1819                 default:
1820                         return _PAGE_SZ8K_4U;
1821                 case 64 * 1024:
1822                         return _PAGE_SZ64K_4U;
1823                 case 512 * 1024:
1824                         return _PAGE_SZ512K_4U;
1825                 case 4 * 1024 * 1024:
1826                         return _PAGE_SZ4MB_4U;
1827                 };
1828         }
1829 }
1830
1831 pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size)
1832 {
1833         pte_t pte;
1834
1835         pte_val(pte)  = page | pgprot_val(pgprot_noncached(prot));
1836         pte_val(pte) |= (((unsigned long)space) << 32);
1837         pte_val(pte) |= pte_sz_bits(page_size);
1838
1839         return pte;
1840 }
1841
1842 static unsigned long kern_large_tte(unsigned long paddr)
1843 {
1844         unsigned long val;
1845
1846         val = (_PAGE_VALID | _PAGE_SZ4MB_4U |
1847                _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U |
1848                _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U);
1849         if (tlb_type == hypervisor)
1850                 val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
1851                        _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_P_4V |
1852                        _PAGE_EXEC_4V | _PAGE_W_4V);
1853
1854         return val | paddr;
1855 }
1856
1857 /* If not locked, zap it. */
1858 void __flush_tlb_all(void)
1859 {
1860         unsigned long pstate;
1861         int i;
1862
1863         __asm__ __volatile__("flushw\n\t"
1864                              "rdpr      %%pstate, %0\n\t"
1865                              "wrpr      %0, %1, %%pstate"
1866                              : "=r" (pstate)
1867                              : "i" (PSTATE_IE));
1868         if (tlb_type == hypervisor) {
1869                 sun4v_mmu_demap_all();
1870         } else if (tlb_type == spitfire) {
1871                 for (i = 0; i < 64; i++) {
1872                         /* Spitfire Errata #32 workaround */
1873                         /* NOTE: Always runs on spitfire, so no
1874                          *       cheetah+ page size encodings.
1875                          */
1876                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
1877                                              "flush     %%g6"
1878                                              : /* No outputs */
1879                                              : "r" (0),
1880                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1881
1882                         if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) {
1883                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1884                                                      "membar #Sync"
1885                                                      : /* no outputs */
1886                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
1887                                 spitfire_put_dtlb_data(i, 0x0UL);
1888                         }
1889
1890                         /* Spitfire Errata #32 workaround */
1891                         /* NOTE: Always runs on spitfire, so no
1892                          *       cheetah+ page size encodings.
1893                          */
1894                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
1895                                              "flush     %%g6"
1896                                              : /* No outputs */
1897                                              : "r" (0),
1898                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1899
1900                         if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) {
1901                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1902                                                      "membar #Sync"
1903                                                      : /* no outputs */
1904                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
1905                                 spitfire_put_itlb_data(i, 0x0UL);
1906                         }
1907                 }
1908         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1909                 cheetah_flush_dtlb_all();
1910                 cheetah_flush_itlb_all();
1911         }
1912         __asm__ __volatile__("wrpr      %0, 0, %%pstate"
1913                              : : "r" (pstate));
1914 }
1915
1916 #ifdef CONFIG_MEMORY_HOTPLUG
1917
1918 void online_page(struct page *page)
1919 {
1920         ClearPageReserved(page);
1921         init_page_count(page);
1922         __free_page(page);
1923         totalram_pages++;
1924         num_physpages++;
1925 }
1926
1927 #endif /* CONFIG_MEMORY_HOTPLUG */