[SPARC64]: Do not do TLB pre-filling any more.
[linux-2.6.git] / arch / sparc64 / mm / init.c
1 /*  $Id: init.c,v 1.209 2002/02/09 19:49:31 davem Exp $
2  *  arch/sparc64/mm/init.c
3  *
4  *  Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
5  *  Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
6  */
7  
8 #include <linux/config.h>
9 #include <linux/kernel.h>
10 #include <linux/sched.h>
11 #include <linux/string.h>
12 #include <linux/init.h>
13 #include <linux/bootmem.h>
14 #include <linux/mm.h>
15 #include <linux/hugetlb.h>
16 #include <linux/slab.h>
17 #include <linux/initrd.h>
18 #include <linux/swap.h>
19 #include <linux/pagemap.h>
20 #include <linux/fs.h>
21 #include <linux/seq_file.h>
22 #include <linux/kprobes.h>
23 #include <linux/cache.h>
24
25 #include <asm/head.h>
26 #include <asm/system.h>
27 #include <asm/page.h>
28 #include <asm/pgalloc.h>
29 #include <asm/pgtable.h>
30 #include <asm/oplib.h>
31 #include <asm/iommu.h>
32 #include <asm/io.h>
33 #include <asm/uaccess.h>
34 #include <asm/mmu_context.h>
35 #include <asm/tlbflush.h>
36 #include <asm/dma.h>
37 #include <asm/starfire.h>
38 #include <asm/tlb.h>
39 #include <asm/spitfire.h>
40 #include <asm/sections.h>
41
42 extern void device_scan(void);
43
44 struct sparc_phys_banks sp_banks[SPARC_PHYS_BANKS];
45
46 unsigned long *sparc64_valid_addr_bitmap __read_mostly;
47
48 /* Ugly, but necessary... -DaveM */
49 unsigned long phys_base __read_mostly;
50 unsigned long kern_base __read_mostly;
51 unsigned long kern_size __read_mostly;
52 unsigned long pfn_base __read_mostly;
53
54 /* get_new_mmu_context() uses "cache + 1".  */
55 DEFINE_SPINLOCK(ctx_alloc_lock);
56 unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
57 #define CTX_BMAP_SLOTS (1UL << (CTX_NR_BITS - 6))
58 unsigned long mmu_context_bmap[CTX_BMAP_SLOTS];
59
60 /* References to special section boundaries */
61 extern char  _start[], _end[];
62
63 /* Initial ramdisk setup */
64 extern unsigned long sparc_ramdisk_image64;
65 extern unsigned int sparc_ramdisk_image;
66 extern unsigned int sparc_ramdisk_size;
67
68 struct page *mem_map_zero __read_mostly;
69
70 int bigkernel = 0;
71
72 /* XXX Tune this... */
73 #define PGT_CACHE_LOW   25
74 #define PGT_CACHE_HIGH  50
75
76 void check_pgt_cache(void)
77 {
78         preempt_disable();
79         if (pgtable_cache_size > PGT_CACHE_HIGH) {
80                 do {
81                         if (pgd_quicklist)
82                                 free_pgd_slow(get_pgd_fast());
83                         if (pte_quicklist[0])
84                                 free_pte_slow(pte_alloc_one_fast(NULL, 0));
85                         if (pte_quicklist[1])
86                                 free_pte_slow(pte_alloc_one_fast(NULL, 1 << (PAGE_SHIFT + 10)));
87                 } while (pgtable_cache_size > PGT_CACHE_LOW);
88         }
89         preempt_enable();
90 }
91
92 #ifdef CONFIG_DEBUG_DCFLUSH
93 atomic_t dcpage_flushes = ATOMIC_INIT(0);
94 #ifdef CONFIG_SMP
95 atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
96 #endif
97 #endif
98
99 __inline__ void flush_dcache_page_impl(struct page *page)
100 {
101 #ifdef CONFIG_DEBUG_DCFLUSH
102         atomic_inc(&dcpage_flushes);
103 #endif
104
105 #ifdef DCACHE_ALIASING_POSSIBLE
106         __flush_dcache_page(page_address(page),
107                             ((tlb_type == spitfire) &&
108                              page_mapping(page) != NULL));
109 #else
110         if (page_mapping(page) != NULL &&
111             tlb_type == spitfire)
112                 __flush_icache_page(__pa(page_address(page)));
113 #endif
114 }
115
116 #define PG_dcache_dirty         PG_arch_1
117 #define PG_dcache_cpu_shift     24
118 #define PG_dcache_cpu_mask      (256 - 1)
119
120 #if NR_CPUS > 256
121 #error D-cache dirty tracking and thread_info->cpu need fixing for > 256 cpus
122 #endif
123
124 #define dcache_dirty_cpu(page) \
125         (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
126
127 static __inline__ void set_dcache_dirty(struct page *page, int this_cpu)
128 {
129         unsigned long mask = this_cpu;
130         unsigned long non_cpu_bits;
131
132         non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
133         mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
134
135         __asm__ __volatile__("1:\n\t"
136                              "ldx       [%2], %%g7\n\t"
137                              "and       %%g7, %1, %%g1\n\t"
138                              "or        %%g1, %0, %%g1\n\t"
139                              "casx      [%2], %%g7, %%g1\n\t"
140                              "cmp       %%g7, %%g1\n\t"
141                              "membar    #StoreLoad | #StoreStore\n\t"
142                              "bne,pn    %%xcc, 1b\n\t"
143                              " nop"
144                              : /* no outputs */
145                              : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
146                              : "g1", "g7");
147 }
148
149 static __inline__ void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
150 {
151         unsigned long mask = (1UL << PG_dcache_dirty);
152
153         __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
154                              "1:\n\t"
155                              "ldx       [%2], %%g7\n\t"
156                              "srlx      %%g7, %4, %%g1\n\t"
157                              "and       %%g1, %3, %%g1\n\t"
158                              "cmp       %%g1, %0\n\t"
159                              "bne,pn    %%icc, 2f\n\t"
160                              " andn     %%g7, %1, %%g1\n\t"
161                              "casx      [%2], %%g7, %%g1\n\t"
162                              "cmp       %%g7, %%g1\n\t"
163                              "membar    #StoreLoad | #StoreStore\n\t"
164                              "bne,pn    %%xcc, 1b\n\t"
165                              " nop\n"
166                              "2:"
167                              : /* no outputs */
168                              : "r" (cpu), "r" (mask), "r" (&page->flags),
169                                "i" (PG_dcache_cpu_mask),
170                                "i" (PG_dcache_cpu_shift)
171                              : "g1", "g7");
172 }
173
174 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
175 {
176         struct page *page;
177         unsigned long pfn;
178         unsigned long pg_flags;
179
180         pfn = pte_pfn(pte);
181         if (pfn_valid(pfn) &&
182             (page = pfn_to_page(pfn), page_mapping(page)) &&
183             ((pg_flags = page->flags) & (1UL << PG_dcache_dirty))) {
184                 int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
185                            PG_dcache_cpu_mask);
186                 int this_cpu = get_cpu();
187
188                 /* This is just to optimize away some function calls
189                  * in the SMP case.
190                  */
191                 if (cpu == this_cpu)
192                         flush_dcache_page_impl(page);
193                 else
194                         smp_flush_dcache_page_impl(page, cpu);
195
196                 clear_dcache_dirty_cpu(page, cpu);
197
198                 put_cpu();
199         }
200 }
201
202 void flush_dcache_page(struct page *page)
203 {
204         struct address_space *mapping;
205         int this_cpu;
206
207         /* Do not bother with the expensive D-cache flush if it
208          * is merely the zero page.  The 'bigcore' testcase in GDB
209          * causes this case to run millions of times.
210          */
211         if (page == ZERO_PAGE(0))
212                 return;
213
214         this_cpu = get_cpu();
215
216         mapping = page_mapping(page);
217         if (mapping && !mapping_mapped(mapping)) {
218                 int dirty = test_bit(PG_dcache_dirty, &page->flags);
219                 if (dirty) {
220                         int dirty_cpu = dcache_dirty_cpu(page);
221
222                         if (dirty_cpu == this_cpu)
223                                 goto out;
224                         smp_flush_dcache_page_impl(page, dirty_cpu);
225                 }
226                 set_dcache_dirty(page, this_cpu);
227         } else {
228                 /* We could delay the flush for the !page_mapping
229                  * case too.  But that case is for exec env/arg
230                  * pages and those are %99 certainly going to get
231                  * faulted into the tlb (and thus flushed) anyways.
232                  */
233                 flush_dcache_page_impl(page);
234         }
235
236 out:
237         put_cpu();
238 }
239
240 void __kprobes flush_icache_range(unsigned long start, unsigned long end)
241 {
242         /* Cheetah has coherent I-cache. */
243         if (tlb_type == spitfire) {
244                 unsigned long kaddr;
245
246                 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE)
247                         __flush_icache_page(__get_phys(kaddr));
248         }
249 }
250
251 unsigned long page_to_pfn(struct page *page)
252 {
253         return (unsigned long) ((page - mem_map) + pfn_base);
254 }
255
256 struct page *pfn_to_page(unsigned long pfn)
257 {
258         return (mem_map + (pfn - pfn_base));
259 }
260
261 void show_mem(void)
262 {
263         printk("Mem-info:\n");
264         show_free_areas();
265         printk("Free swap:       %6ldkB\n",
266                nr_swap_pages << (PAGE_SHIFT-10));
267         printk("%ld pages of RAM\n", num_physpages);
268         printk("%d free pages\n", nr_free_pages());
269         printk("%d pages in page table cache\n",pgtable_cache_size);
270 }
271
272 void mmu_info(struct seq_file *m)
273 {
274         if (tlb_type == cheetah)
275                 seq_printf(m, "MMU Type\t: Cheetah\n");
276         else if (tlb_type == cheetah_plus)
277                 seq_printf(m, "MMU Type\t: Cheetah+\n");
278         else if (tlb_type == spitfire)
279                 seq_printf(m, "MMU Type\t: Spitfire\n");
280         else
281                 seq_printf(m, "MMU Type\t: ???\n");
282
283 #ifdef CONFIG_DEBUG_DCFLUSH
284         seq_printf(m, "DCPageFlushes\t: %d\n",
285                    atomic_read(&dcpage_flushes));
286 #ifdef CONFIG_SMP
287         seq_printf(m, "DCPageFlushesXC\t: %d\n",
288                    atomic_read(&dcpage_flushes_xcall));
289 #endif /* CONFIG_SMP */
290 #endif /* CONFIG_DEBUG_DCFLUSH */
291 }
292
293 struct linux_prom_translation {
294         unsigned long virt;
295         unsigned long size;
296         unsigned long data;
297 };
298 static struct linux_prom_translation prom_trans[512] __initdata;
299
300 extern unsigned long prom_boot_page;
301 extern void prom_remap(unsigned long physpage, unsigned long virtpage, int mmu_ihandle);
302 extern int prom_get_mmu_ihandle(void);
303 extern void register_prom_callbacks(void);
304
305 /* Exported for SMP bootup purposes. */
306 unsigned long kern_locked_tte_data;
307
308 /* Exported for kernel TLB miss handling in ktlb.S */
309 unsigned long prom_pmd_phys __read_mostly;
310 unsigned int swapper_pgd_zero __read_mostly;
311
312 /* Allocate power-of-2 aligned chunks from the end of the
313  * kernel image.  Return physical address.
314  */
315 static inline unsigned long early_alloc_phys(unsigned long size)
316 {
317         unsigned long base;
318
319         BUILD_BUG_ON(size & (size - 1));
320
321         kern_size = (kern_size + (size - 1)) & ~(size - 1);
322         base = kern_base + kern_size;
323         kern_size += size;
324
325         return base;
326 }
327
328 static inline unsigned long load_phys32(unsigned long pa)
329 {
330         unsigned long val;
331
332         __asm__ __volatile__("lduwa     [%1] %2, %0"
333                              : "=&r" (val)
334                              : "r" (pa), "i" (ASI_PHYS_USE_EC));
335
336         return val;
337 }
338
339 static inline unsigned long load_phys64(unsigned long pa)
340 {
341         unsigned long val;
342
343         __asm__ __volatile__("ldxa      [%1] %2, %0"
344                              : "=&r" (val)
345                              : "r" (pa), "i" (ASI_PHYS_USE_EC));
346
347         return val;
348 }
349
350 static inline void store_phys32(unsigned long pa, unsigned long val)
351 {
352         __asm__ __volatile__("stwa      %0, [%1] %2"
353                              : /* no outputs */
354                              : "r" (val), "r" (pa), "i" (ASI_PHYS_USE_EC));
355 }
356
357 static inline void store_phys64(unsigned long pa, unsigned long val)
358 {
359         __asm__ __volatile__("stxa      %0, [%1] %2"
360                              : /* no outputs */
361                              : "r" (val), "r" (pa), "i" (ASI_PHYS_USE_EC));
362 }
363
364 #define BASE_PAGE_SIZE 8192
365
366 /*
367  * Translate PROM's mapping we capture at boot time into physical address.
368  * The second parameter is only set from prom_callback() invocations.
369  */
370 unsigned long prom_virt_to_phys(unsigned long promva, int *error)
371 {
372         unsigned long pmd_phys = (prom_pmd_phys +
373                                   ((promva >> 23) & 0x7ff) * sizeof(pmd_t));
374         unsigned long pte_phys;
375         pmd_t pmd_ent;
376         pte_t pte_ent;
377         unsigned long base;
378
379         pmd_val(pmd_ent) = load_phys32(pmd_phys);
380         if (pmd_none(pmd_ent)) {
381                 if (error)
382                         *error = 1;
383                 return 0;
384         }
385
386         pte_phys = (unsigned long)pmd_val(pmd_ent) << 11UL;
387         pte_phys += ((promva >> 13) & 0x3ff) * sizeof(pte_t);
388         pte_val(pte_ent) = load_phys64(pte_phys);
389         if (!pte_present(pte_ent)) {
390                 if (error)
391                         *error = 1;
392                 return 0;
393         }
394         if (error) {
395                 *error = 0;
396                 return pte_val(pte_ent);
397         }
398         base = pte_val(pte_ent) & _PAGE_PADDR;
399         return (base + (promva & (BASE_PAGE_SIZE - 1)));
400 }
401
402 /* The obp translations are saved based on 8k pagesize, since obp can
403  * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
404  * HI_OBP_ADDRESS range are handled in entry.S and do not use the vpte
405  * scheme (also, see rant in inherit_locked_prom_mappings()).
406  */
407 static void __init build_obp_range(unsigned long start, unsigned long end, unsigned long data)
408 {
409         unsigned long vaddr;
410
411         for (vaddr = start; vaddr < end; vaddr += BASE_PAGE_SIZE) {
412                 unsigned long val, pte_phys, pmd_phys;
413                 pmd_t pmd_ent;
414                 int i;
415
416                 pmd_phys = (prom_pmd_phys +
417                             (((vaddr >> 23) & 0x7ff) * sizeof(pmd_t)));
418                 pmd_val(pmd_ent) = load_phys32(pmd_phys);
419                 if (pmd_none(pmd_ent)) {
420                         pte_phys = early_alloc_phys(BASE_PAGE_SIZE);
421
422                         for (i = 0; i < BASE_PAGE_SIZE / sizeof(pte_t); i++)
423                                 store_phys64(pte_phys+i*sizeof(pte_t),0);
424
425                         pmd_val(pmd_ent) = pte_phys >> 11UL;
426                         store_phys32(pmd_phys, pmd_val(pmd_ent));
427                 }
428
429                 pte_phys = (unsigned long)pmd_val(pmd_ent) << 11UL;
430                 pte_phys += (((vaddr >> 13) & 0x3ff) * sizeof(pte_t));
431
432                 val = data;
433
434                 /* Clear diag TTE bits. */
435                 if (tlb_type == spitfire)
436                         val &= ~0x0003fe0000000000UL;
437
438                 store_phys64(pte_phys, val | _PAGE_MODIFIED);
439
440                 data += BASE_PAGE_SIZE;
441         }
442 }
443
444 static inline int in_obp_range(unsigned long vaddr)
445 {
446         return (vaddr >= LOW_OBP_ADDRESS &&
447                 vaddr < HI_OBP_ADDRESS);
448 }
449
450 #define OBP_PMD_SIZE 2048
451 static void __init build_obp_pgtable(int prom_trans_ents)
452 {
453         unsigned long i;
454
455         prom_pmd_phys = early_alloc_phys(OBP_PMD_SIZE);
456         for (i = 0; i < OBP_PMD_SIZE; i += 4)
457                 store_phys32(prom_pmd_phys + i, 0);
458
459         for (i = 0; i < prom_trans_ents; i++) {
460                 unsigned long start, end;
461
462                 if (!in_obp_range(prom_trans[i].virt))
463                         continue;
464
465                 start = prom_trans[i].virt;
466                 end = start + prom_trans[i].size;
467                 if (end > HI_OBP_ADDRESS)
468                         end = HI_OBP_ADDRESS;
469
470                 build_obp_range(start, end, prom_trans[i].data);
471         }
472 }
473
474 /* Read OBP translations property into 'prom_trans[]'.
475  * Return the number of entries.
476  */
477 static int __init read_obp_translations(void)
478 {
479         int n, node;
480
481         node = prom_finddevice("/virtual-memory");
482         n = prom_getproplen(node, "translations");
483         if (unlikely(n == 0 || n == -1)) {
484                 prom_printf("prom_mappings: Couldn't get size.\n");
485                 prom_halt();
486         }
487         if (unlikely(n > sizeof(prom_trans))) {
488                 prom_printf("prom_mappings: Size %Zd is too big.\n", n);
489                 prom_halt();
490         }
491
492         if ((n = prom_getproperty(node, "translations",
493                                   (char *)&prom_trans[0],
494                                   sizeof(prom_trans))) == -1) {
495                 prom_printf("prom_mappings: Couldn't get property.\n");
496                 prom_halt();
497         }
498         n = n / sizeof(struct linux_prom_translation);
499         return n;
500 }
501
502 static void __init remap_kernel(void)
503 {
504         unsigned long phys_page, tte_vaddr, tte_data;
505         int tlb_ent = sparc64_highest_locked_tlbent();
506
507         tte_vaddr = (unsigned long) KERNBASE;
508         phys_page = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
509         tte_data = (phys_page | (_PAGE_VALID | _PAGE_SZ4MB |
510                                  _PAGE_CP | _PAGE_CV | _PAGE_P |
511                                  _PAGE_L | _PAGE_W));
512
513         kern_locked_tte_data = tte_data;
514
515         /* Now lock us into the TLBs via OBP. */
516         prom_dtlb_load(tlb_ent, tte_data, tte_vaddr);
517         prom_itlb_load(tlb_ent, tte_data, tte_vaddr);
518         if (bigkernel) {
519                 prom_dtlb_load(tlb_ent - 1,
520                                tte_data + 0x400000, 
521                                tte_vaddr + 0x400000);
522                 prom_itlb_load(tlb_ent - 1,
523                                tte_data + 0x400000, 
524                                tte_vaddr + 0x400000);
525         }
526 }
527
528 static void __init inherit_prom_mappings(void)
529 {
530         int n;
531
532         n = read_obp_translations();
533         build_obp_pgtable(n);
534
535         /* Now fixup OBP's idea about where we really are mapped. */
536         prom_printf("Remapping the kernel... ");
537         remap_kernel();
538
539         prom_printf("done.\n");
540
541         register_prom_callbacks();
542 }
543
544 /* The OBP specifications for sun4u mark 0xfffffffc00000000 and
545  * upwards as reserved for use by the firmware (I wonder if this
546  * will be the same on Cheetah...).  We use this virtual address
547  * range for the VPTE table mappings of the nucleus so we need
548  * to zap them when we enter the PROM.  -DaveM
549  */
550 static void __flush_nucleus_vptes(void)
551 {
552         unsigned long prom_reserved_base = 0xfffffffc00000000UL;
553         int i;
554
555         /* Only DTLB must be checked for VPTE entries. */
556         if (tlb_type == spitfire) {
557                 for (i = 0; i < 63; i++) {
558                         unsigned long tag;
559
560                         /* Spitfire Errata #32 workaround */
561                         /* NOTE: Always runs on spitfire, so no cheetah+
562                          *       page size encodings.
563                          */
564                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
565                                              "flush     %%g6"
566                                              : /* No outputs */
567                                              : "r" (0),
568                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
569
570                         tag = spitfire_get_dtlb_tag(i);
571                         if (((tag & ~(PAGE_MASK)) == 0) &&
572                             ((tag &  (PAGE_MASK)) >= prom_reserved_base)) {
573                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
574                                                      "membar #Sync"
575                                                      : /* no outputs */
576                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
577                                 spitfire_put_dtlb_data(i, 0x0UL);
578                         }
579                 }
580         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
581                 for (i = 0; i < 512; i++) {
582                         unsigned long tag = cheetah_get_dtlb_tag(i, 2);
583
584                         if ((tag & ~PAGE_MASK) == 0 &&
585                             (tag & PAGE_MASK) >= prom_reserved_base) {
586                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
587                                                      "membar #Sync"
588                                                      : /* no outputs */
589                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
590                                 cheetah_put_dtlb_data(i, 0x0UL, 2);
591                         }
592
593                         if (tlb_type != cheetah_plus)
594                                 continue;
595
596                         tag = cheetah_get_dtlb_tag(i, 3);
597
598                         if ((tag & ~PAGE_MASK) == 0 &&
599                             (tag & PAGE_MASK) >= prom_reserved_base) {
600                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
601                                                      "membar #Sync"
602                                                      : /* no outputs */
603                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
604                                 cheetah_put_dtlb_data(i, 0x0UL, 3);
605                         }
606                 }
607         } else {
608                 /* Implement me :-) */
609                 BUG();
610         }
611 }
612
613 static int prom_ditlb_set;
614 struct prom_tlb_entry {
615         int             tlb_ent;
616         unsigned long   tlb_tag;
617         unsigned long   tlb_data;
618 };
619 struct prom_tlb_entry prom_itlb[16], prom_dtlb[16];
620
621 void prom_world(int enter)
622 {
623         unsigned long pstate;
624         int i;
625
626         if (!enter)
627                 set_fs((mm_segment_t) { get_thread_current_ds() });
628
629         if (!prom_ditlb_set)
630                 return;
631
632         /* Make sure the following runs atomically. */
633         __asm__ __volatile__("flushw\n\t"
634                              "rdpr      %%pstate, %0\n\t"
635                              "wrpr      %0, %1, %%pstate"
636                              : "=r" (pstate)
637                              : "i" (PSTATE_IE));
638
639         if (enter) {
640                 /* Kick out nucleus VPTEs. */
641                 __flush_nucleus_vptes();
642
643                 /* Install PROM world. */
644                 for (i = 0; i < 16; i++) {
645                         if (prom_dtlb[i].tlb_ent != -1) {
646                                 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
647                                                      "membar #Sync"
648                                         : : "r" (prom_dtlb[i].tlb_tag), "r" (TLB_TAG_ACCESS),
649                                         "i" (ASI_DMMU));
650                                 if (tlb_type == spitfire)
651                                         spitfire_put_dtlb_data(prom_dtlb[i].tlb_ent,
652                                                                prom_dtlb[i].tlb_data);
653                                 else if (tlb_type == cheetah || tlb_type == cheetah_plus)
654                                         cheetah_put_ldtlb_data(prom_dtlb[i].tlb_ent,
655                                                                prom_dtlb[i].tlb_data);
656                         }
657                         if (prom_itlb[i].tlb_ent != -1) {
658                                 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
659                                                      "membar #Sync"
660                                                      : : "r" (prom_itlb[i].tlb_tag),
661                                                      "r" (TLB_TAG_ACCESS),
662                                                      "i" (ASI_IMMU));
663                                 if (tlb_type == spitfire)
664                                         spitfire_put_itlb_data(prom_itlb[i].tlb_ent,
665                                                                prom_itlb[i].tlb_data);
666                                 else if (tlb_type == cheetah || tlb_type == cheetah_plus)
667                                         cheetah_put_litlb_data(prom_itlb[i].tlb_ent,
668                                                                prom_itlb[i].tlb_data);
669                         }
670                 }
671         } else {
672                 for (i = 0; i < 16; i++) {
673                         if (prom_dtlb[i].tlb_ent != -1) {
674                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
675                                                      "membar #Sync"
676                                         : : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
677                                 if (tlb_type == spitfire)
678                                         spitfire_put_dtlb_data(prom_dtlb[i].tlb_ent, 0x0UL);
679                                 else
680                                         cheetah_put_ldtlb_data(prom_dtlb[i].tlb_ent, 0x0UL);
681                         }
682                         if (prom_itlb[i].tlb_ent != -1) {
683                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
684                                                      "membar #Sync"
685                                                      : : "r" (TLB_TAG_ACCESS),
686                                                      "i" (ASI_IMMU));
687                                 if (tlb_type == spitfire)
688                                         spitfire_put_itlb_data(prom_itlb[i].tlb_ent, 0x0UL);
689                                 else
690                                         cheetah_put_litlb_data(prom_itlb[i].tlb_ent, 0x0UL);
691                         }
692                 }
693         }
694         __asm__ __volatile__("wrpr      %0, 0, %%pstate"
695                              : : "r" (pstate));
696 }
697
698 void inherit_locked_prom_mappings(int save_p)
699 {
700         int i;
701         int dtlb_seen = 0;
702         int itlb_seen = 0;
703
704         /* Fucking losing PROM has more mappings in the TLB, but
705          * it (conveniently) fails to mention any of these in the
706          * translations property.  The only ones that matter are
707          * the locked PROM tlb entries, so we impose the following
708          * irrecovable rule on the PROM, it is allowed 8 locked
709          * entries in the ITLB and 8 in the DTLB.
710          *
711          * Supposedly the upper 16GB of the address space is
712          * reserved for OBP, BUT I WISH THIS WAS DOCUMENTED
713          * SOMEWHERE!!!!!!!!!!!!!!!!!  Furthermore the entire interface
714          * used between the client program and the firmware on sun5
715          * systems to coordinate mmu mappings is also COMPLETELY
716          * UNDOCUMENTED!!!!!! Thanks S(t)un!
717          */
718         if (save_p) {
719                 for (i = 0; i < 16; i++) {
720                         prom_itlb[i].tlb_ent = -1;
721                         prom_dtlb[i].tlb_ent = -1;
722                 }
723         }
724         if (tlb_type == spitfire) {
725                 int high = SPITFIRE_HIGHEST_LOCKED_TLBENT - bigkernel;
726                 for (i = 0; i < high; i++) {
727                         unsigned long data;
728
729                         /* Spitfire Errata #32 workaround */
730                         /* NOTE: Always runs on spitfire, so no cheetah+
731                          *       page size encodings.
732                          */
733                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
734                                              "flush     %%g6"
735                                              : /* No outputs */
736                                              : "r" (0),
737                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
738
739                         data = spitfire_get_dtlb_data(i);
740                         if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
741                                 unsigned long tag;
742
743                                 /* Spitfire Errata #32 workaround */
744                                 /* NOTE: Always runs on spitfire, so no
745                                  *       cheetah+ page size encodings.
746                                  */
747                                 __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
748                                                      "flush     %%g6"
749                                                      : /* No outputs */
750                                                      : "r" (0),
751                                                      "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
752
753                                 tag = spitfire_get_dtlb_tag(i);
754                                 if (save_p) {
755                                         prom_dtlb[dtlb_seen].tlb_ent = i;
756                                         prom_dtlb[dtlb_seen].tlb_tag = tag;
757                                         prom_dtlb[dtlb_seen].tlb_data = data;
758                                 }
759                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
760                                                      "membar #Sync"
761                                                      : : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
762                                 spitfire_put_dtlb_data(i, 0x0UL);
763
764                                 dtlb_seen++;
765                                 if (dtlb_seen > 15)
766                                         break;
767                         }
768                 }
769
770                 for (i = 0; i < high; i++) {
771                         unsigned long data;
772
773                         /* Spitfire Errata #32 workaround */
774                         /* NOTE: Always runs on spitfire, so no
775                          *       cheetah+ page size encodings.
776                          */
777                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
778                                              "flush     %%g6"
779                                              : /* No outputs */
780                                              : "r" (0),
781                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
782
783                         data = spitfire_get_itlb_data(i);
784                         if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
785                                 unsigned long tag;
786
787                                 /* Spitfire Errata #32 workaround */
788                                 /* NOTE: Always runs on spitfire, so no
789                                  *       cheetah+ page size encodings.
790                                  */
791                                 __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
792                                                      "flush     %%g6"
793                                                      : /* No outputs */
794                                                      : "r" (0),
795                                                      "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
796
797                                 tag = spitfire_get_itlb_tag(i);
798                                 if (save_p) {
799                                         prom_itlb[itlb_seen].tlb_ent = i;
800                                         prom_itlb[itlb_seen].tlb_tag = tag;
801                                         prom_itlb[itlb_seen].tlb_data = data;
802                                 }
803                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
804                                                      "membar #Sync"
805                                                      : : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
806                                 spitfire_put_itlb_data(i, 0x0UL);
807
808                                 itlb_seen++;
809                                 if (itlb_seen > 15)
810                                         break;
811                         }
812                 }
813         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
814                 int high = CHEETAH_HIGHEST_LOCKED_TLBENT - bigkernel;
815
816                 for (i = 0; i < high; i++) {
817                         unsigned long data;
818
819                         data = cheetah_get_ldtlb_data(i);
820                         if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
821                                 unsigned long tag;
822
823                                 tag = cheetah_get_ldtlb_tag(i);
824                                 if (save_p) {
825                                         prom_dtlb[dtlb_seen].tlb_ent = i;
826                                         prom_dtlb[dtlb_seen].tlb_tag = tag;
827                                         prom_dtlb[dtlb_seen].tlb_data = data;
828                                 }
829                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
830                                                      "membar #Sync"
831                                                      : : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
832                                 cheetah_put_ldtlb_data(i, 0x0UL);
833
834                                 dtlb_seen++;
835                                 if (dtlb_seen > 15)
836                                         break;
837                         }
838                 }
839
840                 for (i = 0; i < high; i++) {
841                         unsigned long data;
842
843                         data = cheetah_get_litlb_data(i);
844                         if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
845                                 unsigned long tag;
846
847                                 tag = cheetah_get_litlb_tag(i);
848                                 if (save_p) {
849                                         prom_itlb[itlb_seen].tlb_ent = i;
850                                         prom_itlb[itlb_seen].tlb_tag = tag;
851                                         prom_itlb[itlb_seen].tlb_data = data;
852                                 }
853                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
854                                                      "membar #Sync"
855                                                      : : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
856                                 cheetah_put_litlb_data(i, 0x0UL);
857
858                                 itlb_seen++;
859                                 if (itlb_seen > 15)
860                                         break;
861                         }
862                 }
863         } else {
864                 /* Implement me :-) */
865                 BUG();
866         }
867         if (save_p)
868                 prom_ditlb_set = 1;
869 }
870
871 /* Give PROM back his world, done during reboots... */
872 void prom_reload_locked(void)
873 {
874         int i;
875
876         for (i = 0; i < 16; i++) {
877                 if (prom_dtlb[i].tlb_ent != -1) {
878                         __asm__ __volatile__("stxa %0, [%1] %2\n\t"
879                                              "membar #Sync"
880                                 : : "r" (prom_dtlb[i].tlb_tag), "r" (TLB_TAG_ACCESS),
881                                 "i" (ASI_DMMU));
882                         if (tlb_type == spitfire)
883                                 spitfire_put_dtlb_data(prom_dtlb[i].tlb_ent,
884                                                        prom_dtlb[i].tlb_data);
885                         else if (tlb_type == cheetah || tlb_type == cheetah_plus)
886                                 cheetah_put_ldtlb_data(prom_dtlb[i].tlb_ent,
887                                                       prom_dtlb[i].tlb_data);
888                 }
889
890                 if (prom_itlb[i].tlb_ent != -1) {
891                         __asm__ __volatile__("stxa %0, [%1] %2\n\t"
892                                              "membar #Sync"
893                                              : : "r" (prom_itlb[i].tlb_tag),
894                                              "r" (TLB_TAG_ACCESS),
895                                              "i" (ASI_IMMU));
896                         if (tlb_type == spitfire)
897                                 spitfire_put_itlb_data(prom_itlb[i].tlb_ent,
898                                                        prom_itlb[i].tlb_data);
899                         else
900                                 cheetah_put_litlb_data(prom_itlb[i].tlb_ent,
901                                                        prom_itlb[i].tlb_data);
902                 }
903         }
904 }
905
906 #ifdef DCACHE_ALIASING_POSSIBLE
907 void __flush_dcache_range(unsigned long start, unsigned long end)
908 {
909         unsigned long va;
910
911         if (tlb_type == spitfire) {
912                 int n = 0;
913
914                 for (va = start; va < end; va += 32) {
915                         spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
916                         if (++n >= 512)
917                                 break;
918                 }
919         } else {
920                 start = __pa(start);
921                 end = __pa(end);
922                 for (va = start; va < end; va += 32)
923                         __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
924                                              "membar #Sync"
925                                              : /* no outputs */
926                                              : "r" (va),
927                                                "i" (ASI_DCACHE_INVALIDATE));
928         }
929 }
930 #endif /* DCACHE_ALIASING_POSSIBLE */
931
932 /* If not locked, zap it. */
933 void __flush_tlb_all(void)
934 {
935         unsigned long pstate;
936         int i;
937
938         __asm__ __volatile__("flushw\n\t"
939                              "rdpr      %%pstate, %0\n\t"
940                              "wrpr      %0, %1, %%pstate"
941                              : "=r" (pstate)
942                              : "i" (PSTATE_IE));
943         if (tlb_type == spitfire) {
944                 for (i = 0; i < 64; i++) {
945                         /* Spitfire Errata #32 workaround */
946                         /* NOTE: Always runs on spitfire, so no
947                          *       cheetah+ page size encodings.
948                          */
949                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
950                                              "flush     %%g6"
951                                              : /* No outputs */
952                                              : "r" (0),
953                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
954
955                         if (!(spitfire_get_dtlb_data(i) & _PAGE_L)) {
956                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
957                                                      "membar #Sync"
958                                                      : /* no outputs */
959                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
960                                 spitfire_put_dtlb_data(i, 0x0UL);
961                         }
962
963                         /* Spitfire Errata #32 workaround */
964                         /* NOTE: Always runs on spitfire, so no
965                          *       cheetah+ page size encodings.
966                          */
967                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
968                                              "flush     %%g6"
969                                              : /* No outputs */
970                                              : "r" (0),
971                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
972
973                         if (!(spitfire_get_itlb_data(i) & _PAGE_L)) {
974                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
975                                                      "membar #Sync"
976                                                      : /* no outputs */
977                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
978                                 spitfire_put_itlb_data(i, 0x0UL);
979                         }
980                 }
981         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
982                 cheetah_flush_dtlb_all();
983                 cheetah_flush_itlb_all();
984         }
985         __asm__ __volatile__("wrpr      %0, 0, %%pstate"
986                              : : "r" (pstate));
987 }
988
989 /* Caller does TLB context flushing on local CPU if necessary.
990  * The caller also ensures that CTX_VALID(mm->context) is false.
991  *
992  * We must be careful about boundary cases so that we never
993  * let the user have CTX 0 (nucleus) or we ever use a CTX
994  * version of zero (and thus NO_CONTEXT would not be caught
995  * by version mis-match tests in mmu_context.h).
996  */
997 void get_new_mmu_context(struct mm_struct *mm)
998 {
999         unsigned long ctx, new_ctx;
1000         unsigned long orig_pgsz_bits;
1001         
1002
1003         spin_lock(&ctx_alloc_lock);
1004         orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
1005         ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
1006         new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
1007         if (new_ctx >= (1 << CTX_NR_BITS)) {
1008                 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
1009                 if (new_ctx >= ctx) {
1010                         int i;
1011                         new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
1012                                 CTX_FIRST_VERSION;
1013                         if (new_ctx == 1)
1014                                 new_ctx = CTX_FIRST_VERSION;
1015
1016                         /* Don't call memset, for 16 entries that's just
1017                          * plain silly...
1018                          */
1019                         mmu_context_bmap[0] = 3;
1020                         mmu_context_bmap[1] = 0;
1021                         mmu_context_bmap[2] = 0;
1022                         mmu_context_bmap[3] = 0;
1023                         for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
1024                                 mmu_context_bmap[i + 0] = 0;
1025                                 mmu_context_bmap[i + 1] = 0;
1026                                 mmu_context_bmap[i + 2] = 0;
1027                                 mmu_context_bmap[i + 3] = 0;
1028                         }
1029                         goto out;
1030                 }
1031         }
1032         mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
1033         new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
1034 out:
1035         tlb_context_cache = new_ctx;
1036         mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
1037         spin_unlock(&ctx_alloc_lock);
1038 }
1039
1040 #ifndef CONFIG_SMP
1041 struct pgtable_cache_struct pgt_quicklists;
1042 #endif
1043
1044 /* OK, we have to color these pages. The page tables are accessed
1045  * by non-Dcache enabled mapping in the VPTE area by the dtlb_backend.S
1046  * code, as well as by PAGE_OFFSET range direct-mapped addresses by 
1047  * other parts of the kernel. By coloring, we make sure that the tlbmiss 
1048  * fast handlers do not get data from old/garbage dcache lines that 
1049  * correspond to an old/stale virtual address (user/kernel) that 
1050  * previously mapped the pagetable page while accessing vpte range 
1051  * addresses. The idea is that if the vpte color and PAGE_OFFSET range 
1052  * color is the same, then when the kernel initializes the pagetable 
1053  * using the later address range, accesses with the first address
1054  * range will see the newly initialized data rather than the garbage.
1055  */
1056 #ifdef DCACHE_ALIASING_POSSIBLE
1057 #define DC_ALIAS_SHIFT  1
1058 #else
1059 #define DC_ALIAS_SHIFT  0
1060 #endif
1061 pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address)
1062 {
1063         struct page *page;
1064         unsigned long color;
1065
1066         {
1067                 pte_t *ptep = pte_alloc_one_fast(mm, address);
1068
1069                 if (ptep)
1070                         return ptep;
1071         }
1072
1073         color = VPTE_COLOR(address);
1074         page = alloc_pages(GFP_KERNEL|__GFP_REPEAT, DC_ALIAS_SHIFT);
1075         if (page) {
1076                 unsigned long *to_free;
1077                 unsigned long paddr;
1078                 pte_t *pte;
1079
1080 #ifdef DCACHE_ALIASING_POSSIBLE
1081                 set_page_count(page, 1);
1082                 ClearPageCompound(page);
1083
1084                 set_page_count((page + 1), 1);
1085                 ClearPageCompound(page + 1);
1086 #endif
1087                 paddr = (unsigned long) page_address(page);
1088                 memset((char *)paddr, 0, (PAGE_SIZE << DC_ALIAS_SHIFT));
1089
1090                 if (!color) {
1091                         pte = (pte_t *) paddr;
1092                         to_free = (unsigned long *) (paddr + PAGE_SIZE);
1093                 } else {
1094                         pte = (pte_t *) (paddr + PAGE_SIZE);
1095                         to_free = (unsigned long *) paddr;
1096                 }
1097
1098 #ifdef DCACHE_ALIASING_POSSIBLE
1099                 /* Now free the other one up, adjust cache size. */
1100                 preempt_disable();
1101                 *to_free = (unsigned long) pte_quicklist[color ^ 0x1];
1102                 pte_quicklist[color ^ 0x1] = to_free;
1103                 pgtable_cache_size++;
1104                 preempt_enable();
1105 #endif
1106
1107                 return pte;
1108         }
1109         return NULL;
1110 }
1111
1112 void sparc_ultra_dump_itlb(void)
1113 {
1114         int slot;
1115
1116         if (tlb_type == spitfire) {
1117                 printk ("Contents of itlb: ");
1118                 for (slot = 0; slot < 14; slot++) printk ("    ");
1119                 printk ("%2x:%016lx,%016lx\n",
1120                         0,
1121                         spitfire_get_itlb_tag(0), spitfire_get_itlb_data(0));
1122                 for (slot = 1; slot < 64; slot+=3) {
1123                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n", 
1124                                 slot,
1125                                 spitfire_get_itlb_tag(slot), spitfire_get_itlb_data(slot),
1126                                 slot+1,
1127                                 spitfire_get_itlb_tag(slot+1), spitfire_get_itlb_data(slot+1),
1128                                 slot+2,
1129                                 spitfire_get_itlb_tag(slot+2), spitfire_get_itlb_data(slot+2));
1130                 }
1131         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1132                 printk ("Contents of itlb0:\n");
1133                 for (slot = 0; slot < 16; slot+=2) {
1134                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1135                                 slot,
1136                                 cheetah_get_litlb_tag(slot), cheetah_get_litlb_data(slot),
1137                                 slot+1,
1138                                 cheetah_get_litlb_tag(slot+1), cheetah_get_litlb_data(slot+1));
1139                 }
1140                 printk ("Contents of itlb2:\n");
1141                 for (slot = 0; slot < 128; slot+=2) {
1142                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1143                                 slot,
1144                                 cheetah_get_itlb_tag(slot), cheetah_get_itlb_data(slot),
1145                                 slot+1,
1146                                 cheetah_get_itlb_tag(slot+1), cheetah_get_itlb_data(slot+1));
1147                 }
1148         }
1149 }
1150
1151 void sparc_ultra_dump_dtlb(void)
1152 {
1153         int slot;
1154
1155         if (tlb_type == spitfire) {
1156                 printk ("Contents of dtlb: ");
1157                 for (slot = 0; slot < 14; slot++) printk ("    ");
1158                 printk ("%2x:%016lx,%016lx\n", 0,
1159                         spitfire_get_dtlb_tag(0), spitfire_get_dtlb_data(0));
1160                 for (slot = 1; slot < 64; slot+=3) {
1161                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n", 
1162                                 slot,
1163                                 spitfire_get_dtlb_tag(slot), spitfire_get_dtlb_data(slot),
1164                                 slot+1,
1165                                 spitfire_get_dtlb_tag(slot+1), spitfire_get_dtlb_data(slot+1),
1166                                 slot+2,
1167                                 spitfire_get_dtlb_tag(slot+2), spitfire_get_dtlb_data(slot+2));
1168                 }
1169         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1170                 printk ("Contents of dtlb0:\n");
1171                 for (slot = 0; slot < 16; slot+=2) {
1172                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1173                                 slot,
1174                                 cheetah_get_ldtlb_tag(slot), cheetah_get_ldtlb_data(slot),
1175                                 slot+1,
1176                                 cheetah_get_ldtlb_tag(slot+1), cheetah_get_ldtlb_data(slot+1));
1177                 }
1178                 printk ("Contents of dtlb2:\n");
1179                 for (slot = 0; slot < 512; slot+=2) {
1180                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1181                                 slot,
1182                                 cheetah_get_dtlb_tag(slot, 2), cheetah_get_dtlb_data(slot, 2),
1183                                 slot+1,
1184                                 cheetah_get_dtlb_tag(slot+1, 2), cheetah_get_dtlb_data(slot+1, 2));
1185                 }
1186                 if (tlb_type == cheetah_plus) {
1187                         printk ("Contents of dtlb3:\n");
1188                         for (slot = 0; slot < 512; slot+=2) {
1189                                 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1190                                         slot,
1191                                         cheetah_get_dtlb_tag(slot, 3), cheetah_get_dtlb_data(slot, 3),
1192                                         slot+1,
1193                                         cheetah_get_dtlb_tag(slot+1, 3), cheetah_get_dtlb_data(slot+1, 3));
1194                         }
1195                 }
1196         }
1197 }
1198
1199 extern unsigned long cmdline_memory_size;
1200
1201 unsigned long __init bootmem_init(unsigned long *pages_avail)
1202 {
1203         unsigned long bootmap_size, start_pfn, end_pfn;
1204         unsigned long end_of_phys_memory = 0UL;
1205         unsigned long bootmap_pfn, bytes_avail, size;
1206         int i;
1207
1208 #ifdef CONFIG_DEBUG_BOOTMEM
1209         prom_printf("bootmem_init: Scan sp_banks, ");
1210 #endif
1211
1212         bytes_avail = 0UL;
1213         for (i = 0; sp_banks[i].num_bytes != 0; i++) {
1214                 end_of_phys_memory = sp_banks[i].base_addr +
1215                         sp_banks[i].num_bytes;
1216                 bytes_avail += sp_banks[i].num_bytes;
1217                 if (cmdline_memory_size) {
1218                         if (bytes_avail > cmdline_memory_size) {
1219                                 unsigned long slack = bytes_avail - cmdline_memory_size;
1220
1221                                 bytes_avail -= slack;
1222                                 end_of_phys_memory -= slack;
1223
1224                                 sp_banks[i].num_bytes -= slack;
1225                                 if (sp_banks[i].num_bytes == 0) {
1226                                         sp_banks[i].base_addr = 0xdeadbeef;
1227                                 } else {
1228                                         sp_banks[i+1].num_bytes = 0;
1229                                         sp_banks[i+1].base_addr = 0xdeadbeef;
1230                                 }
1231                                 break;
1232                         }
1233                 }
1234         }
1235
1236         *pages_avail = bytes_avail >> PAGE_SHIFT;
1237
1238         /* Start with page aligned address of last symbol in kernel
1239          * image.  The kernel is hard mapped below PAGE_OFFSET in a
1240          * 4MB locked TLB translation.
1241          */
1242         start_pfn = PAGE_ALIGN(kern_base + kern_size) >> PAGE_SHIFT;
1243
1244         bootmap_pfn = start_pfn;
1245
1246         end_pfn = end_of_phys_memory >> PAGE_SHIFT;
1247
1248 #ifdef CONFIG_BLK_DEV_INITRD
1249         /* Now have to check initial ramdisk, so that bootmap does not overwrite it */
1250         if (sparc_ramdisk_image || sparc_ramdisk_image64) {
1251                 unsigned long ramdisk_image = sparc_ramdisk_image ?
1252                         sparc_ramdisk_image : sparc_ramdisk_image64;
1253                 if (ramdisk_image >= (unsigned long)_end - 2 * PAGE_SIZE)
1254                         ramdisk_image -= KERNBASE;
1255                 initrd_start = ramdisk_image + phys_base;
1256                 initrd_end = initrd_start + sparc_ramdisk_size;
1257                 if (initrd_end > end_of_phys_memory) {
1258                         printk(KERN_CRIT "initrd extends beyond end of memory "
1259                                          "(0x%016lx > 0x%016lx)\ndisabling initrd\n",
1260                                initrd_end, end_of_phys_memory);
1261                         initrd_start = 0;
1262                 }
1263                 if (initrd_start) {
1264                         if (initrd_start >= (start_pfn << PAGE_SHIFT) &&
1265                             initrd_start < (start_pfn << PAGE_SHIFT) + 2 * PAGE_SIZE)
1266                                 bootmap_pfn = PAGE_ALIGN (initrd_end) >> PAGE_SHIFT;
1267                 }
1268         }
1269 #endif  
1270         /* Initialize the boot-time allocator. */
1271         max_pfn = max_low_pfn = end_pfn;
1272         min_low_pfn = pfn_base;
1273
1274 #ifdef CONFIG_DEBUG_BOOTMEM
1275         prom_printf("init_bootmem(min[%lx], bootmap[%lx], max[%lx])\n",
1276                     min_low_pfn, bootmap_pfn, max_low_pfn);
1277 #endif
1278         bootmap_size = init_bootmem_node(NODE_DATA(0), bootmap_pfn, pfn_base, end_pfn);
1279
1280         /* Now register the available physical memory with the
1281          * allocator.
1282          */
1283         for (i = 0; sp_banks[i].num_bytes != 0; i++) {
1284 #ifdef CONFIG_DEBUG_BOOTMEM
1285                 prom_printf("free_bootmem(sp_banks:%d): base[%lx] size[%lx]\n",
1286                             i, sp_banks[i].base_addr, sp_banks[i].num_bytes);
1287 #endif
1288                 free_bootmem(sp_banks[i].base_addr, sp_banks[i].num_bytes);
1289         }
1290
1291 #ifdef CONFIG_BLK_DEV_INITRD
1292         if (initrd_start) {
1293                 size = initrd_end - initrd_start;
1294
1295                 /* Resert the initrd image area. */
1296 #ifdef CONFIG_DEBUG_BOOTMEM
1297                 prom_printf("reserve_bootmem(initrd): base[%llx] size[%lx]\n",
1298                         initrd_start, initrd_end);
1299 #endif
1300                 reserve_bootmem(initrd_start, size);
1301                 *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
1302
1303                 initrd_start += PAGE_OFFSET;
1304                 initrd_end += PAGE_OFFSET;
1305         }
1306 #endif
1307         /* Reserve the kernel text/data/bss. */
1308 #ifdef CONFIG_DEBUG_BOOTMEM
1309         prom_printf("reserve_bootmem(kernel): base[%lx] size[%lx]\n", kern_base, kern_size);
1310 #endif
1311         reserve_bootmem(kern_base, kern_size);
1312         *pages_avail -= PAGE_ALIGN(kern_size) >> PAGE_SHIFT;
1313
1314         /* Reserve the bootmem map.   We do not account for it
1315          * in pages_avail because we will release that memory
1316          * in free_all_bootmem.
1317          */
1318         size = bootmap_size;
1319 #ifdef CONFIG_DEBUG_BOOTMEM
1320         prom_printf("reserve_bootmem(bootmap): base[%lx] size[%lx]\n",
1321                     (bootmap_pfn << PAGE_SHIFT), size);
1322 #endif
1323         reserve_bootmem((bootmap_pfn << PAGE_SHIFT), size);
1324         *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
1325
1326         return end_pfn;
1327 }
1328
1329 #ifdef CONFIG_DEBUG_PAGEALLOC
1330 static unsigned long kernel_map_range(unsigned long pstart, unsigned long pend, pgprot_t prot)
1331 {
1332         unsigned long vstart = PAGE_OFFSET + pstart;
1333         unsigned long vend = PAGE_OFFSET + pend;
1334         unsigned long alloc_bytes = 0UL;
1335
1336         if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
1337                 prom_printf("kernel_map: Unaligned sp_banks[%lx:%lx]\n",
1338                             vstart, vend);
1339                 prom_halt();
1340         }
1341
1342         while (vstart < vend) {
1343                 unsigned long this_end, paddr = __pa(vstart);
1344                 pgd_t *pgd = pgd_offset_k(vstart);
1345                 pud_t *pud;
1346                 pmd_t *pmd;
1347                 pte_t *pte;
1348
1349                 pud = pud_offset(pgd, vstart);
1350                 if (pud_none(*pud)) {
1351                         pmd_t *new;
1352
1353                         new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1354                         alloc_bytes += PAGE_SIZE;
1355                         pud_populate(&init_mm, pud, new);
1356                 }
1357
1358                 pmd = pmd_offset(pud, vstart);
1359                 if (!pmd_present(*pmd)) {
1360                         pte_t *new;
1361
1362                         new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1363                         alloc_bytes += PAGE_SIZE;
1364                         pmd_populate_kernel(&init_mm, pmd, new);
1365                 }
1366
1367                 pte = pte_offset_kernel(pmd, vstart);
1368                 this_end = (vstart + PMD_SIZE) & PMD_MASK;
1369                 if (this_end > vend)
1370                         this_end = vend;
1371
1372                 while (vstart < this_end) {
1373                         pte_val(*pte) = (paddr | pgprot_val(prot));
1374
1375                         vstart += PAGE_SIZE;
1376                         paddr += PAGE_SIZE;
1377                         pte++;
1378                 }
1379         }
1380
1381         return alloc_bytes;
1382 }
1383
1384 extern struct linux_mlist_p1275 *prom_ptot_ptr;
1385 extern unsigned int kvmap_linear_patch[1];
1386
1387 static void __init kernel_physical_mapping_init(void)
1388 {
1389         struct linux_mlist_p1275 *p = prom_ptot_ptr;
1390         unsigned long mem_alloced = 0UL;
1391
1392         while (p) {
1393                 unsigned long phys_start, phys_end;
1394
1395                 phys_start = p->start_adr;
1396                 phys_end = phys_start + p->num_bytes;
1397                 mem_alloced += kernel_map_range(phys_start, phys_end,
1398                                                 PAGE_KERNEL);
1399
1400                 p = p->theres_more;
1401         }
1402
1403         printk("Allocated %ld bytes for kernel page tables.\n",
1404                mem_alloced);
1405
1406         kvmap_linear_patch[0] = 0x01000000; /* nop */
1407         flushi(&kvmap_linear_patch[0]);
1408
1409         __flush_tlb_all();
1410 }
1411
1412 void kernel_map_pages(struct page *page, int numpages, int enable)
1413 {
1414         unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1415         unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1416
1417         kernel_map_range(phys_start, phys_end,
1418                          (enable ? PAGE_KERNEL : __pgprot(0)));
1419
1420         /* we should perform an IPI and flush all tlbs,
1421          * but that can deadlock->flush only current cpu.
1422          */
1423         __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1424                                  PAGE_OFFSET + phys_end);
1425 }
1426 #endif
1427
1428 /* paging_init() sets up the page tables */
1429
1430 extern void cheetah_ecache_flush_init(void);
1431
1432 static unsigned long last_valid_pfn;
1433 pgd_t swapper_pg_dir[2048];
1434
1435 void __init paging_init(void)
1436 {
1437         unsigned long end_pfn, pages_avail, shift;
1438         unsigned long real_end;
1439
1440         set_bit(0, mmu_context_bmap);
1441
1442         shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
1443
1444         real_end = (unsigned long)_end;
1445         if ((real_end > ((unsigned long)KERNBASE + 0x400000)))
1446                 bigkernel = 1;
1447         if ((real_end > ((unsigned long)KERNBASE + 0x800000))) {
1448                 prom_printf("paging_init: Kernel > 8MB, too large.\n");
1449                 prom_halt();
1450         }
1451
1452         /* Set kernel pgd to upper alias so physical page computations
1453          * work.
1454          */
1455         init_mm.pgd += ((shift) / (sizeof(pgd_t)));
1456         
1457         memset(swapper_low_pmd_dir, 0, sizeof(swapper_low_pmd_dir));
1458
1459         /* Now can init the kernel/bad page tables. */
1460         pud_set(pud_offset(&swapper_pg_dir[0], 0),
1461                 swapper_low_pmd_dir + (shift / sizeof(pgd_t)));
1462         
1463         swapper_pgd_zero = pgd_val(swapper_pg_dir[0]);
1464         
1465         /* Inherit non-locked OBP mappings. */
1466         inherit_prom_mappings();
1467         
1468         /* Ok, we can use our TLB miss and window trap handlers safely.
1469          * We need to do a quick peek here to see if we are on StarFire
1470          * or not, so setup_tba can setup the IRQ globals correctly (it
1471          * needs to get the hard smp processor id correctly).
1472          */
1473         {
1474                 extern void setup_tba(int);
1475                 setup_tba(this_is_starfire);
1476         }
1477
1478         inherit_locked_prom_mappings(1);
1479
1480         __flush_tlb_all();
1481
1482         /* Setup bootmem... */
1483         pages_avail = 0;
1484         last_valid_pfn = end_pfn = bootmem_init(&pages_avail);
1485
1486 #ifdef CONFIG_DEBUG_PAGEALLOC
1487         kernel_physical_mapping_init();
1488 #endif
1489
1490         {
1491                 unsigned long zones_size[MAX_NR_ZONES];
1492                 unsigned long zholes_size[MAX_NR_ZONES];
1493                 unsigned long npages;
1494                 int znum;
1495
1496                 for (znum = 0; znum < MAX_NR_ZONES; znum++)
1497                         zones_size[znum] = zholes_size[znum] = 0;
1498
1499                 npages = end_pfn - pfn_base;
1500                 zones_size[ZONE_DMA] = npages;
1501                 zholes_size[ZONE_DMA] = npages - pages_avail;
1502
1503                 free_area_init_node(0, &contig_page_data, zones_size,
1504                                     phys_base >> PAGE_SHIFT, zholes_size);
1505         }
1506
1507         device_scan();
1508 }
1509
1510 /* Ok, it seems that the prom can allocate some more memory chunks
1511  * as a side effect of some prom calls we perform during the
1512  * boot sequence.  My most likely theory is that it is from the
1513  * prom_set_traptable() call, and OBP is allocating a scratchpad
1514  * for saving client program register state etc.
1515  */
1516 static void __init sort_memlist(struct linux_mlist_p1275 *thislist)
1517 {
1518         int swapi = 0;
1519         int i, mitr;
1520         unsigned long tmpaddr, tmpsize;
1521         unsigned long lowest;
1522
1523         for (i = 0; thislist[i].theres_more != 0; i++) {
1524                 lowest = thislist[i].start_adr;
1525                 for (mitr = i+1; thislist[mitr-1].theres_more != 0; mitr++)
1526                         if (thislist[mitr].start_adr < lowest) {
1527                                 lowest = thislist[mitr].start_adr;
1528                                 swapi = mitr;
1529                         }
1530                 if (lowest == thislist[i].start_adr)
1531                         continue;
1532                 tmpaddr = thislist[swapi].start_adr;
1533                 tmpsize = thislist[swapi].num_bytes;
1534                 for (mitr = swapi; mitr > i; mitr--) {
1535                         thislist[mitr].start_adr = thislist[mitr-1].start_adr;
1536                         thislist[mitr].num_bytes = thislist[mitr-1].num_bytes;
1537                 }
1538                 thislist[i].start_adr = tmpaddr;
1539                 thislist[i].num_bytes = tmpsize;
1540         }
1541 }
1542
1543 void __init rescan_sp_banks(void)
1544 {
1545         struct linux_prom64_registers memlist[64];
1546         struct linux_mlist_p1275 avail[64], *mlist;
1547         unsigned long bytes, base_paddr;
1548         int num_regs, node = prom_finddevice("/memory");
1549         int i;
1550
1551         num_regs = prom_getproperty(node, "available",
1552                                     (char *) memlist, sizeof(memlist));
1553         num_regs = (num_regs / sizeof(struct linux_prom64_registers));
1554         for (i = 0; i < num_regs; i++) {
1555                 avail[i].start_adr = memlist[i].phys_addr;
1556                 avail[i].num_bytes = memlist[i].reg_size;
1557                 avail[i].theres_more = &avail[i + 1];
1558         }
1559         avail[i - 1].theres_more = NULL;
1560         sort_memlist(avail);
1561
1562         mlist = &avail[0];
1563         i = 0;
1564         bytes = mlist->num_bytes;
1565         base_paddr = mlist->start_adr;
1566   
1567         sp_banks[0].base_addr = base_paddr;
1568         sp_banks[0].num_bytes = bytes;
1569
1570         while (mlist->theres_more != NULL){
1571                 i++;
1572                 mlist = mlist->theres_more;
1573                 bytes = mlist->num_bytes;
1574                 if (i >= SPARC_PHYS_BANKS-1) {
1575                         printk ("The machine has more banks than "
1576                                 "this kernel can support\n"
1577                                 "Increase the SPARC_PHYS_BANKS "
1578                                 "setting (currently %d)\n",
1579                                 SPARC_PHYS_BANKS);
1580                         i = SPARC_PHYS_BANKS-1;
1581                         break;
1582                 }
1583     
1584                 sp_banks[i].base_addr = mlist->start_adr;
1585                 sp_banks[i].num_bytes = mlist->num_bytes;
1586         }
1587
1588         i++;
1589         sp_banks[i].base_addr = 0xdeadbeefbeefdeadUL;
1590         sp_banks[i].num_bytes = 0;
1591
1592         for (i = 0; sp_banks[i].num_bytes != 0; i++)
1593                 sp_banks[i].num_bytes &= PAGE_MASK;
1594 }
1595
1596 static void __init taint_real_pages(void)
1597 {
1598         struct sparc_phys_banks saved_sp_banks[SPARC_PHYS_BANKS];
1599         int i;
1600
1601         for (i = 0; i < SPARC_PHYS_BANKS; i++) {
1602                 saved_sp_banks[i].base_addr =
1603                         sp_banks[i].base_addr;
1604                 saved_sp_banks[i].num_bytes =
1605                         sp_banks[i].num_bytes;
1606         }
1607
1608         rescan_sp_banks();
1609
1610         /* Find changes discovered in the sp_bank rescan and
1611          * reserve the lost portions in the bootmem maps.
1612          */
1613         for (i = 0; saved_sp_banks[i].num_bytes; i++) {
1614                 unsigned long old_start, old_end;
1615
1616                 old_start = saved_sp_banks[i].base_addr;
1617                 old_end = old_start +
1618                         saved_sp_banks[i].num_bytes;
1619                 while (old_start < old_end) {
1620                         int n;
1621
1622                         for (n = 0; sp_banks[n].num_bytes; n++) {
1623                                 unsigned long new_start, new_end;
1624
1625                                 new_start = sp_banks[n].base_addr;
1626                                 new_end = new_start + sp_banks[n].num_bytes;
1627
1628                                 if (new_start <= old_start &&
1629                                     new_end >= (old_start + PAGE_SIZE)) {
1630                                         set_bit (old_start >> 22,
1631                                                  sparc64_valid_addr_bitmap);
1632                                         goto do_next_page;
1633                                 }
1634                         }
1635                         reserve_bootmem(old_start, PAGE_SIZE);
1636
1637                 do_next_page:
1638                         old_start += PAGE_SIZE;
1639                 }
1640         }
1641 }
1642
1643 void __init mem_init(void)
1644 {
1645         unsigned long codepages, datapages, initpages;
1646         unsigned long addr, last;
1647         int i;
1648
1649         i = last_valid_pfn >> ((22 - PAGE_SHIFT) + 6);
1650         i += 1;
1651         sparc64_valid_addr_bitmap = (unsigned long *) alloc_bootmem(i << 3);
1652         if (sparc64_valid_addr_bitmap == NULL) {
1653                 prom_printf("mem_init: Cannot alloc valid_addr_bitmap.\n");
1654                 prom_halt();
1655         }
1656         memset(sparc64_valid_addr_bitmap, 0, i << 3);
1657
1658         addr = PAGE_OFFSET + kern_base;
1659         last = PAGE_ALIGN(kern_size) + addr;
1660         while (addr < last) {
1661                 set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap);
1662                 addr += PAGE_SIZE;
1663         }
1664
1665         taint_real_pages();
1666
1667         max_mapnr = last_valid_pfn - pfn_base;
1668         high_memory = __va(last_valid_pfn << PAGE_SHIFT);
1669
1670 #ifdef CONFIG_DEBUG_BOOTMEM
1671         prom_printf("mem_init: Calling free_all_bootmem().\n");
1672 #endif
1673         totalram_pages = num_physpages = free_all_bootmem() - 1;
1674
1675         /*
1676          * Set up the zero page, mark it reserved, so that page count
1677          * is not manipulated when freeing the page from user ptes.
1678          */
1679         mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
1680         if (mem_map_zero == NULL) {
1681                 prom_printf("paging_init: Cannot alloc zero page.\n");
1682                 prom_halt();
1683         }
1684         SetPageReserved(mem_map_zero);
1685
1686         codepages = (((unsigned long) _etext) - ((unsigned long) _start));
1687         codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT;
1688         datapages = (((unsigned long) _edata) - ((unsigned long) _etext));
1689         datapages = PAGE_ALIGN(datapages) >> PAGE_SHIFT;
1690         initpages = (((unsigned long) __init_end) - ((unsigned long) __init_begin));
1691         initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT;
1692
1693         printk("Memory: %uk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n",
1694                nr_free_pages() << (PAGE_SHIFT-10),
1695                codepages << (PAGE_SHIFT-10),
1696                datapages << (PAGE_SHIFT-10), 
1697                initpages << (PAGE_SHIFT-10), 
1698                PAGE_OFFSET, (last_valid_pfn << PAGE_SHIFT));
1699
1700         if (tlb_type == cheetah || tlb_type == cheetah_plus)
1701                 cheetah_ecache_flush_init();
1702 }
1703
1704 void free_initmem(void)
1705 {
1706         unsigned long addr, initend;
1707
1708         /*
1709          * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
1710          */
1711         addr = PAGE_ALIGN((unsigned long)(__init_begin));
1712         initend = (unsigned long)(__init_end) & PAGE_MASK;
1713         for (; addr < initend; addr += PAGE_SIZE) {
1714                 unsigned long page;
1715                 struct page *p;
1716
1717                 page = (addr +
1718                         ((unsigned long) __va(kern_base)) -
1719                         ((unsigned long) KERNBASE));
1720                 memset((void *)addr, 0xcc, PAGE_SIZE);
1721                 p = virt_to_page(page);
1722
1723                 ClearPageReserved(p);
1724                 set_page_count(p, 1);
1725                 __free_page(p);
1726                 num_physpages++;
1727                 totalram_pages++;
1728         }
1729 }
1730
1731 #ifdef CONFIG_BLK_DEV_INITRD
1732 void free_initrd_mem(unsigned long start, unsigned long end)
1733 {
1734         if (start < end)
1735                 printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
1736         for (; start < end; start += PAGE_SIZE) {
1737                 struct page *p = virt_to_page(start);
1738
1739                 ClearPageReserved(p);
1740                 set_page_count(p, 1);
1741                 __free_page(p);
1742                 num_physpages++;
1743                 totalram_pages++;
1744         }
1745 }
1746 #endif