[SPARC64]: Correctable ECC errors cannot occur at trap level > 0.
[linux-2.6.git] / arch / sparc64 / mm / init.c
1 /*  $Id: init.c,v 1.209 2002/02/09 19:49:31 davem Exp $
2  *  arch/sparc64/mm/init.c
3  *
4  *  Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
5  *  Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
6  */
7  
8 #include <linux/config.h>
9 #include <linux/kernel.h>
10 #include <linux/sched.h>
11 #include <linux/string.h>
12 #include <linux/init.h>
13 #include <linux/bootmem.h>
14 #include <linux/mm.h>
15 #include <linux/hugetlb.h>
16 #include <linux/slab.h>
17 #include <linux/initrd.h>
18 #include <linux/swap.h>
19 #include <linux/pagemap.h>
20 #include <linux/fs.h>
21 #include <linux/seq_file.h>
22 #include <linux/kprobes.h>
23 #include <linux/cache.h>
24 #include <linux/sort.h>
25
26 #include <asm/head.h>
27 #include <asm/system.h>
28 #include <asm/page.h>
29 #include <asm/pgalloc.h>
30 #include <asm/pgtable.h>
31 #include <asm/oplib.h>
32 #include <asm/iommu.h>
33 #include <asm/io.h>
34 #include <asm/uaccess.h>
35 #include <asm/mmu_context.h>
36 #include <asm/tlbflush.h>
37 #include <asm/dma.h>
38 #include <asm/starfire.h>
39 #include <asm/tlb.h>
40 #include <asm/spitfire.h>
41 #include <asm/sections.h>
42 #include <asm/tsb.h>
43
44 extern void device_scan(void);
45
46 #define MAX_BANKS       32
47
48 static struct linux_prom64_registers pavail[MAX_BANKS] __initdata;
49 static struct linux_prom64_registers pavail_rescan[MAX_BANKS] __initdata;
50 static int pavail_ents __initdata;
51 static int pavail_rescan_ents __initdata;
52
53 static int cmp_p64(const void *a, const void *b)
54 {
55         const struct linux_prom64_registers *x = a, *y = b;
56
57         if (x->phys_addr > y->phys_addr)
58                 return 1;
59         if (x->phys_addr < y->phys_addr)
60                 return -1;
61         return 0;
62 }
63
64 static void __init read_obp_memory(const char *property,
65                                    struct linux_prom64_registers *regs,
66                                    int *num_ents)
67 {
68         int node = prom_finddevice("/memory");
69         int prop_size = prom_getproplen(node, property);
70         int ents, ret, i;
71
72         ents = prop_size / sizeof(struct linux_prom64_registers);
73         if (ents > MAX_BANKS) {
74                 prom_printf("The machine has more %s property entries than "
75                             "this kernel can support (%d).\n",
76                             property, MAX_BANKS);
77                 prom_halt();
78         }
79
80         ret = prom_getproperty(node, property, (char *) regs, prop_size);
81         if (ret == -1) {
82                 prom_printf("Couldn't get %s property from /memory.\n");
83                 prom_halt();
84         }
85
86         *num_ents = ents;
87
88         /* Sanitize what we got from the firmware, by page aligning
89          * everything.
90          */
91         for (i = 0; i < ents; i++) {
92                 unsigned long base, size;
93
94                 base = regs[i].phys_addr;
95                 size = regs[i].reg_size;
96
97                 size &= PAGE_MASK;
98                 if (base & ~PAGE_MASK) {
99                         unsigned long new_base = PAGE_ALIGN(base);
100
101                         size -= new_base - base;
102                         if ((long) size < 0L)
103                                 size = 0UL;
104                         base = new_base;
105                 }
106                 regs[i].phys_addr = base;
107                 regs[i].reg_size = size;
108         }
109         sort(regs, ents, sizeof(struct linux_prom64_registers),
110              cmp_p64, NULL);
111 }
112
113 unsigned long *sparc64_valid_addr_bitmap __read_mostly;
114
115 /* Ugly, but necessary... -DaveM */
116 unsigned long phys_base __read_mostly;
117 unsigned long kern_base __read_mostly;
118 unsigned long kern_size __read_mostly;
119 unsigned long pfn_base __read_mostly;
120
121 /* get_new_mmu_context() uses "cache + 1".  */
122 DEFINE_SPINLOCK(ctx_alloc_lock);
123 unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
124 #define CTX_BMAP_SLOTS (1UL << (CTX_NR_BITS - 6))
125 unsigned long mmu_context_bmap[CTX_BMAP_SLOTS];
126
127 /* References to special section boundaries */
128 extern char  _start[], _end[];
129
130 /* Initial ramdisk setup */
131 extern unsigned long sparc_ramdisk_image64;
132 extern unsigned int sparc_ramdisk_image;
133 extern unsigned int sparc_ramdisk_size;
134
135 struct page *mem_map_zero __read_mostly;
136
137 unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
138
139 unsigned long sparc64_kern_pri_context __read_mostly;
140 unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
141 unsigned long sparc64_kern_sec_context __read_mostly;
142
143 int bigkernel = 0;
144
145 kmem_cache_t *pgtable_cache __read_mostly;
146
147 static void zero_ctor(void *addr, kmem_cache_t *cache, unsigned long flags)
148 {
149         clear_page(addr);
150 }
151
152 void pgtable_cache_init(void)
153 {
154         pgtable_cache = kmem_cache_create("pgtable_cache",
155                                           PAGE_SIZE, PAGE_SIZE,
156                                           SLAB_HWCACHE_ALIGN |
157                                           SLAB_MUST_HWCACHE_ALIGN,
158                                           zero_ctor,
159                                           NULL);
160         if (!pgtable_cache) {
161                 prom_printf("pgtable_cache_init(): Could not create!\n");
162                 prom_halt();
163         }
164 }
165
166 #ifdef CONFIG_DEBUG_DCFLUSH
167 atomic_t dcpage_flushes = ATOMIC_INIT(0);
168 #ifdef CONFIG_SMP
169 atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
170 #endif
171 #endif
172
173 __inline__ void flush_dcache_page_impl(struct page *page)
174 {
175 #ifdef CONFIG_DEBUG_DCFLUSH
176         atomic_inc(&dcpage_flushes);
177 #endif
178
179 #ifdef DCACHE_ALIASING_POSSIBLE
180         __flush_dcache_page(page_address(page),
181                             ((tlb_type == spitfire) &&
182                              page_mapping(page) != NULL));
183 #else
184         if (page_mapping(page) != NULL &&
185             tlb_type == spitfire)
186                 __flush_icache_page(__pa(page_address(page)));
187 #endif
188 }
189
190 #define PG_dcache_dirty         PG_arch_1
191 #define PG_dcache_cpu_shift     24
192 #define PG_dcache_cpu_mask      (256 - 1)
193
194 #if NR_CPUS > 256
195 #error D-cache dirty tracking and thread_info->cpu need fixing for > 256 cpus
196 #endif
197
198 #define dcache_dirty_cpu(page) \
199         (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
200
201 static __inline__ void set_dcache_dirty(struct page *page, int this_cpu)
202 {
203         unsigned long mask = this_cpu;
204         unsigned long non_cpu_bits;
205
206         non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
207         mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
208
209         __asm__ __volatile__("1:\n\t"
210                              "ldx       [%2], %%g7\n\t"
211                              "and       %%g7, %1, %%g1\n\t"
212                              "or        %%g1, %0, %%g1\n\t"
213                              "casx      [%2], %%g7, %%g1\n\t"
214                              "cmp       %%g7, %%g1\n\t"
215                              "membar    #StoreLoad | #StoreStore\n\t"
216                              "bne,pn    %%xcc, 1b\n\t"
217                              " nop"
218                              : /* no outputs */
219                              : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
220                              : "g1", "g7");
221 }
222
223 static __inline__ void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
224 {
225         unsigned long mask = (1UL << PG_dcache_dirty);
226
227         __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
228                              "1:\n\t"
229                              "ldx       [%2], %%g7\n\t"
230                              "srlx      %%g7, %4, %%g1\n\t"
231                              "and       %%g1, %3, %%g1\n\t"
232                              "cmp       %%g1, %0\n\t"
233                              "bne,pn    %%icc, 2f\n\t"
234                              " andn     %%g7, %1, %%g1\n\t"
235                              "casx      [%2], %%g7, %%g1\n\t"
236                              "cmp       %%g7, %%g1\n\t"
237                              "membar    #StoreLoad | #StoreStore\n\t"
238                              "bne,pn    %%xcc, 1b\n\t"
239                              " nop\n"
240                              "2:"
241                              : /* no outputs */
242                              : "r" (cpu), "r" (mask), "r" (&page->flags),
243                                "i" (PG_dcache_cpu_mask),
244                                "i" (PG_dcache_cpu_shift)
245                              : "g1", "g7");
246 }
247
248 static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
249 {
250         unsigned long tsb_addr = (unsigned long) ent;
251
252         if (tlb_type == cheetah_plus)
253                 tsb_addr = __pa(tsb_addr);
254
255         __tsb_insert(tsb_addr, tag, pte);
256 }
257
258 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
259 {
260         struct mm_struct *mm;
261         struct page *page;
262         unsigned long pfn;
263         unsigned long pg_flags;
264         unsigned long mm_rss;
265
266         pfn = pte_pfn(pte);
267         if (pfn_valid(pfn) &&
268             (page = pfn_to_page(pfn), page_mapping(page)) &&
269             ((pg_flags = page->flags) & (1UL << PG_dcache_dirty))) {
270                 int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
271                            PG_dcache_cpu_mask);
272                 int this_cpu = get_cpu();
273
274                 /* This is just to optimize away some function calls
275                  * in the SMP case.
276                  */
277                 if (cpu == this_cpu)
278                         flush_dcache_page_impl(page);
279                 else
280                         smp_flush_dcache_page_impl(page, cpu);
281
282                 clear_dcache_dirty_cpu(page, cpu);
283
284                 put_cpu();
285         }
286
287         mm = vma->vm_mm;
288         mm_rss = get_mm_rss(mm);
289         if (mm_rss >= mm->context.tsb_rss_limit)
290                 tsb_grow(mm, mm_rss, GFP_ATOMIC);
291
292         if ((pte_val(pte) & _PAGE_ALL_SZ_BITS) == _PAGE_SZBITS) {
293                 struct tsb *tsb;
294                 unsigned long tag;
295
296                 tsb = &mm->context.tsb[(address >> PAGE_SHIFT) &
297                                        (mm->context.tsb_nentries - 1UL)];
298                 tag = (address >> 22UL) | CTX_HWBITS(mm->context) << 48UL;
299                 tsb_insert(tsb, tag, pte_val(pte));
300         }
301 }
302
303 void flush_dcache_page(struct page *page)
304 {
305         struct address_space *mapping;
306         int this_cpu;
307
308         /* Do not bother with the expensive D-cache flush if it
309          * is merely the zero page.  The 'bigcore' testcase in GDB
310          * causes this case to run millions of times.
311          */
312         if (page == ZERO_PAGE(0))
313                 return;
314
315         this_cpu = get_cpu();
316
317         mapping = page_mapping(page);
318         if (mapping && !mapping_mapped(mapping)) {
319                 int dirty = test_bit(PG_dcache_dirty, &page->flags);
320                 if (dirty) {
321                         int dirty_cpu = dcache_dirty_cpu(page);
322
323                         if (dirty_cpu == this_cpu)
324                                 goto out;
325                         smp_flush_dcache_page_impl(page, dirty_cpu);
326                 }
327                 set_dcache_dirty(page, this_cpu);
328         } else {
329                 /* We could delay the flush for the !page_mapping
330                  * case too.  But that case is for exec env/arg
331                  * pages and those are %99 certainly going to get
332                  * faulted into the tlb (and thus flushed) anyways.
333                  */
334                 flush_dcache_page_impl(page);
335         }
336
337 out:
338         put_cpu();
339 }
340
341 void __kprobes flush_icache_range(unsigned long start, unsigned long end)
342 {
343         /* Cheetah has coherent I-cache. */
344         if (tlb_type == spitfire) {
345                 unsigned long kaddr;
346
347                 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE)
348                         __flush_icache_page(__get_phys(kaddr));
349         }
350 }
351
352 unsigned long page_to_pfn(struct page *page)
353 {
354         return (unsigned long) ((page - mem_map) + pfn_base);
355 }
356
357 struct page *pfn_to_page(unsigned long pfn)
358 {
359         return (mem_map + (pfn - pfn_base));
360 }
361
362 void show_mem(void)
363 {
364         printk("Mem-info:\n");
365         show_free_areas();
366         printk("Free swap:       %6ldkB\n",
367                nr_swap_pages << (PAGE_SHIFT-10));
368         printk("%ld pages of RAM\n", num_physpages);
369         printk("%d free pages\n", nr_free_pages());
370 }
371
372 void mmu_info(struct seq_file *m)
373 {
374         if (tlb_type == cheetah)
375                 seq_printf(m, "MMU Type\t: Cheetah\n");
376         else if (tlb_type == cheetah_plus)
377                 seq_printf(m, "MMU Type\t: Cheetah+\n");
378         else if (tlb_type == spitfire)
379                 seq_printf(m, "MMU Type\t: Spitfire\n");
380         else
381                 seq_printf(m, "MMU Type\t: ???\n");
382
383 #ifdef CONFIG_DEBUG_DCFLUSH
384         seq_printf(m, "DCPageFlushes\t: %d\n",
385                    atomic_read(&dcpage_flushes));
386 #ifdef CONFIG_SMP
387         seq_printf(m, "DCPageFlushesXC\t: %d\n",
388                    atomic_read(&dcpage_flushes_xcall));
389 #endif /* CONFIG_SMP */
390 #endif /* CONFIG_DEBUG_DCFLUSH */
391 }
392
393 struct linux_prom_translation {
394         unsigned long virt;
395         unsigned long size;
396         unsigned long data;
397 };
398
399 /* Exported for kernel TLB miss handling in ktlb.S */
400 struct linux_prom_translation prom_trans[512] __read_mostly;
401 unsigned int prom_trans_ents __read_mostly;
402
403 extern unsigned long prom_boot_page;
404 extern void prom_remap(unsigned long physpage, unsigned long virtpage, int mmu_ihandle);
405 extern int prom_get_mmu_ihandle(void);
406 extern void register_prom_callbacks(void);
407
408 /* Exported for SMP bootup purposes. */
409 unsigned long kern_locked_tte_data;
410
411 /*
412  * Translate PROM's mapping we capture at boot time into physical address.
413  * The second parameter is only set from prom_callback() invocations.
414  */
415 unsigned long prom_virt_to_phys(unsigned long promva, int *error)
416 {
417         int i;
418
419         for (i = 0; i < prom_trans_ents; i++) {
420                 struct linux_prom_translation *p = &prom_trans[i];
421
422                 if (promva >= p->virt &&
423                     promva < (p->virt + p->size)) {
424                         unsigned long base = p->data & _PAGE_PADDR;
425
426                         if (error)
427                                 *error = 0;
428                         return base + (promva & (8192 - 1));
429                 }
430         }
431         if (error)
432                 *error = 1;
433         return 0UL;
434 }
435
436 /* The obp translations are saved based on 8k pagesize, since obp can
437  * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
438  * HI_OBP_ADDRESS range are handled in ktlb.S.
439  */
440 static inline int in_obp_range(unsigned long vaddr)
441 {
442         return (vaddr >= LOW_OBP_ADDRESS &&
443                 vaddr < HI_OBP_ADDRESS);
444 }
445
446 static int cmp_ptrans(const void *a, const void *b)
447 {
448         const struct linux_prom_translation *x = a, *y = b;
449
450         if (x->virt > y->virt)
451                 return 1;
452         if (x->virt < y->virt)
453                 return -1;
454         return 0;
455 }
456
457 /* Read OBP translations property into 'prom_trans[]'.  */
458 static void __init read_obp_translations(void)
459 {
460         int n, node, ents, first, last, i;
461
462         node = prom_finddevice("/virtual-memory");
463         n = prom_getproplen(node, "translations");
464         if (unlikely(n == 0 || n == -1)) {
465                 prom_printf("prom_mappings: Couldn't get size.\n");
466                 prom_halt();
467         }
468         if (unlikely(n > sizeof(prom_trans))) {
469                 prom_printf("prom_mappings: Size %Zd is too big.\n", n);
470                 prom_halt();
471         }
472
473         if ((n = prom_getproperty(node, "translations",
474                                   (char *)&prom_trans[0],
475                                   sizeof(prom_trans))) == -1) {
476                 prom_printf("prom_mappings: Couldn't get property.\n");
477                 prom_halt();
478         }
479
480         n = n / sizeof(struct linux_prom_translation);
481
482         ents = n;
483
484         sort(prom_trans, ents, sizeof(struct linux_prom_translation),
485              cmp_ptrans, NULL);
486
487         /* Now kick out all the non-OBP entries.  */
488         for (i = 0; i < ents; i++) {
489                 if (in_obp_range(prom_trans[i].virt))
490                         break;
491         }
492         first = i;
493         for (; i < ents; i++) {
494                 if (!in_obp_range(prom_trans[i].virt))
495                         break;
496         }
497         last = i;
498
499         for (i = 0; i < (last - first); i++) {
500                 struct linux_prom_translation *src = &prom_trans[i + first];
501                 struct linux_prom_translation *dest = &prom_trans[i];
502
503                 *dest = *src;
504         }
505         for (; i < ents; i++) {
506                 struct linux_prom_translation *dest = &prom_trans[i];
507                 dest->virt = dest->size = dest->data = 0x0UL;
508         }
509
510         prom_trans_ents = last - first;
511
512         if (tlb_type == spitfire) {
513                 /* Clear diag TTE bits. */
514                 for (i = 0; i < prom_trans_ents; i++)
515                         prom_trans[i].data &= ~0x0003fe0000000000UL;
516         }
517 }
518
519 static void __init remap_kernel(void)
520 {
521         unsigned long phys_page, tte_vaddr, tte_data;
522         int tlb_ent = sparc64_highest_locked_tlbent();
523
524         tte_vaddr = (unsigned long) KERNBASE;
525         phys_page = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
526         tte_data = (phys_page | (_PAGE_VALID | _PAGE_SZ4MB |
527                                  _PAGE_CP | _PAGE_CV | _PAGE_P |
528                                  _PAGE_L | _PAGE_W));
529
530         kern_locked_tte_data = tte_data;
531
532         /* Now lock us into the TLBs via OBP. */
533         prom_dtlb_load(tlb_ent, tte_data, tte_vaddr);
534         prom_itlb_load(tlb_ent, tte_data, tte_vaddr);
535         if (bigkernel) {
536                 tlb_ent -= 1;
537                 prom_dtlb_load(tlb_ent,
538                                tte_data + 0x400000, 
539                                tte_vaddr + 0x400000);
540                 prom_itlb_load(tlb_ent,
541                                tte_data + 0x400000, 
542                                tte_vaddr + 0x400000);
543         }
544         sparc64_highest_unlocked_tlb_ent = tlb_ent - 1;
545         if (tlb_type == cheetah_plus) {
546                 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
547                                             CTX_CHEETAH_PLUS_NUC);
548                 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
549                 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
550         }
551 }
552
553
554 static void __init inherit_prom_mappings(void)
555 {
556         read_obp_translations();
557
558         /* Now fixup OBP's idea about where we really are mapped. */
559         prom_printf("Remapping the kernel... ");
560         remap_kernel();
561         prom_printf("done.\n");
562
563         prom_printf("Registering callbacks... ");
564         register_prom_callbacks();
565         prom_printf("done.\n");
566 }
567
568 void prom_world(int enter)
569 {
570         if (!enter)
571                 set_fs((mm_segment_t) { get_thread_current_ds() });
572
573         __asm__ __volatile__("flushw");
574 }
575
576 #ifdef DCACHE_ALIASING_POSSIBLE
577 void __flush_dcache_range(unsigned long start, unsigned long end)
578 {
579         unsigned long va;
580
581         if (tlb_type == spitfire) {
582                 int n = 0;
583
584                 for (va = start; va < end; va += 32) {
585                         spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
586                         if (++n >= 512)
587                                 break;
588                 }
589         } else {
590                 start = __pa(start);
591                 end = __pa(end);
592                 for (va = start; va < end; va += 32)
593                         __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
594                                              "membar #Sync"
595                                              : /* no outputs */
596                                              : "r" (va),
597                                                "i" (ASI_DCACHE_INVALIDATE));
598         }
599 }
600 #endif /* DCACHE_ALIASING_POSSIBLE */
601
602 /* If not locked, zap it. */
603 void __flush_tlb_all(void)
604 {
605         unsigned long pstate;
606         int i;
607
608         __asm__ __volatile__("flushw\n\t"
609                              "rdpr      %%pstate, %0\n\t"
610                              "wrpr      %0, %1, %%pstate"
611                              : "=r" (pstate)
612                              : "i" (PSTATE_IE));
613         if (tlb_type == spitfire) {
614                 for (i = 0; i < 64; i++) {
615                         /* Spitfire Errata #32 workaround */
616                         /* NOTE: Always runs on spitfire, so no
617                          *       cheetah+ page size encodings.
618                          */
619                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
620                                              "flush     %%g6"
621                                              : /* No outputs */
622                                              : "r" (0),
623                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
624
625                         if (!(spitfire_get_dtlb_data(i) & _PAGE_L)) {
626                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
627                                                      "membar #Sync"
628                                                      : /* no outputs */
629                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
630                                 spitfire_put_dtlb_data(i, 0x0UL);
631                         }
632
633                         /* Spitfire Errata #32 workaround */
634                         /* NOTE: Always runs on spitfire, so no
635                          *       cheetah+ page size encodings.
636                          */
637                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
638                                              "flush     %%g6"
639                                              : /* No outputs */
640                                              : "r" (0),
641                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
642
643                         if (!(spitfire_get_itlb_data(i) & _PAGE_L)) {
644                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
645                                                      "membar #Sync"
646                                                      : /* no outputs */
647                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
648                                 spitfire_put_itlb_data(i, 0x0UL);
649                         }
650                 }
651         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
652                 cheetah_flush_dtlb_all();
653                 cheetah_flush_itlb_all();
654         }
655         __asm__ __volatile__("wrpr      %0, 0, %%pstate"
656                              : : "r" (pstate));
657 }
658
659 /* Caller does TLB context flushing on local CPU if necessary.
660  * The caller also ensures that CTX_VALID(mm->context) is false.
661  *
662  * We must be careful about boundary cases so that we never
663  * let the user have CTX 0 (nucleus) or we ever use a CTX
664  * version of zero (and thus NO_CONTEXT would not be caught
665  * by version mis-match tests in mmu_context.h).
666  */
667 void get_new_mmu_context(struct mm_struct *mm)
668 {
669         unsigned long ctx, new_ctx;
670         unsigned long orig_pgsz_bits;
671         
672
673         spin_lock(&ctx_alloc_lock);
674         orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
675         ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
676         new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
677         if (new_ctx >= (1 << CTX_NR_BITS)) {
678                 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
679                 if (new_ctx >= ctx) {
680                         int i;
681                         new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
682                                 CTX_FIRST_VERSION;
683                         if (new_ctx == 1)
684                                 new_ctx = CTX_FIRST_VERSION;
685
686                         /* Don't call memset, for 16 entries that's just
687                          * plain silly...
688                          */
689                         mmu_context_bmap[0] = 3;
690                         mmu_context_bmap[1] = 0;
691                         mmu_context_bmap[2] = 0;
692                         mmu_context_bmap[3] = 0;
693                         for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
694                                 mmu_context_bmap[i + 0] = 0;
695                                 mmu_context_bmap[i + 1] = 0;
696                                 mmu_context_bmap[i + 2] = 0;
697                                 mmu_context_bmap[i + 3] = 0;
698                         }
699                         goto out;
700                 }
701         }
702         mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
703         new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
704 out:
705         tlb_context_cache = new_ctx;
706         mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
707         spin_unlock(&ctx_alloc_lock);
708 }
709
710 void sparc_ultra_dump_itlb(void)
711 {
712         int slot;
713
714         if (tlb_type == spitfire) {
715                 printk ("Contents of itlb: ");
716                 for (slot = 0; slot < 14; slot++) printk ("    ");
717                 printk ("%2x:%016lx,%016lx\n",
718                         0,
719                         spitfire_get_itlb_tag(0), spitfire_get_itlb_data(0));
720                 for (slot = 1; slot < 64; slot+=3) {
721                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n", 
722                                 slot,
723                                 spitfire_get_itlb_tag(slot), spitfire_get_itlb_data(slot),
724                                 slot+1,
725                                 spitfire_get_itlb_tag(slot+1), spitfire_get_itlb_data(slot+1),
726                                 slot+2,
727                                 spitfire_get_itlb_tag(slot+2), spitfire_get_itlb_data(slot+2));
728                 }
729         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
730                 printk ("Contents of itlb0:\n");
731                 for (slot = 0; slot < 16; slot+=2) {
732                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
733                                 slot,
734                                 cheetah_get_litlb_tag(slot), cheetah_get_litlb_data(slot),
735                                 slot+1,
736                                 cheetah_get_litlb_tag(slot+1), cheetah_get_litlb_data(slot+1));
737                 }
738                 printk ("Contents of itlb2:\n");
739                 for (slot = 0; slot < 128; slot+=2) {
740                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
741                                 slot,
742                                 cheetah_get_itlb_tag(slot), cheetah_get_itlb_data(slot),
743                                 slot+1,
744                                 cheetah_get_itlb_tag(slot+1), cheetah_get_itlb_data(slot+1));
745                 }
746         }
747 }
748
749 void sparc_ultra_dump_dtlb(void)
750 {
751         int slot;
752
753         if (tlb_type == spitfire) {
754                 printk ("Contents of dtlb: ");
755                 for (slot = 0; slot < 14; slot++) printk ("    ");
756                 printk ("%2x:%016lx,%016lx\n", 0,
757                         spitfire_get_dtlb_tag(0), spitfire_get_dtlb_data(0));
758                 for (slot = 1; slot < 64; slot+=3) {
759                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n", 
760                                 slot,
761                                 spitfire_get_dtlb_tag(slot), spitfire_get_dtlb_data(slot),
762                                 slot+1,
763                                 spitfire_get_dtlb_tag(slot+1), spitfire_get_dtlb_data(slot+1),
764                                 slot+2,
765                                 spitfire_get_dtlb_tag(slot+2), spitfire_get_dtlb_data(slot+2));
766                 }
767         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
768                 printk ("Contents of dtlb0:\n");
769                 for (slot = 0; slot < 16; slot+=2) {
770                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
771                                 slot,
772                                 cheetah_get_ldtlb_tag(slot), cheetah_get_ldtlb_data(slot),
773                                 slot+1,
774                                 cheetah_get_ldtlb_tag(slot+1), cheetah_get_ldtlb_data(slot+1));
775                 }
776                 printk ("Contents of dtlb2:\n");
777                 for (slot = 0; slot < 512; slot+=2) {
778                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
779                                 slot,
780                                 cheetah_get_dtlb_tag(slot, 2), cheetah_get_dtlb_data(slot, 2),
781                                 slot+1,
782                                 cheetah_get_dtlb_tag(slot+1, 2), cheetah_get_dtlb_data(slot+1, 2));
783                 }
784                 if (tlb_type == cheetah_plus) {
785                         printk ("Contents of dtlb3:\n");
786                         for (slot = 0; slot < 512; slot+=2) {
787                                 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
788                                         slot,
789                                         cheetah_get_dtlb_tag(slot, 3), cheetah_get_dtlb_data(slot, 3),
790                                         slot+1,
791                                         cheetah_get_dtlb_tag(slot+1, 3), cheetah_get_dtlb_data(slot+1, 3));
792                         }
793                 }
794         }
795 }
796
797 static inline void spitfire_errata32(void)
798 {
799         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
800                              "flush     %%g6"
801                              : /* No outputs */
802                              : "r" (0),
803                                "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
804 }
805
806 extern unsigned long cmdline_memory_size;
807
808 unsigned long __init bootmem_init(unsigned long *pages_avail)
809 {
810         unsigned long bootmap_size, start_pfn, end_pfn;
811         unsigned long end_of_phys_memory = 0UL;
812         unsigned long bootmap_pfn, bytes_avail, size;
813         int i;
814
815 #ifdef CONFIG_DEBUG_BOOTMEM
816         prom_printf("bootmem_init: Scan pavail, ");
817 #endif
818
819         bytes_avail = 0UL;
820         for (i = 0; i < pavail_ents; i++) {
821                 end_of_phys_memory = pavail[i].phys_addr +
822                         pavail[i].reg_size;
823                 bytes_avail += pavail[i].reg_size;
824                 if (cmdline_memory_size) {
825                         if (bytes_avail > cmdline_memory_size) {
826                                 unsigned long slack = bytes_avail - cmdline_memory_size;
827
828                                 bytes_avail -= slack;
829                                 end_of_phys_memory -= slack;
830
831                                 pavail[i].reg_size -= slack;
832                                 if ((long)pavail[i].reg_size <= 0L) {
833                                         pavail[i].phys_addr = 0xdeadbeefUL;
834                                         pavail[i].reg_size = 0UL;
835                                         pavail_ents = i;
836                                 } else {
837                                         pavail[i+1].reg_size = 0Ul;
838                                         pavail[i+1].phys_addr = 0xdeadbeefUL;
839                                         pavail_ents = i + 1;
840                                 }
841                                 break;
842                         }
843                 }
844         }
845
846         *pages_avail = bytes_avail >> PAGE_SHIFT;
847
848         /* Start with page aligned address of last symbol in kernel
849          * image.  The kernel is hard mapped below PAGE_OFFSET in a
850          * 4MB locked TLB translation.
851          */
852         start_pfn = PAGE_ALIGN(kern_base + kern_size) >> PAGE_SHIFT;
853
854         bootmap_pfn = start_pfn;
855
856         end_pfn = end_of_phys_memory >> PAGE_SHIFT;
857
858 #ifdef CONFIG_BLK_DEV_INITRD
859         /* Now have to check initial ramdisk, so that bootmap does not overwrite it */
860         if (sparc_ramdisk_image || sparc_ramdisk_image64) {
861                 unsigned long ramdisk_image = sparc_ramdisk_image ?
862                         sparc_ramdisk_image : sparc_ramdisk_image64;
863                 if (ramdisk_image >= (unsigned long)_end - 2 * PAGE_SIZE)
864                         ramdisk_image -= KERNBASE;
865                 initrd_start = ramdisk_image + phys_base;
866                 initrd_end = initrd_start + sparc_ramdisk_size;
867                 if (initrd_end > end_of_phys_memory) {
868                         printk(KERN_CRIT "initrd extends beyond end of memory "
869                                          "(0x%016lx > 0x%016lx)\ndisabling initrd\n",
870                                initrd_end, end_of_phys_memory);
871                         initrd_start = 0;
872                 }
873                 if (initrd_start) {
874                         if (initrd_start >= (start_pfn << PAGE_SHIFT) &&
875                             initrd_start < (start_pfn << PAGE_SHIFT) + 2 * PAGE_SIZE)
876                                 bootmap_pfn = PAGE_ALIGN (initrd_end) >> PAGE_SHIFT;
877                 }
878         }
879 #endif  
880         /* Initialize the boot-time allocator. */
881         max_pfn = max_low_pfn = end_pfn;
882         min_low_pfn = pfn_base;
883
884 #ifdef CONFIG_DEBUG_BOOTMEM
885         prom_printf("init_bootmem(min[%lx], bootmap[%lx], max[%lx])\n",
886                     min_low_pfn, bootmap_pfn, max_low_pfn);
887 #endif
888         bootmap_size = init_bootmem_node(NODE_DATA(0), bootmap_pfn, pfn_base, end_pfn);
889
890         /* Now register the available physical memory with the
891          * allocator.
892          */
893         for (i = 0; i < pavail_ents; i++) {
894 #ifdef CONFIG_DEBUG_BOOTMEM
895                 prom_printf("free_bootmem(pavail:%d): base[%lx] size[%lx]\n",
896                             i, pavail[i].phys_addr, pavail[i].reg_size);
897 #endif
898                 free_bootmem(pavail[i].phys_addr, pavail[i].reg_size);
899         }
900
901 #ifdef CONFIG_BLK_DEV_INITRD
902         if (initrd_start) {
903                 size = initrd_end - initrd_start;
904
905                 /* Resert the initrd image area. */
906 #ifdef CONFIG_DEBUG_BOOTMEM
907                 prom_printf("reserve_bootmem(initrd): base[%llx] size[%lx]\n",
908                         initrd_start, initrd_end);
909 #endif
910                 reserve_bootmem(initrd_start, size);
911                 *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
912
913                 initrd_start += PAGE_OFFSET;
914                 initrd_end += PAGE_OFFSET;
915         }
916 #endif
917         /* Reserve the kernel text/data/bss. */
918 #ifdef CONFIG_DEBUG_BOOTMEM
919         prom_printf("reserve_bootmem(kernel): base[%lx] size[%lx]\n", kern_base, kern_size);
920 #endif
921         reserve_bootmem(kern_base, kern_size);
922         *pages_avail -= PAGE_ALIGN(kern_size) >> PAGE_SHIFT;
923
924         /* Reserve the bootmem map.   We do not account for it
925          * in pages_avail because we will release that memory
926          * in free_all_bootmem.
927          */
928         size = bootmap_size;
929 #ifdef CONFIG_DEBUG_BOOTMEM
930         prom_printf("reserve_bootmem(bootmap): base[%lx] size[%lx]\n",
931                     (bootmap_pfn << PAGE_SHIFT), size);
932 #endif
933         reserve_bootmem((bootmap_pfn << PAGE_SHIFT), size);
934         *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
935
936         return end_pfn;
937 }
938
939 #ifdef CONFIG_DEBUG_PAGEALLOC
940 static unsigned long kernel_map_range(unsigned long pstart, unsigned long pend, pgprot_t prot)
941 {
942         unsigned long vstart = PAGE_OFFSET + pstart;
943         unsigned long vend = PAGE_OFFSET + pend;
944         unsigned long alloc_bytes = 0UL;
945
946         if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
947                 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
948                             vstart, vend);
949                 prom_halt();
950         }
951
952         while (vstart < vend) {
953                 unsigned long this_end, paddr = __pa(vstart);
954                 pgd_t *pgd = pgd_offset_k(vstart);
955                 pud_t *pud;
956                 pmd_t *pmd;
957                 pte_t *pte;
958
959                 pud = pud_offset(pgd, vstart);
960                 if (pud_none(*pud)) {
961                         pmd_t *new;
962
963                         new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
964                         alloc_bytes += PAGE_SIZE;
965                         pud_populate(&init_mm, pud, new);
966                 }
967
968                 pmd = pmd_offset(pud, vstart);
969                 if (!pmd_present(*pmd)) {
970                         pte_t *new;
971
972                         new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
973                         alloc_bytes += PAGE_SIZE;
974                         pmd_populate_kernel(&init_mm, pmd, new);
975                 }
976
977                 pte = pte_offset_kernel(pmd, vstart);
978                 this_end = (vstart + PMD_SIZE) & PMD_MASK;
979                 if (this_end > vend)
980                         this_end = vend;
981
982                 while (vstart < this_end) {
983                         pte_val(*pte) = (paddr | pgprot_val(prot));
984
985                         vstart += PAGE_SIZE;
986                         paddr += PAGE_SIZE;
987                         pte++;
988                 }
989         }
990
991         return alloc_bytes;
992 }
993
994 static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
995 static int pall_ents __initdata;
996
997 extern unsigned int kvmap_linear_patch[1];
998
999 static void __init kernel_physical_mapping_init(void)
1000 {
1001         unsigned long i, mem_alloced = 0UL;
1002
1003         read_obp_memory("reg", &pall[0], &pall_ents);
1004
1005         for (i = 0; i < pall_ents; i++) {
1006                 unsigned long phys_start, phys_end;
1007
1008                 phys_start = pall[i].phys_addr;
1009                 phys_end = phys_start + pall[i].reg_size;
1010                 mem_alloced += kernel_map_range(phys_start, phys_end,
1011                                                 PAGE_KERNEL);
1012         }
1013
1014         printk("Allocated %ld bytes for kernel page tables.\n",
1015                mem_alloced);
1016
1017         kvmap_linear_patch[0] = 0x01000000; /* nop */
1018         flushi(&kvmap_linear_patch[0]);
1019
1020         __flush_tlb_all();
1021 }
1022
1023 void kernel_map_pages(struct page *page, int numpages, int enable)
1024 {
1025         unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1026         unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1027
1028         kernel_map_range(phys_start, phys_end,
1029                          (enable ? PAGE_KERNEL : __pgprot(0)));
1030
1031         flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1032                                PAGE_OFFSET + phys_end);
1033
1034         /* we should perform an IPI and flush all tlbs,
1035          * but that can deadlock->flush only current cpu.
1036          */
1037         __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1038                                  PAGE_OFFSET + phys_end);
1039 }
1040 #endif
1041
1042 unsigned long __init find_ecache_flush_span(unsigned long size)
1043 {
1044         int i;
1045
1046         for (i = 0; i < pavail_ents; i++) {
1047                 if (pavail[i].reg_size >= size)
1048                         return pavail[i].phys_addr;
1049         }
1050
1051         return ~0UL;
1052 }
1053
1054 static void __init tsb_phys_patch(void)
1055 {
1056         struct tsb_phys_patch_entry *p;
1057
1058         p = &__tsb_phys_patch;
1059         while (p < &__tsb_phys_patch_end) {
1060                 unsigned long addr = p->addr;
1061
1062                 *(unsigned int *) addr = p->insn;
1063                 wmb();
1064                 __asm__ __volatile__("flush     %0"
1065                                      : /* no outputs */
1066                                      : "r" (addr));
1067
1068                 p++;
1069         }
1070 }
1071
1072 /* paging_init() sets up the page tables */
1073
1074 extern void cheetah_ecache_flush_init(void);
1075
1076 static unsigned long last_valid_pfn;
1077 pgd_t swapper_pg_dir[2048];
1078
1079 void __init paging_init(void)
1080 {
1081         unsigned long end_pfn, pages_avail, shift;
1082         unsigned long real_end, i;
1083
1084         if (tlb_type == cheetah_plus)
1085                 tsb_phys_patch();
1086
1087         /* Find available physical memory... */
1088         read_obp_memory("available", &pavail[0], &pavail_ents);
1089
1090         phys_base = 0xffffffffffffffffUL;
1091         for (i = 0; i < pavail_ents; i++)
1092                 phys_base = min(phys_base, pavail[i].phys_addr);
1093
1094         pfn_base = phys_base >> PAGE_SHIFT;
1095
1096         kern_base = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
1097         kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
1098
1099         set_bit(0, mmu_context_bmap);
1100
1101         shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
1102
1103         real_end = (unsigned long)_end;
1104         if ((real_end > ((unsigned long)KERNBASE + 0x400000)))
1105                 bigkernel = 1;
1106         if ((real_end > ((unsigned long)KERNBASE + 0x800000))) {
1107                 prom_printf("paging_init: Kernel > 8MB, too large.\n");
1108                 prom_halt();
1109         }
1110
1111         /* Set kernel pgd to upper alias so physical page computations
1112          * work.
1113          */
1114         init_mm.pgd += ((shift) / (sizeof(pgd_t)));
1115         
1116         memset(swapper_low_pmd_dir, 0, sizeof(swapper_low_pmd_dir));
1117
1118         /* Now can init the kernel/bad page tables. */
1119         pud_set(pud_offset(&swapper_pg_dir[0], 0),
1120                 swapper_low_pmd_dir + (shift / sizeof(pgd_t)));
1121         
1122         inherit_prom_mappings();
1123         
1124         /* Ok, we can use our TLB miss and window trap handlers safely.  */
1125         setup_tba();
1126
1127         __flush_tlb_all();
1128
1129         /* Setup bootmem... */
1130         pages_avail = 0;
1131         last_valid_pfn = end_pfn = bootmem_init(&pages_avail);
1132
1133 #ifdef CONFIG_DEBUG_PAGEALLOC
1134         kernel_physical_mapping_init();
1135 #endif
1136
1137         {
1138                 unsigned long zones_size[MAX_NR_ZONES];
1139                 unsigned long zholes_size[MAX_NR_ZONES];
1140                 unsigned long npages;
1141                 int znum;
1142
1143                 for (znum = 0; znum < MAX_NR_ZONES; znum++)
1144                         zones_size[znum] = zholes_size[znum] = 0;
1145
1146                 npages = end_pfn - pfn_base;
1147                 zones_size[ZONE_DMA] = npages;
1148                 zholes_size[ZONE_DMA] = npages - pages_avail;
1149
1150                 free_area_init_node(0, &contig_page_data, zones_size,
1151                                     phys_base >> PAGE_SHIFT, zholes_size);
1152         }
1153
1154         device_scan();
1155 }
1156
1157 static void __init taint_real_pages(void)
1158 {
1159         int i;
1160
1161         read_obp_memory("available", &pavail_rescan[0], &pavail_rescan_ents);
1162
1163         /* Find changes discovered in the physmem available rescan and
1164          * reserve the lost portions in the bootmem maps.
1165          */
1166         for (i = 0; i < pavail_ents; i++) {
1167                 unsigned long old_start, old_end;
1168
1169                 old_start = pavail[i].phys_addr;
1170                 old_end = old_start +
1171                         pavail[i].reg_size;
1172                 while (old_start < old_end) {
1173                         int n;
1174
1175                         for (n = 0; pavail_rescan_ents; n++) {
1176                                 unsigned long new_start, new_end;
1177
1178                                 new_start = pavail_rescan[n].phys_addr;
1179                                 new_end = new_start +
1180                                         pavail_rescan[n].reg_size;
1181
1182                                 if (new_start <= old_start &&
1183                                     new_end >= (old_start + PAGE_SIZE)) {
1184                                         set_bit(old_start >> 22,
1185                                                 sparc64_valid_addr_bitmap);
1186                                         goto do_next_page;
1187                                 }
1188                         }
1189                         reserve_bootmem(old_start, PAGE_SIZE);
1190
1191                 do_next_page:
1192                         old_start += PAGE_SIZE;
1193                 }
1194         }
1195 }
1196
1197 void __init mem_init(void)
1198 {
1199         unsigned long codepages, datapages, initpages;
1200         unsigned long addr, last;
1201         int i;
1202
1203         i = last_valid_pfn >> ((22 - PAGE_SHIFT) + 6);
1204         i += 1;
1205         sparc64_valid_addr_bitmap = (unsigned long *) alloc_bootmem(i << 3);
1206         if (sparc64_valid_addr_bitmap == NULL) {
1207                 prom_printf("mem_init: Cannot alloc valid_addr_bitmap.\n");
1208                 prom_halt();
1209         }
1210         memset(sparc64_valid_addr_bitmap, 0, i << 3);
1211
1212         addr = PAGE_OFFSET + kern_base;
1213         last = PAGE_ALIGN(kern_size) + addr;
1214         while (addr < last) {
1215                 set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap);
1216                 addr += PAGE_SIZE;
1217         }
1218
1219         taint_real_pages();
1220
1221         max_mapnr = last_valid_pfn - pfn_base;
1222         high_memory = __va(last_valid_pfn << PAGE_SHIFT);
1223
1224 #ifdef CONFIG_DEBUG_BOOTMEM
1225         prom_printf("mem_init: Calling free_all_bootmem().\n");
1226 #endif
1227         totalram_pages = num_physpages = free_all_bootmem() - 1;
1228
1229         /*
1230          * Set up the zero page, mark it reserved, so that page count
1231          * is not manipulated when freeing the page from user ptes.
1232          */
1233         mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
1234         if (mem_map_zero == NULL) {
1235                 prom_printf("paging_init: Cannot alloc zero page.\n");
1236                 prom_halt();
1237         }
1238         SetPageReserved(mem_map_zero);
1239
1240         codepages = (((unsigned long) _etext) - ((unsigned long) _start));
1241         codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT;
1242         datapages = (((unsigned long) _edata) - ((unsigned long) _etext));
1243         datapages = PAGE_ALIGN(datapages) >> PAGE_SHIFT;
1244         initpages = (((unsigned long) __init_end) - ((unsigned long) __init_begin));
1245         initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT;
1246
1247         printk("Memory: %uk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n",
1248                nr_free_pages() << (PAGE_SHIFT-10),
1249                codepages << (PAGE_SHIFT-10),
1250                datapages << (PAGE_SHIFT-10), 
1251                initpages << (PAGE_SHIFT-10), 
1252                PAGE_OFFSET, (last_valid_pfn << PAGE_SHIFT));
1253
1254         if (tlb_type == cheetah || tlb_type == cheetah_plus)
1255                 cheetah_ecache_flush_init();
1256 }
1257
1258 void free_initmem(void)
1259 {
1260         unsigned long addr, initend;
1261
1262         /*
1263          * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
1264          */
1265         addr = PAGE_ALIGN((unsigned long)(__init_begin));
1266         initend = (unsigned long)(__init_end) & PAGE_MASK;
1267         for (; addr < initend; addr += PAGE_SIZE) {
1268                 unsigned long page;
1269                 struct page *p;
1270
1271                 page = (addr +
1272                         ((unsigned long) __va(kern_base)) -
1273                         ((unsigned long) KERNBASE));
1274                 memset((void *)addr, 0xcc, PAGE_SIZE);
1275                 p = virt_to_page(page);
1276
1277                 ClearPageReserved(p);
1278                 set_page_count(p, 1);
1279                 __free_page(p);
1280                 num_physpages++;
1281                 totalram_pages++;
1282         }
1283 }
1284
1285 #ifdef CONFIG_BLK_DEV_INITRD
1286 void free_initrd_mem(unsigned long start, unsigned long end)
1287 {
1288         if (start < end)
1289                 printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
1290         for (; start < end; start += PAGE_SIZE) {
1291                 struct page *p = virt_to_page(start);
1292
1293                 ClearPageReserved(p);
1294                 set_page_count(p, 1);
1295                 __free_page(p);
1296                 num_physpages++;
1297                 totalram_pages++;
1298         }
1299 }
1300 #endif