[SPARC64]: Add prom_{start,stop}cpu_cpuid().
[linux-2.6.git] / arch / sparc64 / kernel / smp.c
1 /* smp.c: Sparc64 SMP support.
2  *
3  * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
4  */
5
6 #include <linux/module.h>
7 #include <linux/kernel.h>
8 #include <linux/sched.h>
9 #include <linux/mm.h>
10 #include <linux/pagemap.h>
11 #include <linux/threads.h>
12 #include <linux/smp.h>
13 #include <linux/smp_lock.h>
14 #include <linux/interrupt.h>
15 #include <linux/kernel_stat.h>
16 #include <linux/delay.h>
17 #include <linux/init.h>
18 #include <linux/spinlock.h>
19 #include <linux/fs.h>
20 #include <linux/seq_file.h>
21 #include <linux/cache.h>
22 #include <linux/jiffies.h>
23 #include <linux/profile.h>
24 #include <linux/bootmem.h>
25
26 #include <asm/head.h>
27 #include <asm/ptrace.h>
28 #include <asm/atomic.h>
29 #include <asm/tlbflush.h>
30 #include <asm/mmu_context.h>
31 #include <asm/cpudata.h>
32
33 #include <asm/irq.h>
34 #include <asm/page.h>
35 #include <asm/pgtable.h>
36 #include <asm/oplib.h>
37 #include <asm/uaccess.h>
38 #include <asm/timer.h>
39 #include <asm/starfire.h>
40 #include <asm/tlb.h>
41 #include <asm/sections.h>
42
43 extern void calibrate_delay(void);
44
45 /* Please don't make this stuff initdata!!!  --DaveM */
46 static unsigned char boot_cpu_id;
47
48 cpumask_t cpu_online_map __read_mostly = CPU_MASK_NONE;
49 cpumask_t phys_cpu_present_map __read_mostly = CPU_MASK_NONE;
50 static cpumask_t smp_commenced_mask;
51 static cpumask_t cpu_callout_map;
52
53 void smp_info(struct seq_file *m)
54 {
55         int i;
56         
57         seq_printf(m, "State:\n");
58         for (i = 0; i < NR_CPUS; i++) {
59                 if (cpu_online(i))
60                         seq_printf(m,
61                                    "CPU%d:\t\tonline\n", i);
62         }
63 }
64
65 void smp_bogo(struct seq_file *m)
66 {
67         int i;
68         
69         for (i = 0; i < NR_CPUS; i++)
70                 if (cpu_online(i))
71                         seq_printf(m,
72                                    "Cpu%dBogo\t: %lu.%02lu\n"
73                                    "Cpu%dClkTck\t: %016lx\n",
74                                    i, cpu_data(i).udelay_val / (500000/HZ),
75                                    (cpu_data(i).udelay_val / (5000/HZ)) % 100,
76                                    i, cpu_data(i).clock_tick);
77 }
78
79 void __init smp_store_cpu_info(int id)
80 {
81         int cpu_node, def;
82
83         /* multiplier and counter set by
84            smp_setup_percpu_timer()  */
85         cpu_data(id).udelay_val                 = loops_per_jiffy;
86
87         cpu_find_by_mid(id, &cpu_node);
88         cpu_data(id).clock_tick = prom_getintdefault(cpu_node,
89                                                      "clock-frequency", 0);
90
91         cpu_data(id).idle_volume                = 1;
92
93         def = ((tlb_type == hypervisor) ? (8 * 1024) : (16 * 1024));
94         cpu_data(id).dcache_size = prom_getintdefault(cpu_node, "dcache-size",
95                                                       def);
96
97         def = 32;
98         cpu_data(id).dcache_line_size =
99                 prom_getintdefault(cpu_node, "dcache-line-size", def);
100
101         def = 16 * 1024;
102         cpu_data(id).icache_size = prom_getintdefault(cpu_node, "icache-size",
103                                                       def);
104
105         def = 32;
106         cpu_data(id).icache_line_size =
107                 prom_getintdefault(cpu_node, "icache-line-size", def);
108
109         def = ((tlb_type == hypervisor) ?
110                (3 * 1024 * 1024) :
111                (4 * 1024 * 1024));
112         cpu_data(id).ecache_size = prom_getintdefault(cpu_node, "ecache-size",
113                                                       def);
114
115         def = 64;
116         cpu_data(id).ecache_line_size =
117                 prom_getintdefault(cpu_node, "ecache-line-size", def);
118
119         printk("CPU[%d]: Caches "
120                "D[sz(%d):line_sz(%d)] "
121                "I[sz(%d):line_sz(%d)] "
122                "E[sz(%d):line_sz(%d)]\n",
123                id,
124                cpu_data(id).dcache_size, cpu_data(id).dcache_line_size,
125                cpu_data(id).icache_size, cpu_data(id).icache_line_size,
126                cpu_data(id).ecache_size, cpu_data(id).ecache_line_size);
127 }
128
129 static void smp_setup_percpu_timer(void);
130
131 static volatile unsigned long callin_flag = 0;
132
133 void __init smp_callin(void)
134 {
135         int cpuid = hard_smp_processor_id();
136
137         __local_per_cpu_offset = __per_cpu_offset(cpuid);
138
139         if (tlb_type == hypervisor)
140                 sun4v_ktsb_register();
141
142         __flush_tlb_all();
143
144         smp_setup_percpu_timer();
145
146         if (cheetah_pcache_forced_on)
147                 cheetah_enable_pcache();
148
149         local_irq_enable();
150
151         calibrate_delay();
152         smp_store_cpu_info(cpuid);
153         callin_flag = 1;
154         __asm__ __volatile__("membar #Sync\n\t"
155                              "flush  %%g6" : : : "memory");
156
157         /* Clear this or we will die instantly when we
158          * schedule back to this idler...
159          */
160         current_thread_info()->new_child = 0;
161
162         /* Attach to the address space of init_task. */
163         atomic_inc(&init_mm.mm_count);
164         current->active_mm = &init_mm;
165
166         while (!cpu_isset(cpuid, smp_commenced_mask))
167                 rmb();
168
169         cpu_set(cpuid, cpu_online_map);
170
171         /* idle thread is expected to have preempt disabled */
172         preempt_disable();
173 }
174
175 void cpu_panic(void)
176 {
177         printk("CPU[%d]: Returns from cpu_idle!\n", smp_processor_id());
178         panic("SMP bolixed\n");
179 }
180
181 static unsigned long current_tick_offset __read_mostly;
182
183 /* This tick register synchronization scheme is taken entirely from
184  * the ia64 port, see arch/ia64/kernel/smpboot.c for details and credit.
185  *
186  * The only change I've made is to rework it so that the master
187  * initiates the synchonization instead of the slave. -DaveM
188  */
189
190 #define MASTER  0
191 #define SLAVE   (SMP_CACHE_BYTES/sizeof(unsigned long))
192
193 #define NUM_ROUNDS      64      /* magic value */
194 #define NUM_ITERS       5       /* likewise */
195
196 static DEFINE_SPINLOCK(itc_sync_lock);
197 static unsigned long go[SLAVE + 1];
198
199 #define DEBUG_TICK_SYNC 0
200
201 static inline long get_delta (long *rt, long *master)
202 {
203         unsigned long best_t0 = 0, best_t1 = ~0UL, best_tm = 0;
204         unsigned long tcenter, t0, t1, tm;
205         unsigned long i;
206
207         for (i = 0; i < NUM_ITERS; i++) {
208                 t0 = tick_ops->get_tick();
209                 go[MASTER] = 1;
210                 membar_storeload();
211                 while (!(tm = go[SLAVE]))
212                         rmb();
213                 go[SLAVE] = 0;
214                 wmb();
215                 t1 = tick_ops->get_tick();
216
217                 if (t1 - t0 < best_t1 - best_t0)
218                         best_t0 = t0, best_t1 = t1, best_tm = tm;
219         }
220
221         *rt = best_t1 - best_t0;
222         *master = best_tm - best_t0;
223
224         /* average best_t0 and best_t1 without overflow: */
225         tcenter = (best_t0/2 + best_t1/2);
226         if (best_t0 % 2 + best_t1 % 2 == 2)
227                 tcenter++;
228         return tcenter - best_tm;
229 }
230
231 void smp_synchronize_tick_client(void)
232 {
233         long i, delta, adj, adjust_latency = 0, done = 0;
234         unsigned long flags, rt, master_time_stamp, bound;
235 #if DEBUG_TICK_SYNC
236         struct {
237                 long rt;        /* roundtrip time */
238                 long master;    /* master's timestamp */
239                 long diff;      /* difference between midpoint and master's timestamp */
240                 long lat;       /* estimate of itc adjustment latency */
241         } t[NUM_ROUNDS];
242 #endif
243
244         go[MASTER] = 1;
245
246         while (go[MASTER])
247                 rmb();
248
249         local_irq_save(flags);
250         {
251                 for (i = 0; i < NUM_ROUNDS; i++) {
252                         delta = get_delta(&rt, &master_time_stamp);
253                         if (delta == 0) {
254                                 done = 1;       /* let's lock on to this... */
255                                 bound = rt;
256                         }
257
258                         if (!done) {
259                                 if (i > 0) {
260                                         adjust_latency += -delta;
261                                         adj = -delta + adjust_latency/4;
262                                 } else
263                                         adj = -delta;
264
265                                 tick_ops->add_tick(adj, current_tick_offset);
266                         }
267 #if DEBUG_TICK_SYNC
268                         t[i].rt = rt;
269                         t[i].master = master_time_stamp;
270                         t[i].diff = delta;
271                         t[i].lat = adjust_latency/4;
272 #endif
273                 }
274         }
275         local_irq_restore(flags);
276
277 #if DEBUG_TICK_SYNC
278         for (i = 0; i < NUM_ROUNDS; i++)
279                 printk("rt=%5ld master=%5ld diff=%5ld adjlat=%5ld\n",
280                        t[i].rt, t[i].master, t[i].diff, t[i].lat);
281 #endif
282
283         printk(KERN_INFO "CPU %d: synchronized TICK with master CPU (last diff %ld cycles,"
284                "maxerr %lu cycles)\n", smp_processor_id(), delta, rt);
285 }
286
287 static void smp_start_sync_tick_client(int cpu);
288
289 static void smp_synchronize_one_tick(int cpu)
290 {
291         unsigned long flags, i;
292
293         go[MASTER] = 0;
294
295         smp_start_sync_tick_client(cpu);
296
297         /* wait for client to be ready */
298         while (!go[MASTER])
299                 rmb();
300
301         /* now let the client proceed into his loop */
302         go[MASTER] = 0;
303         membar_storeload();
304
305         spin_lock_irqsave(&itc_sync_lock, flags);
306         {
307                 for (i = 0; i < NUM_ROUNDS*NUM_ITERS; i++) {
308                         while (!go[MASTER])
309                                 rmb();
310                         go[MASTER] = 0;
311                         wmb();
312                         go[SLAVE] = tick_ops->get_tick();
313                         membar_storeload();
314                 }
315         }
316         spin_unlock_irqrestore(&itc_sync_lock, flags);
317 }
318
319 extern unsigned long sparc64_cpu_startup;
320
321 /* The OBP cpu startup callback truncates the 3rd arg cookie to
322  * 32-bits (I think) so to be safe we have it read the pointer
323  * contained here so we work on >4GB machines. -DaveM
324  */
325 static struct thread_info *cpu_new_thread = NULL;
326
327 static int __devinit smp_boot_one_cpu(unsigned int cpu)
328 {
329         unsigned long entry =
330                 (unsigned long)(&sparc64_cpu_startup);
331         unsigned long cookie =
332                 (unsigned long)(&cpu_new_thread);
333         struct task_struct *p;
334         int timeout, ret;
335
336         p = fork_idle(cpu);
337         callin_flag = 0;
338         cpu_new_thread = task_thread_info(p);
339         cpu_set(cpu, cpu_callout_map);
340
341         if (tlb_type == hypervisor) {
342                 prom_startcpu_cpuid(cpu, entry, cookie);
343         } else {
344                 int cpu_node;
345
346                 cpu_find_by_mid(cpu, &cpu_node);
347                 prom_startcpu(cpu_node, entry, cookie);
348         }
349
350         for (timeout = 0; timeout < 5000000; timeout++) {
351                 if (callin_flag)
352                         break;
353                 udelay(100);
354         }
355         if (callin_flag) {
356                 ret = 0;
357         } else {
358                 printk("Processor %d is stuck.\n", cpu);
359                 cpu_clear(cpu, cpu_callout_map);
360                 ret = -ENODEV;
361         }
362         cpu_new_thread = NULL;
363
364         return ret;
365 }
366
367 static void spitfire_xcall_helper(u64 data0, u64 data1, u64 data2, u64 pstate, unsigned long cpu)
368 {
369         u64 result, target;
370         int stuck, tmp;
371
372         if (this_is_starfire) {
373                 /* map to real upaid */
374                 cpu = (((cpu & 0x3c) << 1) |
375                         ((cpu & 0x40) >> 4) |
376                         (cpu & 0x3));
377         }
378
379         target = (cpu << 14) | 0x70;
380 again:
381         /* Ok, this is the real Spitfire Errata #54.
382          * One must read back from a UDB internal register
383          * after writes to the UDB interrupt dispatch, but
384          * before the membar Sync for that write.
385          * So we use the high UDB control register (ASI 0x7f,
386          * ADDR 0x20) for the dummy read. -DaveM
387          */
388         tmp = 0x40;
389         __asm__ __volatile__(
390         "wrpr   %1, %2, %%pstate\n\t"
391         "stxa   %4, [%0] %3\n\t"
392         "stxa   %5, [%0+%8] %3\n\t"
393         "add    %0, %8, %0\n\t"
394         "stxa   %6, [%0+%8] %3\n\t"
395         "membar #Sync\n\t"
396         "stxa   %%g0, [%7] %3\n\t"
397         "membar #Sync\n\t"
398         "mov    0x20, %%g1\n\t"
399         "ldxa   [%%g1] 0x7f, %%g0\n\t"
400         "membar #Sync"
401         : "=r" (tmp)
402         : "r" (pstate), "i" (PSTATE_IE), "i" (ASI_INTR_W),
403           "r" (data0), "r" (data1), "r" (data2), "r" (target),
404           "r" (0x10), "0" (tmp)
405         : "g1");
406
407         /* NOTE: PSTATE_IE is still clear. */
408         stuck = 100000;
409         do {
410                 __asm__ __volatile__("ldxa [%%g0] %1, %0"
411                         : "=r" (result)
412                         : "i" (ASI_INTR_DISPATCH_STAT));
413                 if (result == 0) {
414                         __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
415                                              : : "r" (pstate));
416                         return;
417                 }
418                 stuck -= 1;
419                 if (stuck == 0)
420                         break;
421         } while (result & 0x1);
422         __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
423                              : : "r" (pstate));
424         if (stuck == 0) {
425                 printk("CPU[%d]: mondo stuckage result[%016lx]\n",
426                        smp_processor_id(), result);
427         } else {
428                 udelay(2);
429                 goto again;
430         }
431 }
432
433 static __inline__ void spitfire_xcall_deliver(u64 data0, u64 data1, u64 data2, cpumask_t mask)
434 {
435         u64 pstate;
436         int i;
437
438         __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
439         for_each_cpu_mask(i, mask)
440                 spitfire_xcall_helper(data0, data1, data2, pstate, i);
441 }
442
443 /* Cheetah now allows to send the whole 64-bytes of data in the interrupt
444  * packet, but we have no use for that.  However we do take advantage of
445  * the new pipelining feature (ie. dispatch to multiple cpus simultaneously).
446  */
447 static void cheetah_xcall_deliver(u64 data0, u64 data1, u64 data2, cpumask_t mask)
448 {
449         u64 pstate, ver;
450         int nack_busy_id, is_jbus;
451
452         if (cpus_empty(mask))
453                 return;
454
455         /* Unfortunately, someone at Sun had the brilliant idea to make the
456          * busy/nack fields hard-coded by ITID number for this Ultra-III
457          * derivative processor.
458          */
459         __asm__ ("rdpr %%ver, %0" : "=r" (ver));
460         is_jbus = ((ver >> 32) == __JALAPENO_ID ||
461                    (ver >> 32) == __SERRANO_ID);
462
463         __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
464
465 retry:
466         __asm__ __volatile__("wrpr %0, %1, %%pstate\n\t"
467                              : : "r" (pstate), "i" (PSTATE_IE));
468
469         /* Setup the dispatch data registers. */
470         __asm__ __volatile__("stxa      %0, [%3] %6\n\t"
471                              "stxa      %1, [%4] %6\n\t"
472                              "stxa      %2, [%5] %6\n\t"
473                              "membar    #Sync\n\t"
474                              : /* no outputs */
475                              : "r" (data0), "r" (data1), "r" (data2),
476                                "r" (0x40), "r" (0x50), "r" (0x60),
477                                "i" (ASI_INTR_W));
478
479         nack_busy_id = 0;
480         {
481                 int i;
482
483                 for_each_cpu_mask(i, mask) {
484                         u64 target = (i << 14) | 0x70;
485
486                         if (!is_jbus)
487                                 target |= (nack_busy_id << 24);
488                         __asm__ __volatile__(
489                                 "stxa   %%g0, [%0] %1\n\t"
490                                 "membar #Sync\n\t"
491                                 : /* no outputs */
492                                 : "r" (target), "i" (ASI_INTR_W));
493                         nack_busy_id++;
494                 }
495         }
496
497         /* Now, poll for completion. */
498         {
499                 u64 dispatch_stat;
500                 long stuck;
501
502                 stuck = 100000 * nack_busy_id;
503                 do {
504                         __asm__ __volatile__("ldxa      [%%g0] %1, %0"
505                                              : "=r" (dispatch_stat)
506                                              : "i" (ASI_INTR_DISPATCH_STAT));
507                         if (dispatch_stat == 0UL) {
508                                 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
509                                                      : : "r" (pstate));
510                                 return;
511                         }
512                         if (!--stuck)
513                                 break;
514                 } while (dispatch_stat & 0x5555555555555555UL);
515
516                 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
517                                      : : "r" (pstate));
518
519                 if ((dispatch_stat & ~(0x5555555555555555UL)) == 0) {
520                         /* Busy bits will not clear, continue instead
521                          * of freezing up on this cpu.
522                          */
523                         printk("CPU[%d]: mondo stuckage result[%016lx]\n",
524                                smp_processor_id(), dispatch_stat);
525                 } else {
526                         int i, this_busy_nack = 0;
527
528                         /* Delay some random time with interrupts enabled
529                          * to prevent deadlock.
530                          */
531                         udelay(2 * nack_busy_id);
532
533                         /* Clear out the mask bits for cpus which did not
534                          * NACK us.
535                          */
536                         for_each_cpu_mask(i, mask) {
537                                 u64 check_mask;
538
539                                 if (is_jbus)
540                                         check_mask = (0x2UL << (2*i));
541                                 else
542                                         check_mask = (0x2UL <<
543                                                       this_busy_nack);
544                                 if ((dispatch_stat & check_mask) == 0)
545                                         cpu_clear(i, mask);
546                                 this_busy_nack += 2;
547                         }
548
549                         goto retry;
550                 }
551         }
552 }
553
554 #if 0
555 /* Multi-cpu list version.  */
556 static int init_cpu_list(u16 *list, cpumask_t mask)
557 {
558         int i, cnt;
559
560         cnt = 0;
561         for_each_cpu_mask(i, mask)
562                 list[cnt++] = i;
563
564         return cnt;
565 }
566
567 static int update_cpu_list(u16 *list, int orig_cnt, cpumask_t mask)
568 {
569         int i;
570
571         for (i = 0; i < orig_cnt; i++) {
572                 if (list[i] == 0xffff)
573                         cpu_clear(i, mask);
574         }
575
576         return init_cpu_list(list, mask);
577 }
578
579 static void hypervisor_xcall_deliver(u64 data0, u64 data1, u64 data2, cpumask_t mask)
580 {
581         int this_cpu = get_cpu();
582         struct trap_per_cpu *tb = &trap_block[this_cpu];
583         u64 *mondo = __va(tb->cpu_mondo_block_pa);
584         u16 *cpu_list = __va(tb->cpu_list_pa);
585         int cnt, retries;
586
587         mondo[0] = data0;
588         mondo[1] = data1;
589         mondo[2] = data2;
590         wmb();
591
592         retries = 0;
593         cnt = init_cpu_list(cpu_list, mask);
594         do {
595                 register unsigned long func __asm__("%o5");
596                 register unsigned long arg0 __asm__("%o0");
597                 register unsigned long arg1 __asm__("%o1");
598                 register unsigned long arg2 __asm__("%o2");
599
600                 func = HV_FAST_CPU_MONDO_SEND;
601                 arg0 = cnt;
602                 arg1 = tb->cpu_list_pa;
603                 arg2 = tb->cpu_mondo_block_pa;
604
605                 __asm__ __volatile__("ta        %8"
606                                      : "=&r" (func), "=&r" (arg0),
607                                        "=&r" (arg1), "=&r" (arg2)
608                                      : "0" (func), "1" (arg0),
609                                        "2" (arg1), "3" (arg2),
610                                        "i" (HV_FAST_TRAP)
611                                      : "memory");
612                 if (likely(arg0 == HV_EOK))
613                         break;
614
615                 if (unlikely(++retries > 100)) {
616                         printk("CPU[%d]: sun4v mondo error %lu\n",
617                                this_cpu, func);
618                         break;
619                 }
620
621                 cnt = update_cpu_list(cpu_list, cnt, mask);
622
623                 udelay(2 * cnt);
624         } while (1);
625
626         put_cpu();
627 }
628 #else
629 /* Single-cpu list version.  */
630 static void hypervisor_xcall_deliver(u64 data0, u64 data1, u64 data2, cpumask_t mask)
631 {
632         int this_cpu = get_cpu();
633         struct trap_per_cpu *tb = &trap_block[this_cpu];
634         u64 *mondo = __va(tb->cpu_mondo_block_pa);
635         u16 *cpu_list = __va(tb->cpu_list_pa);
636         int i;
637
638         mondo[0] = data0;
639         mondo[1] = data1;
640         mondo[2] = data2;
641         wmb();
642
643         for_each_cpu_mask(i, mask) {
644                 int retries = 0;
645
646                 do {
647                         register unsigned long func __asm__("%o5");
648                         register unsigned long arg0 __asm__("%o0");
649                         register unsigned long arg1 __asm__("%o1");
650                         register unsigned long arg2 __asm__("%o2");
651
652                         cpu_list[0] = i;
653                         func = HV_FAST_CPU_MONDO_SEND;
654                         arg0 = 1;
655                         arg1 = tb->cpu_list_pa;
656                         arg2 = tb->cpu_mondo_block_pa;
657
658                         __asm__ __volatile__("ta        %8"
659                                              : "=&r" (func), "=&r" (arg0),
660                                                "=&r" (arg1), "=&r" (arg2)
661                                              : "0" (func), "1" (arg0),
662                                                "2" (arg1), "3" (arg2),
663                                                "i" (HV_FAST_TRAP)
664                                              : "memory");
665                         if (likely(arg0 == HV_EOK))
666                                 break;
667
668                         if (unlikely(++retries > 100)) {
669                                 printk("CPU[%d]: sun4v mondo error %lu\n",
670                                        this_cpu, func);
671                                 break;
672                         }
673
674                         udelay(2 * i);
675                 } while (1);
676         }
677
678         put_cpu();
679 }
680 #endif
681
682 /* Send cross call to all processors mentioned in MASK
683  * except self.
684  */
685 static void smp_cross_call_masked(unsigned long *func, u32 ctx, u64 data1, u64 data2, cpumask_t mask)
686 {
687         u64 data0 = (((u64)ctx)<<32 | (((u64)func) & 0xffffffff));
688         int this_cpu = get_cpu();
689
690         cpus_and(mask, mask, cpu_online_map);
691         cpu_clear(this_cpu, mask);
692
693         if (tlb_type == spitfire)
694                 spitfire_xcall_deliver(data0, data1, data2, mask);
695         else if (tlb_type == cheetah || tlb_type == cheetah_plus)
696                 cheetah_xcall_deliver(data0, data1, data2, mask);
697         else
698                 hypervisor_xcall_deliver(data0, data1, data2, mask);
699         /* NOTE: Caller runs local copy on master. */
700
701         put_cpu();
702 }
703
704 extern unsigned long xcall_sync_tick;
705
706 static void smp_start_sync_tick_client(int cpu)
707 {
708         cpumask_t mask = cpumask_of_cpu(cpu);
709
710         smp_cross_call_masked(&xcall_sync_tick,
711                               0, 0, 0, mask);
712 }
713
714 /* Send cross call to all processors except self. */
715 #define smp_cross_call(func, ctx, data1, data2) \
716         smp_cross_call_masked(func, ctx, data1, data2, cpu_online_map)
717
718 struct call_data_struct {
719         void (*func) (void *info);
720         void *info;
721         atomic_t finished;
722         int wait;
723 };
724
725 static DEFINE_SPINLOCK(call_lock);
726 static struct call_data_struct *call_data;
727
728 extern unsigned long xcall_call_function;
729
730 /*
731  * You must not call this function with disabled interrupts or from a
732  * hardware interrupt handler or from a bottom half handler.
733  */
734 static int smp_call_function_mask(void (*func)(void *info), void *info,
735                                   int nonatomic, int wait, cpumask_t mask)
736 {
737         struct call_data_struct data;
738         int cpus = cpus_weight(mask) - 1;
739         long timeout;
740
741         if (!cpus)
742                 return 0;
743
744         /* Can deadlock when called with interrupts disabled */
745         WARN_ON(irqs_disabled());
746
747         data.func = func;
748         data.info = info;
749         atomic_set(&data.finished, 0);
750         data.wait = wait;
751
752         spin_lock(&call_lock);
753
754         call_data = &data;
755
756         smp_cross_call_masked(&xcall_call_function, 0, 0, 0, mask);
757
758         /* 
759          * Wait for other cpus to complete function or at
760          * least snap the call data.
761          */
762         timeout = 1000000;
763         while (atomic_read(&data.finished) != cpus) {
764                 if (--timeout <= 0)
765                         goto out_timeout;
766                 barrier();
767                 udelay(1);
768         }
769
770         spin_unlock(&call_lock);
771
772         return 0;
773
774 out_timeout:
775         spin_unlock(&call_lock);
776         printk("XCALL: Remote cpus not responding, ncpus=%ld finished=%ld\n",
777                (long) num_online_cpus() - 1L,
778                (long) atomic_read(&data.finished));
779         return 0;
780 }
781
782 int smp_call_function(void (*func)(void *info), void *info,
783                       int nonatomic, int wait)
784 {
785         return smp_call_function_mask(func, info, nonatomic, wait,
786                                       cpu_online_map);
787 }
788
789 void smp_call_function_client(int irq, struct pt_regs *regs)
790 {
791         void (*func) (void *info) = call_data->func;
792         void *info = call_data->info;
793
794         clear_softint(1 << irq);
795         if (call_data->wait) {
796                 /* let initiator proceed only after completion */
797                 func(info);
798                 atomic_inc(&call_data->finished);
799         } else {
800                 /* let initiator proceed after getting data */
801                 atomic_inc(&call_data->finished);
802                 func(info);
803         }
804 }
805
806 static void tsb_sync(void *info)
807 {
808         struct mm_struct *mm = info;
809
810         if (current->active_mm == mm)
811                 tsb_context_switch(mm);
812 }
813
814 void smp_tsb_sync(struct mm_struct *mm)
815 {
816         smp_call_function_mask(tsb_sync, mm, 0, 1, mm->cpu_vm_mask);
817 }
818
819 extern unsigned long xcall_flush_tlb_mm;
820 extern unsigned long xcall_flush_tlb_pending;
821 extern unsigned long xcall_flush_tlb_kernel_range;
822 extern unsigned long xcall_report_regs;
823 extern unsigned long xcall_receive_signal;
824
825 #ifdef DCACHE_ALIASING_POSSIBLE
826 extern unsigned long xcall_flush_dcache_page_cheetah;
827 #endif
828 extern unsigned long xcall_flush_dcache_page_spitfire;
829
830 #ifdef CONFIG_DEBUG_DCFLUSH
831 extern atomic_t dcpage_flushes;
832 extern atomic_t dcpage_flushes_xcall;
833 #endif
834
835 static __inline__ void __local_flush_dcache_page(struct page *page)
836 {
837 #ifdef DCACHE_ALIASING_POSSIBLE
838         __flush_dcache_page(page_address(page),
839                             ((tlb_type == spitfire) &&
840                              page_mapping(page) != NULL));
841 #else
842         if (page_mapping(page) != NULL &&
843             tlb_type == spitfire)
844                 __flush_icache_page(__pa(page_address(page)));
845 #endif
846 }
847
848 void smp_flush_dcache_page_impl(struct page *page, int cpu)
849 {
850         cpumask_t mask = cpumask_of_cpu(cpu);
851         int this_cpu;
852
853         if (tlb_type == hypervisor)
854                 return;
855
856 #ifdef CONFIG_DEBUG_DCFLUSH
857         atomic_inc(&dcpage_flushes);
858 #endif
859
860         this_cpu = get_cpu();
861
862         if (cpu == this_cpu) {
863                 __local_flush_dcache_page(page);
864         } else if (cpu_online(cpu)) {
865                 void *pg_addr = page_address(page);
866                 u64 data0;
867
868                 if (tlb_type == spitfire) {
869                         data0 =
870                                 ((u64)&xcall_flush_dcache_page_spitfire);
871                         if (page_mapping(page) != NULL)
872                                 data0 |= ((u64)1 << 32);
873                         spitfire_xcall_deliver(data0,
874                                                __pa(pg_addr),
875                                                (u64) pg_addr,
876                                                mask);
877                 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
878 #ifdef DCACHE_ALIASING_POSSIBLE
879                         data0 =
880                                 ((u64)&xcall_flush_dcache_page_cheetah);
881                         cheetah_xcall_deliver(data0,
882                                               __pa(pg_addr),
883                                               0, mask);
884 #endif
885                 }
886 #ifdef CONFIG_DEBUG_DCFLUSH
887                 atomic_inc(&dcpage_flushes_xcall);
888 #endif
889         }
890
891         put_cpu();
892 }
893
894 void flush_dcache_page_all(struct mm_struct *mm, struct page *page)
895 {
896         void *pg_addr = page_address(page);
897         cpumask_t mask = cpu_online_map;
898         u64 data0;
899         int this_cpu;
900
901         if (tlb_type == hypervisor)
902                 return;
903
904         this_cpu = get_cpu();
905
906         cpu_clear(this_cpu, mask);
907
908 #ifdef CONFIG_DEBUG_DCFLUSH
909         atomic_inc(&dcpage_flushes);
910 #endif
911         if (cpus_empty(mask))
912                 goto flush_self;
913         if (tlb_type == spitfire) {
914                 data0 = ((u64)&xcall_flush_dcache_page_spitfire);
915                 if (page_mapping(page) != NULL)
916                         data0 |= ((u64)1 << 32);
917                 spitfire_xcall_deliver(data0,
918                                        __pa(pg_addr),
919                                        (u64) pg_addr,
920                                        mask);
921         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
922 #ifdef DCACHE_ALIASING_POSSIBLE
923                 data0 = ((u64)&xcall_flush_dcache_page_cheetah);
924                 cheetah_xcall_deliver(data0,
925                                       __pa(pg_addr),
926                                       0, mask);
927 #endif
928         }
929 #ifdef CONFIG_DEBUG_DCFLUSH
930         atomic_inc(&dcpage_flushes_xcall);
931 #endif
932  flush_self:
933         __local_flush_dcache_page(page);
934
935         put_cpu();
936 }
937
938 void smp_receive_signal(int cpu)
939 {
940         cpumask_t mask = cpumask_of_cpu(cpu);
941
942         if (cpu_online(cpu)) {
943                 u64 data0 = (((u64)&xcall_receive_signal) & 0xffffffff);
944
945                 if (tlb_type == spitfire)
946                         spitfire_xcall_deliver(data0, 0, 0, mask);
947                 else if (tlb_type == cheetah || tlb_type == cheetah_plus)
948                         cheetah_xcall_deliver(data0, 0, 0, mask);
949                 else if (tlb_type == hypervisor)
950                         hypervisor_xcall_deliver(data0, 0, 0, mask);
951         }
952 }
953
954 void smp_receive_signal_client(int irq, struct pt_regs *regs)
955 {
956         /* Just return, rtrap takes care of the rest. */
957         clear_softint(1 << irq);
958 }
959
960 void smp_report_regs(void)
961 {
962         smp_cross_call(&xcall_report_regs, 0, 0, 0);
963 }
964
965 /* We know that the window frames of the user have been flushed
966  * to the stack before we get here because all callers of us
967  * are flush_tlb_*() routines, and these run after flush_cache_*()
968  * which performs the flushw.
969  *
970  * The SMP TLB coherency scheme we use works as follows:
971  *
972  * 1) mm->cpu_vm_mask is a bit mask of which cpus an address
973  *    space has (potentially) executed on, this is the heuristic
974  *    we use to avoid doing cross calls.
975  *
976  *    Also, for flushing from kswapd and also for clones, we
977  *    use cpu_vm_mask as the list of cpus to make run the TLB.
978  *
979  * 2) TLB context numbers are shared globally across all processors
980  *    in the system, this allows us to play several games to avoid
981  *    cross calls.
982  *
983  *    One invariant is that when a cpu switches to a process, and
984  *    that processes tsk->active_mm->cpu_vm_mask does not have the
985  *    current cpu's bit set, that tlb context is flushed locally.
986  *
987  *    If the address space is non-shared (ie. mm->count == 1) we avoid
988  *    cross calls when we want to flush the currently running process's
989  *    tlb state.  This is done by clearing all cpu bits except the current
990  *    processor's in current->active_mm->cpu_vm_mask and performing the
991  *    flush locally only.  This will force any subsequent cpus which run
992  *    this task to flush the context from the local tlb if the process
993  *    migrates to another cpu (again).
994  *
995  * 3) For shared address spaces (threads) and swapping we bite the
996  *    bullet for most cases and perform the cross call (but only to
997  *    the cpus listed in cpu_vm_mask).
998  *
999  *    The performance gain from "optimizing" away the cross call for threads is
1000  *    questionable (in theory the big win for threads is the massive sharing of
1001  *    address space state across processors).
1002  */
1003
1004 /* This currently is only used by the hugetlb arch pre-fault
1005  * hook on UltraSPARC-III+ and later when changing the pagesize
1006  * bits of the context register for an address space.
1007  */
1008 void smp_flush_tlb_mm(struct mm_struct *mm)
1009 {
1010         u32 ctx = CTX_HWBITS(mm->context);
1011         int cpu = get_cpu();
1012
1013         if (atomic_read(&mm->mm_users) == 1) {
1014                 mm->cpu_vm_mask = cpumask_of_cpu(cpu);
1015                 goto local_flush_and_out;
1016         }
1017
1018         smp_cross_call_masked(&xcall_flush_tlb_mm,
1019                               ctx, 0, 0,
1020                               mm->cpu_vm_mask);
1021
1022 local_flush_and_out:
1023         __flush_tlb_mm(ctx, SECONDARY_CONTEXT);
1024
1025         put_cpu();
1026 }
1027
1028 void smp_flush_tlb_pending(struct mm_struct *mm, unsigned long nr, unsigned long *vaddrs)
1029 {
1030         u32 ctx = CTX_HWBITS(mm->context);
1031         int cpu = get_cpu();
1032
1033         if (mm == current->active_mm && atomic_read(&mm->mm_users) == 1)
1034                 mm->cpu_vm_mask = cpumask_of_cpu(cpu);
1035         else
1036                 smp_cross_call_masked(&xcall_flush_tlb_pending,
1037                                       ctx, nr, (unsigned long) vaddrs,
1038                                       mm->cpu_vm_mask);
1039
1040         __flush_tlb_pending(ctx, nr, vaddrs);
1041
1042         put_cpu();
1043 }
1044
1045 void smp_flush_tlb_kernel_range(unsigned long start, unsigned long end)
1046 {
1047         start &= PAGE_MASK;
1048         end    = PAGE_ALIGN(end);
1049         if (start != end) {
1050                 smp_cross_call(&xcall_flush_tlb_kernel_range,
1051                                0, start, end);
1052
1053                 __flush_tlb_kernel_range(start, end);
1054         }
1055 }
1056
1057 /* CPU capture. */
1058 /* #define CAPTURE_DEBUG */
1059 extern unsigned long xcall_capture;
1060
1061 static atomic_t smp_capture_depth = ATOMIC_INIT(0);
1062 static atomic_t smp_capture_registry = ATOMIC_INIT(0);
1063 static unsigned long penguins_are_doing_time;
1064
1065 void smp_capture(void)
1066 {
1067         int result = atomic_add_ret(1, &smp_capture_depth);
1068
1069         if (result == 1) {
1070                 int ncpus = num_online_cpus();
1071
1072 #ifdef CAPTURE_DEBUG
1073                 printk("CPU[%d]: Sending penguins to jail...",
1074                        smp_processor_id());
1075 #endif
1076                 penguins_are_doing_time = 1;
1077                 membar_storestore_loadstore();
1078                 atomic_inc(&smp_capture_registry);
1079                 smp_cross_call(&xcall_capture, 0, 0, 0);
1080                 while (atomic_read(&smp_capture_registry) != ncpus)
1081                         rmb();
1082 #ifdef CAPTURE_DEBUG
1083                 printk("done\n");
1084 #endif
1085         }
1086 }
1087
1088 void smp_release(void)
1089 {
1090         if (atomic_dec_and_test(&smp_capture_depth)) {
1091 #ifdef CAPTURE_DEBUG
1092                 printk("CPU[%d]: Giving pardon to "
1093                        "imprisoned penguins\n",
1094                        smp_processor_id());
1095 #endif
1096                 penguins_are_doing_time = 0;
1097                 membar_storeload_storestore();
1098                 atomic_dec(&smp_capture_registry);
1099         }
1100 }
1101
1102 /* Imprisoned penguins run with %pil == 15, but PSTATE_IE set, so they
1103  * can service tlb flush xcalls...
1104  */
1105 extern void prom_world(int);
1106
1107 void smp_penguin_jailcell(int irq, struct pt_regs *regs)
1108 {
1109         clear_softint(1 << irq);
1110
1111         preempt_disable();
1112
1113         __asm__ __volatile__("flushw");
1114         prom_world(1);
1115         atomic_inc(&smp_capture_registry);
1116         membar_storeload_storestore();
1117         while (penguins_are_doing_time)
1118                 rmb();
1119         atomic_dec(&smp_capture_registry);
1120         prom_world(0);
1121
1122         preempt_enable();
1123 }
1124
1125 #define prof_multiplier(__cpu)          cpu_data(__cpu).multiplier
1126 #define prof_counter(__cpu)             cpu_data(__cpu).counter
1127
1128 void smp_percpu_timer_interrupt(struct pt_regs *regs)
1129 {
1130         unsigned long compare, tick, pstate;
1131         int cpu = smp_processor_id();
1132         int user = user_mode(regs);
1133
1134         /*
1135          * Check for level 14 softint.
1136          */
1137         {
1138                 unsigned long tick_mask = tick_ops->softint_mask;
1139
1140                 if (!(get_softint() & tick_mask)) {
1141                         extern void handler_irq(int, struct pt_regs *);
1142
1143                         handler_irq(14, regs);
1144                         return;
1145                 }
1146                 clear_softint(tick_mask);
1147         }
1148
1149         do {
1150                 profile_tick(CPU_PROFILING, regs);
1151                 if (!--prof_counter(cpu)) {
1152                         irq_enter();
1153
1154                         if (cpu == boot_cpu_id) {
1155                                 kstat_this_cpu.irqs[0]++;
1156                                 timer_tick_interrupt(regs);
1157                         }
1158
1159                         update_process_times(user);
1160
1161                         irq_exit();
1162
1163                         prof_counter(cpu) = prof_multiplier(cpu);
1164                 }
1165
1166                 /* Guarantee that the following sequences execute
1167                  * uninterrupted.
1168                  */
1169                 __asm__ __volatile__("rdpr      %%pstate, %0\n\t"
1170                                      "wrpr      %0, %1, %%pstate"
1171                                      : "=r" (pstate)
1172                                      : "i" (PSTATE_IE));
1173
1174                 compare = tick_ops->add_compare(current_tick_offset);
1175                 tick = tick_ops->get_tick();
1176
1177                 /* Restore PSTATE_IE. */
1178                 __asm__ __volatile__("wrpr      %0, 0x0, %%pstate"
1179                                      : /* no outputs */
1180                                      : "r" (pstate));
1181         } while (time_after_eq(tick, compare));
1182 }
1183
1184 static void __init smp_setup_percpu_timer(void)
1185 {
1186         int cpu = smp_processor_id();
1187         unsigned long pstate;
1188
1189         prof_counter(cpu) = prof_multiplier(cpu) = 1;
1190
1191         /* Guarantee that the following sequences execute
1192          * uninterrupted.
1193          */
1194         __asm__ __volatile__("rdpr      %%pstate, %0\n\t"
1195                              "wrpr      %0, %1, %%pstate"
1196                              : "=r" (pstate)
1197                              : "i" (PSTATE_IE));
1198
1199         tick_ops->init_tick(current_tick_offset);
1200
1201         /* Restore PSTATE_IE. */
1202         __asm__ __volatile__("wrpr      %0, 0x0, %%pstate"
1203                              : /* no outputs */
1204                              : "r" (pstate));
1205 }
1206
1207 void __init smp_tick_init(void)
1208 {
1209         boot_cpu_id = hard_smp_processor_id();
1210         current_tick_offset = timer_tick_offset;
1211
1212         cpu_set(boot_cpu_id, cpu_online_map);
1213         prof_counter(boot_cpu_id) = prof_multiplier(boot_cpu_id) = 1;
1214 }
1215
1216 /* /proc/profile writes can call this, don't __init it please. */
1217 static DEFINE_SPINLOCK(prof_setup_lock);
1218
1219 int setup_profiling_timer(unsigned int multiplier)
1220 {
1221         unsigned long flags;
1222         int i;
1223
1224         if ((!multiplier) || (timer_tick_offset / multiplier) < 1000)
1225                 return -EINVAL;
1226
1227         spin_lock_irqsave(&prof_setup_lock, flags);
1228         for (i = 0; i < NR_CPUS; i++)
1229                 prof_multiplier(i) = multiplier;
1230         current_tick_offset = (timer_tick_offset / multiplier);
1231         spin_unlock_irqrestore(&prof_setup_lock, flags);
1232
1233         return 0;
1234 }
1235
1236 /* Constrain the number of cpus to max_cpus.  */
1237 void __init smp_prepare_cpus(unsigned int max_cpus)
1238 {
1239         if (num_possible_cpus() > max_cpus) {
1240                 int instance, mid;
1241
1242                 instance = 0;
1243                 while (!cpu_find_by_instance(instance, NULL, &mid)) {
1244                         if (mid != boot_cpu_id) {
1245                                 cpu_clear(mid, phys_cpu_present_map);
1246                                 if (num_possible_cpus() <= max_cpus)
1247                                         break;
1248                         }
1249                         instance++;
1250                 }
1251         }
1252
1253         smp_store_cpu_info(boot_cpu_id);
1254 }
1255
1256 /* Set this up early so that things like the scheduler can init
1257  * properly.  We use the same cpu mask for both the present and
1258  * possible cpu map.
1259  */
1260 void __init smp_setup_cpu_possible_map(void)
1261 {
1262         int instance, mid;
1263
1264         instance = 0;
1265         while (!cpu_find_by_instance(instance, NULL, &mid)) {
1266                 if (mid < NR_CPUS)
1267                         cpu_set(mid, phys_cpu_present_map);
1268                 instance++;
1269         }
1270 }
1271
1272 void __devinit smp_prepare_boot_cpu(void)
1273 {
1274         int cpu = hard_smp_processor_id();
1275
1276         if (cpu >= NR_CPUS) {
1277                 prom_printf("Serious problem, boot cpu id >= NR_CPUS\n");
1278                 prom_halt();
1279         }
1280
1281         current_thread_info()->cpu = cpu;
1282         __local_per_cpu_offset = __per_cpu_offset(cpu);
1283
1284         cpu_set(smp_processor_id(), cpu_online_map);
1285         cpu_set(smp_processor_id(), phys_cpu_present_map);
1286 }
1287
1288 int __devinit __cpu_up(unsigned int cpu)
1289 {
1290         int ret = smp_boot_one_cpu(cpu);
1291
1292         if (!ret) {
1293                 cpu_set(cpu, smp_commenced_mask);
1294                 while (!cpu_isset(cpu, cpu_online_map))
1295                         mb();
1296                 if (!cpu_isset(cpu, cpu_online_map)) {
1297                         ret = -ENODEV;
1298                 } else {
1299                         /* On SUN4V, writes to %tick and %stick are
1300                          * not allowed.
1301                          */
1302                         if (tlb_type != hypervisor)
1303                                 smp_synchronize_one_tick(cpu);
1304                 }
1305         }
1306         return ret;
1307 }
1308
1309 void __init smp_cpus_done(unsigned int max_cpus)
1310 {
1311         unsigned long bogosum = 0;
1312         int i;
1313
1314         for (i = 0; i < NR_CPUS; i++) {
1315                 if (cpu_online(i))
1316                         bogosum += cpu_data(i).udelay_val;
1317         }
1318         printk("Total of %ld processors activated "
1319                "(%lu.%02lu BogoMIPS).\n",
1320                (long) num_online_cpus(),
1321                bogosum/(500000/HZ),
1322                (bogosum/(5000/HZ))%100);
1323 }
1324
1325 void smp_send_reschedule(int cpu)
1326 {
1327         smp_receive_signal(cpu);
1328 }
1329
1330 /* This is a nop because we capture all other cpus
1331  * anyways when making the PROM active.
1332  */
1333 void smp_send_stop(void)
1334 {
1335 }
1336
1337 unsigned long __per_cpu_base __read_mostly;
1338 unsigned long __per_cpu_shift __read_mostly;
1339
1340 EXPORT_SYMBOL(__per_cpu_base);
1341 EXPORT_SYMBOL(__per_cpu_shift);
1342
1343 void __init setup_per_cpu_areas(void)
1344 {
1345         unsigned long goal, size, i;
1346         char *ptr;
1347
1348         /* Copy section for each CPU (we discard the original) */
1349         goal = ALIGN(__per_cpu_end - __per_cpu_start, SMP_CACHE_BYTES);
1350 #ifdef CONFIG_MODULES
1351         if (goal < PERCPU_ENOUGH_ROOM)
1352                 goal = PERCPU_ENOUGH_ROOM;
1353 #endif
1354         __per_cpu_shift = 0;
1355         for (size = 1UL; size < goal; size <<= 1UL)
1356                 __per_cpu_shift++;
1357
1358         ptr = alloc_bootmem(size * NR_CPUS);
1359
1360         __per_cpu_base = ptr - __per_cpu_start;
1361
1362         for (i = 0; i < NR_CPUS; i++, ptr += size)
1363                 memcpy(ptr, __per_cpu_start, __per_cpu_end - __per_cpu_start);
1364 }