779cf62d3ce9ea54e0cf61176eee8464d4c829ff
[linux-2.6.git] / arch / sparc / include / asm / system_64.h
1 #ifndef __SPARC64_SYSTEM_H
2 #define __SPARC64_SYSTEM_H
3
4 #include <asm/ptrace.h>
5 #include <asm/processor.h>
6 #include <asm/visasm.h>
7
8 #ifndef __ASSEMBLY__
9
10 #include <linux/irqflags.h>
11 #include <asm-generic/cmpxchg-local.h>
12
13 /*
14  * Sparc (general) CPU types
15  */
16 enum sparc_cpu {
17   sun4        = 0x00,
18   sun4c       = 0x01,
19   sun4m       = 0x02,
20   sun4d       = 0x03,
21   sun4e       = 0x04,
22   sun4u       = 0x05, /* V8 ploos ploos */
23   sun_unknown = 0x06,
24   ap1000      = 0x07, /* almost a sun4m */
25 };
26
27 #define sparc_cpu_model sun4u
28
29 /* This cannot ever be a sun4c :) That's just history. */
30 #define ARCH_SUN4C 0
31
32 extern char reboot_command[];
33
34 /* These are here in an effort to more fully work around Spitfire Errata
35  * #51.  Essentially, if a memory barrier occurs soon after a mispredicted
36  * branch, the chip can stop executing instructions until a trap occurs.
37  * Therefore, if interrupts are disabled, the chip can hang forever.
38  *
39  * It used to be believed that the memory barrier had to be right in the
40  * delay slot, but a case has been traced recently wherein the memory barrier
41  * was one instruction after the branch delay slot and the chip still hung.
42  * The offending sequence was the following in sym_wakeup_done() of the
43  * sym53c8xx_2 driver:
44  *
45  *      call    sym_ccb_from_dsa, 0
46  *       movge  %icc, 0, %l0
47  *      brz,pn  %o0, .LL1303
48  *       mov    %o0, %l2
49  *      membar  #LoadLoad
50  *
51  * The branch has to be mispredicted for the bug to occur.  Therefore, we put
52  * the memory barrier explicitly into a "branch always, predicted taken"
53  * delay slot to avoid the problem case.
54  */
55 #define membar_safe(type) \
56 do {    __asm__ __volatile__("ba,pt     %%xcc, 1f\n\t" \
57                              " membar   " type "\n" \
58                              "1:\n" \
59                              : : : "memory"); \
60 } while (0)
61
62 #define mb()    membar_safe("#StoreLoad")
63 #define rmb()   __asm__ __volatile__("":::"memory")
64 #define wmb()   __asm__ __volatile__("":::"memory")
65
66 #endif
67
68 #define nop()           __asm__ __volatile__ ("nop")
69
70 #define read_barrier_depends()          do { } while(0)
71 #define set_mb(__var, __value) \
72         do { __var = __value; membar_safe("#StoreLoad"); } while(0)
73
74 #ifdef CONFIG_SMP
75 #define smp_mb()        mb()
76 #define smp_rmb()       rmb()
77 #define smp_wmb()       wmb()
78 #else
79 #define smp_mb()        __asm__ __volatile__("":::"memory")
80 #define smp_rmb()       __asm__ __volatile__("":::"memory")
81 #define smp_wmb()       __asm__ __volatile__("":::"memory")
82 #endif
83
84 #define smp_read_barrier_depends()      do { } while(0)
85
86 #define flushi(addr)    __asm__ __volatile__ ("flush %0" : : "r" (addr) : "memory")
87
88 #define flushw_all()    __asm__ __volatile__("flushw")
89
90 /* Performance counter register access. */
91 #define read_pcr(__p)  __asm__ __volatile__("rd %%pcr, %0" : "=r" (__p))
92 #define write_pcr(__p) __asm__ __volatile__("wr %0, 0x0, %%pcr" : : "r" (__p))
93 #define read_pic(__p)  __asm__ __volatile__("rd %%pic, %0" : "=r" (__p))
94
95 /* Blackbird errata workaround.  See commentary in
96  * arch/sparc64/kernel/smp.c:smp_percpu_timer_interrupt()
97  * for more information.
98  */
99 #define reset_pic()                                             \
100         __asm__ __volatile__("ba,pt     %xcc, 99f\n\t"          \
101                              ".align    64\n"                   \
102                           "99:wr        %g0, 0x0, %pic\n\t"     \
103                              "rd        %pic, %g0")
104
105 #ifndef __ASSEMBLY__
106
107 extern void sun_do_break(void);
108 extern int stop_a_enabled;
109 extern int scons_pwroff;
110
111 extern void fault_in_user_windows(void);
112 extern void synchronize_user_stack(void);
113
114 extern void __flushw_user(void);
115 #define flushw_user() __flushw_user()
116
117 #define flush_user_windows flushw_user
118 #define flush_register_windows flushw_all
119
120 /* Don't hold the runqueue lock over context switch */
121 #define __ARCH_WANT_UNLOCKED_CTXSW
122 #define prepare_arch_switch(next)               \
123 do {                                            \
124         flushw_all();                           \
125 } while (0)
126
127         /* See what happens when you design the chip correctly?
128          *
129          * We tell gcc we clobber all non-fixed-usage registers except
130          * for l0/l1.  It will use one for 'next' and the other to hold
131          * the output value of 'last'.  'next' is not referenced again
132          * past the invocation of switch_to in the scheduler, so we need
133          * not preserve it's value.  Hairy, but it lets us remove 2 loads
134          * and 2 stores in this critical code path.  -DaveM
135          */
136 #define switch_to(prev, next, last)                                     \
137 do {    if (test_thread_flag(TIF_PERFCTR)) {                            \
138                 unsigned long __tmp;                                    \
139                 read_pcr(__tmp);                                        \
140                 current_thread_info()->pcr_reg = __tmp;                 \
141                 read_pic(__tmp);                                        \
142                 current_thread_info()->kernel_cntd0 += (unsigned int)(__tmp);\
143                 current_thread_info()->kernel_cntd1 += ((__tmp) >> 32); \
144         }                                                               \
145         flush_tlb_pending();                                            \
146         save_and_clear_fpu();                                           \
147         /* If you are tempted to conditionalize the following */        \
148         /* so that ASI is only written if it changes, think again. */   \
149         __asm__ __volatile__("wr %%g0, %0, %%asi"                       \
150         : : "r" (__thread_flag_byte_ptr(task_thread_info(next))[TI_FLAG_BYTE_CURRENT_DS]));\
151         trap_block[current_thread_info()->cpu].thread =                 \
152                 task_thread_info(next);                                 \
153         __asm__ __volatile__(                                           \
154         "mov    %%g4, %%g7\n\t"                                         \
155         "stx    %%i6, [%%sp + 2047 + 0x70]\n\t"                         \
156         "stx    %%i7, [%%sp + 2047 + 0x78]\n\t"                         \
157         "rdpr   %%wstate, %%o5\n\t"                                     \
158         "stx    %%o6, [%%g6 + %6]\n\t"                                  \
159         "stb    %%o5, [%%g6 + %5]\n\t"                                  \
160         "rdpr   %%cwp, %%o5\n\t"                                        \
161         "stb    %%o5, [%%g6 + %8]\n\t"                                  \
162         "wrpr   %%g0, 15, %%pil\n\t"                                    \
163         "mov    %4, %%g6\n\t"                                           \
164         "ldub   [%4 + %8], %%g1\n\t"                                    \
165         "wrpr   %%g1, %%cwp\n\t"                                        \
166         "ldx    [%%g6 + %6], %%o6\n\t"                                  \
167         "ldub   [%%g6 + %5], %%o5\n\t"                                  \
168         "ldub   [%%g6 + %7], %%o7\n\t"                                  \
169         "wrpr   %%o5, 0x0, %%wstate\n\t"                                \
170         "ldx    [%%sp + 2047 + 0x70], %%i6\n\t"                         \
171         "ldx    [%%sp + 2047 + 0x78], %%i7\n\t"                         \
172         "ldx    [%%g6 + %9], %%g4\n\t"                                  \
173         "wrpr   %%g0, 14, %%pil\n\t"                                    \
174         "brz,pt %%o7, switch_to_pc\n\t"                                 \
175         " mov   %%g7, %0\n\t"                                           \
176         "sethi  %%hi(ret_from_syscall), %%g1\n\t"                       \
177         "jmpl   %%g1 + %%lo(ret_from_syscall), %%g0\n\t"                \
178         " nop\n\t"                                                      \
179         ".globl switch_to_pc\n\t"                                       \
180         "switch_to_pc:\n\t"                                             \
181         : "=&r" (last), "=r" (current), "=r" (current_thread_info_reg), \
182           "=r" (__local_per_cpu_offset)                                 \
183         : "0" (task_thread_info(next)),                                 \
184           "i" (TI_WSTATE), "i" (TI_KSP), "i" (TI_NEW_CHILD),            \
185           "i" (TI_CWP), "i" (TI_TASK)                                   \
186         : "cc",                                                         \
187                 "g1", "g2", "g3",                   "g7",               \
188                 "l1", "l2", "l3", "l4", "l5", "l6", "l7",               \
189           "i0", "i1", "i2", "i3", "i4", "i5",                           \
190           "o0", "o1", "o2", "o3", "o4", "o5",       "o7");              \
191         /* If you fuck with this, update ret_from_syscall code too. */  \
192         if (test_thread_flag(TIF_PERFCTR)) {                            \
193                 write_pcr(current_thread_info()->pcr_reg);              \
194                 reset_pic();                                            \
195         }                                                               \
196 } while(0)
197
198 static inline unsigned long xchg32(__volatile__ unsigned int *m, unsigned int val)
199 {
200         unsigned long tmp1, tmp2;
201
202         __asm__ __volatile__(
203 "       mov             %0, %1\n"
204 "1:     lduw            [%4], %2\n"
205 "       cas             [%4], %2, %0\n"
206 "       cmp             %2, %0\n"
207 "       bne,a,pn        %%icc, 1b\n"
208 "        mov            %1, %0\n"
209         : "=&r" (val), "=&r" (tmp1), "=&r" (tmp2)
210         : "0" (val), "r" (m)
211         : "cc", "memory");
212         return val;
213 }
214
215 static inline unsigned long xchg64(__volatile__ unsigned long *m, unsigned long val)
216 {
217         unsigned long tmp1, tmp2;
218
219         __asm__ __volatile__(
220 "       mov             %0, %1\n"
221 "1:     ldx             [%4], %2\n"
222 "       casx            [%4], %2, %0\n"
223 "       cmp             %2, %0\n"
224 "       bne,a,pn        %%xcc, 1b\n"
225 "        mov            %1, %0\n"
226         : "=&r" (val), "=&r" (tmp1), "=&r" (tmp2)
227         : "0" (val), "r" (m)
228         : "cc", "memory");
229         return val;
230 }
231
232 #define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
233
234 extern void __xchg_called_with_bad_pointer(void);
235
236 static inline unsigned long __xchg(unsigned long x, __volatile__ void * ptr,
237                                        int size)
238 {
239         switch (size) {
240         case 4:
241                 return xchg32(ptr, x);
242         case 8:
243                 return xchg64(ptr, x);
244         };
245         __xchg_called_with_bad_pointer();
246         return x;
247 }
248
249 extern void die_if_kernel(char *str, struct pt_regs *regs) __attribute__ ((noreturn));
250
251 /*
252  * Atomic compare and exchange.  Compare OLD with MEM, if identical,
253  * store NEW in MEM.  Return the initial value in MEM.  Success is
254  * indicated by comparing RETURN with OLD.
255  */
256
257 #define __HAVE_ARCH_CMPXCHG 1
258
259 static inline unsigned long
260 __cmpxchg_u32(volatile int *m, int old, int new)
261 {
262         __asm__ __volatile__("cas [%2], %3, %0"
263                              : "=&r" (new)
264                              : "0" (new), "r" (m), "r" (old)
265                              : "memory");
266
267         return new;
268 }
269
270 static inline unsigned long
271 __cmpxchg_u64(volatile long *m, unsigned long old, unsigned long new)
272 {
273         __asm__ __volatile__("casx [%2], %3, %0"
274                              : "=&r" (new)
275                              : "0" (new), "r" (m), "r" (old)
276                              : "memory");
277
278         return new;
279 }
280
281 /* This function doesn't exist, so you'll get a linker error
282    if something tries to do an invalid cmpxchg().  */
283 extern void __cmpxchg_called_with_bad_pointer(void);
284
285 static inline unsigned long
286 __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
287 {
288         switch (size) {
289                 case 4:
290                         return __cmpxchg_u32(ptr, old, new);
291                 case 8:
292                         return __cmpxchg_u64(ptr, old, new);
293         }
294         __cmpxchg_called_with_bad_pointer();
295         return old;
296 }
297
298 #define cmpxchg(ptr,o,n)                                                 \
299   ({                                                                     \
300      __typeof__(*(ptr)) _o_ = (o);                                       \
301      __typeof__(*(ptr)) _n_ = (n);                                       \
302      (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_,           \
303                                     (unsigned long)_n_, sizeof(*(ptr))); \
304   })
305
306 /*
307  * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
308  * them available.
309  */
310
311 static inline unsigned long __cmpxchg_local(volatile void *ptr,
312                                       unsigned long old,
313                                       unsigned long new, int size)
314 {
315         switch (size) {
316         case 4:
317         case 8: return __cmpxchg(ptr, old, new, size);
318         default:
319                 return __cmpxchg_local_generic(ptr, old, new, size);
320         }
321
322         return old;
323 }
324
325 #define cmpxchg_local(ptr, o, n)                                        \
326         ((__typeof__(*(ptr)))__cmpxchg_local((ptr), (unsigned long)(o), \
327                         (unsigned long)(n), sizeof(*(ptr))))
328 #define cmpxchg64_local(ptr, o, n)                                      \
329   ({                                                                    \
330         BUILD_BUG_ON(sizeof(*(ptr)) != 8);                              \
331         cmpxchg_local((ptr), (o), (n));                                 \
332   })
333
334 #endif /* !(__ASSEMBLY__) */
335
336 #define arch_align_stack(x) (x)
337
338 #endif /* !(__SPARC64_SYSTEM_H) */