arch/sh/kernel/cpu/sh4/setup-sh7750.c

   1 /*
   2  * SH7750/SH7751 Setup
   3  *
   4  *  Copyright (C) 2006  Paul Mundt
   5  *  Copyright (C) 2006  Jamie Lenehan
   6  *
   7  * This file is subject to the terms and conditions of the GNU General Public
   8  * License.  See the file "COPYING" in the main directory of this archive
   9  * for more details.
  10  */
  11 #include <linux/platform_device.h>
  12 #include <linux/init.h>
  13 #include <linux/serial.h>
  14 #include <linux/io.h>
  15 #include <linux/sh_timer.h>
  16 #include <linux/serial_sci.h>
  17
  18 static struct resource rtc_resources[] = {
  19         [0] = {
  20                 .start  = 0xffc80000,
  21                 .end    = 0xffc80000 + 0x58 - 1,
  22                 .flags  = IORESOURCE_IO,
  23         },
  24         [1] = {
  25                 /* Shared Period/Carry/Alarm IRQ */
  26                 .start  = 20,
  27                 .flags  = IORESOURCE_IRQ,
  28         },
  29 };
  30
  31 static struct platform_device rtc_device = {
  32         .name           = "sh-rtc",
  33         .id             = -1,
  34         .num_resources  = ARRAY_SIZE(rtc_resources),
  35         .resource       = rtc_resources,
  36 };
  37
  38 static struct plat_sci_port scif0_platform_data = {
  39         .mapbase        = 0xffe00000,
  40         .flags          = UPF_BOOT_AUTOCONF,
  41         .type           = PORT_SCI,
  42         .irqs           = { 23, 23, 23, 0 },
  43 };
  44
  45 static struct platform_device scif0_device = {
  46         .name           = "sh-sci",
  47         .id             = 0,
  48         .dev            = {
  49                 .platform_data  = &scif0_platform_data,
  50         },
  51 };
  52
  53 static struct plat_sci_port scif1_platform_data = {
  54         .mapbase        = 0xffe80000,
  55         .flags          = UPF_BOOT_AUTOCONF,
  56         .type           = PORT_SCIF,
  57         .irqs           = { 40, 40, 40, 40 },
  58 };
  59
  60 static struct platform_device scif1_device = {
  61         .name           = "sh-sci",
  62         .id             = 1,
  63         .dev            = {
  64                 .platform_data  = &scif1_platform_data,
  65         },
  66 };
  67
  68 static struct sh_timer_config tmu0_platform_data = {
  69         .name = "TMU0",
  70         .channel_offset = 0x04,
  71         .timer_bit = 0,
  72         .clk = "peripheral_clk",
  73         .clockevent_rating = 200,
  74 };
  75
  76 static struct resource tmu0_resources[] = {
  77         [0] = {
  78                 .name   = "TMU0",
  79                 .start  = 0xffd80008,
  80                 .end    = 0xffd80013,
  81                 .flags  = IORESOURCE_MEM,
  82         },
  83         [1] = {
  84                 .start  = 16,
  85                 .flags  = IORESOURCE_IRQ,
  86         },
  87 };
  88
  89 static struct platform_device tmu0_device = {
  90         .name           = "sh_tmu",
  91         .id             = 0,
  92         .dev = {
  93                 .platform_data  = &tmu0_platform_data,
  94         },
  95         .resource       = tmu0_resources,
  96         .num_resources  = ARRAY_SIZE(tmu0_resources),
  97 };
  98
  99 static struct sh_timer_config tmu1_platform_data = {
 100         .name = "TMU1",
 101         .channel_offset = 0x10,
 102         .timer_bit = 1,
 103         .clk = "peripheral_clk",
 104         .clocksource_rating = 200,
 105 };
 106
 107 static struct resource tmu1_resources[] = {
 108         [0] = {
 109                 .name   = "TMU1",
 110                 .start  = 0xffd80014,
 111                 .end    = 0xffd8001f,
 112                 .flags  = IORESOURCE_MEM,
 113         },
 114         [1] = {
 115                 .start  = 17,
 116                 .flags  = IORESOURCE_IRQ,
 117         },
 118 };
 119
 120 static struct platform_device tmu1_device = {
 121         .name           = "sh_tmu",
 122         .id             = 1,
 123         .dev = {
 124                 .platform_data  = &tmu1_platform_data,
 125         },
 126         .resource       = tmu1_resources,
 127         .num_resources  = ARRAY_SIZE(tmu1_resources),
 128 };
 129
 130 static struct sh_timer_config tmu2_platform_data = {
 131         .name = "TMU2",
 132         .channel_offset = 0x1c,
 133         .timer_bit = 2,
 134         .clk = "peripheral_clk",
 135 };
 136
 137 static struct resource tmu2_resources[] = {
 138         [0] = {
 139                 .name   = "TMU2",
 140                 .start  = 0xffd80020,
 141                 .end    = 0xffd8002f,
 142                 .flags  = IORESOURCE_MEM,
 143         },
 144         [1] = {
 145                 .start  = 18,
 146                 .flags  = IORESOURCE_IRQ,
 147         },
 148 };
 149
 150 static struct platform_device tmu2_device = {
 151         .name           = "sh_tmu",
 152         .id             = 2,
 153         .dev = {
 154                 .platform_data  = &tmu2_platform_data,
 155         },
 156         .resource       = tmu2_resources,
 157         .num_resources  = ARRAY_SIZE(tmu2_resources),
 158 };
 159
 160 /* SH7750R, SH7751 and SH7751R all have two extra timer channels */
 161 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
 162         defined(CONFIG_CPU_SUBTYPE_SH7751) || \
 163         defined(CONFIG_CPU_SUBTYPE_SH7751R)
 164
 165 static struct sh_timer_config tmu3_platform_data = {
 166         .name = "TMU3",
 167         .channel_offset = 0x04,
 168         .timer_bit = 0,
 169         .clk = "peripheral_clk",
 170 };
 171
 172 static struct resource tmu3_resources[] = {
 173         [0] = {
 174                 .name   = "TMU3",
 175                 .start  = 0xfe100008,
 176                 .end    = 0xfe100013,
 177                 .flags  = IORESOURCE_MEM,
 178         },
 179         [1] = {
 180                 .start  = 72,
 181                 .flags  = IORESOURCE_IRQ,
 182         },
 183 };
 184
 185 static struct platform_device tmu3_device = {
 186         .name           = "sh_tmu",
 187         .id             = 3,
 188         .dev = {
 189                 .platform_data  = &tmu3_platform_data,
 190         },
 191         .resource       = tmu3_resources,
 192         .num_resources  = ARRAY_SIZE(tmu3_resources),
 193 };
 194
 195 static struct sh_timer_config tmu4_platform_data = {
 196         .name = "TMU4",
 197         .channel_offset = 0x10,
 198         .timer_bit = 1,
 199         .clk = "peripheral_clk",
 200 };
 201
 202 static struct resource tmu4_resources[] = {
 203         [0] = {
 204                 .name   = "TMU4",
 205                 .start  = 0xfe100014,
 206                 .end    = 0xfe10001f,
 207                 .flags  = IORESOURCE_MEM,
 208         },
 209         [1] = {
 210                 .start  = 76,
 211                 .flags  = IORESOURCE_IRQ,
 212         },
 213 };
 214
 215 static struct platform_device tmu4_device = {
 216         .name           = "sh_tmu",
 217         .id             = 4,
 218         .dev = {
 219                 .platform_data  = &tmu4_platform_data,
 220         },
 221         .resource       = tmu4_resources,
 222         .num_resources  = ARRAY_SIZE(tmu4_resources),
 223 };
 224
 225 #endif
 226
 227 static struct platform_device *sh7750_devices[] __initdata = {
 228         &scif0_device,
 229         &scif1_device,
 230         &rtc_device,
 231         &tmu0_device,
 232         &tmu1_device,
 233         &tmu2_device,
 234 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
 235         defined(CONFIG_CPU_SUBTYPE_SH7751) || \
 236         defined(CONFIG_CPU_SUBTYPE_SH7751R)
 237         &tmu3_device,
 238         &tmu4_device,
 239 #endif
 240 };
 241
 242 static int __init sh7750_devices_setup(void)
 243 {
 244         return platform_add_devices(sh7750_devices,
 245                                     ARRAY_SIZE(sh7750_devices));
 246 }
 247 arch_initcall(sh7750_devices_setup);
 248
 249 static struct platform_device *sh7750_early_devices[] __initdata = {
 250         &scif0_device,
 251         &scif1_device,
 252         &tmu0_device,
 253         &tmu1_device,
 254         &tmu2_device,
 255 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
 256         defined(CONFIG_CPU_SUBTYPE_SH7751) || \
 257         defined(CONFIG_CPU_SUBTYPE_SH7751R)
 258         &tmu3_device,
 259         &tmu4_device,
 260 #endif
 261 };
 262
 263 void __init plat_early_device_setup(void)
 264 {
 265         early_platform_add_devices(sh7750_early_devices,
 266                                    ARRAY_SIZE(sh7750_early_devices));
 267 }
 268
 269 enum {
 270         UNUSED = 0,
 271
 272         /* interrupt sources */
 273         IRL0, IRL1, IRL2, IRL3, /* only IRLM mode supported */
 274         HUDI, GPIOI, DMAC,
 275         PCIC0_PCISERR, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
 276         PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3,
 277         TMU3, TMU4, TMU0, TMU1, TMU2, RTC, SCI1, SCIF, WDT, REF,
 278
 279         /* interrupt groups */
 280         PCIC1,
 281 };
 282
 283 static struct intc_vect vectors[] __initdata = {
 284         INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620),
 285         INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
 286         INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),
 287         INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
 288         INTC_VECT(RTC, 0x4c0),
 289         INTC_VECT(SCI1, 0x4e0), INTC_VECT(SCI1, 0x500),
 290         INTC_VECT(SCI1, 0x520), INTC_VECT(SCI1, 0x540),
 291         INTC_VECT(SCIF, 0x700), INTC_VECT(SCIF, 0x720),
 292         INTC_VECT(SCIF, 0x740), INTC_VECT(SCIF, 0x760),
 293         INTC_VECT(WDT, 0x560),
 294         INTC_VECT(REF, 0x580), INTC_VECT(REF, 0x5a0),
 295 };
 296
 297 static struct intc_prio_reg prio_registers[] __initdata = {
 298         { 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
 299         { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } },
 300         { 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, SCIF, HUDI } },
 301         { 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } },
 302         { 0xfe080000, 0, 32, 4, /* INTPRI00 */ { 0, 0, 0, 0,
 303                                                  TMU4, TMU3,
 304                                                  PCIC1, PCIC0_PCISERR } },
 305 };
 306
 307 static DECLARE_INTC_DESC(intc_desc, "sh7750", vectors, NULL,
 308                          NULL, prio_registers, NULL);
 309
 310 /* SH7750, SH7750S, SH7751 and SH7091 all have 4-channel DMA controllers */
 311 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
 312         defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
 313         defined(CONFIG_CPU_SUBTYPE_SH7751) || \
 314         defined(CONFIG_CPU_SUBTYPE_SH7091)
 315 static struct intc_vect vectors_dma4[] __initdata = {
 316         INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
 317         INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
 318         INTC_VECT(DMAC, 0x6c0),
 319 };
 320
 321 static DECLARE_INTC_DESC(intc_desc_dma4, "sh7750_dma4",
 322                          vectors_dma4, NULL,
 323                          NULL, prio_registers, NULL);
 324 #endif
 325
 326 /* SH7750R and SH7751R both have 8-channel DMA controllers */
 327 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || defined(CONFIG_CPU_SUBTYPE_SH7751R)
 328 static struct intc_vect vectors_dma8[] __initdata = {
 329         INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
 330         INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
 331         INTC_VECT(DMAC, 0x780), INTC_VECT(DMAC, 0x7a0),
 332         INTC_VECT(DMAC, 0x7c0), INTC_VECT(DMAC, 0x7e0),
 333         INTC_VECT(DMAC, 0x6c0),
 334 };
 335
 336 static DECLARE_INTC_DESC(intc_desc_dma8, "sh7750_dma8",
 337                          vectors_dma8, NULL,
 338                          NULL, prio_registers, NULL);
 339 #endif
 340
 341 /* SH7750R, SH7751 and SH7751R all have two extra timer channels */
 342 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
 343         defined(CONFIG_CPU_SUBTYPE_SH7751) || \
 344         defined(CONFIG_CPU_SUBTYPE_SH7751R)
 345 static struct intc_vect vectors_tmu34[] __initdata = {
 346         INTC_VECT(TMU3, 0xb00), INTC_VECT(TMU4, 0xb80),
 347 };
 348
 349 static struct intc_mask_reg mask_registers[] __initdata = {
 350         { 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */
 351           { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 352             0, 0, 0, 0, 0, 0, TMU4, TMU3,
 353             PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
 354             PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2,
 355             PCIC1_PCIDMA3, PCIC0_PCISERR } },
 356 };
 357
 358 static DECLARE_INTC_DESC(intc_desc_tmu34, "sh7750_tmu34",
 359                          vectors_tmu34, NULL,
 360                          mask_registers, prio_registers, NULL);
 361 #endif
 362
 363 /* SH7750S, SH7750R, SH7751 and SH7751R all have IRLM priority registers */
 364 static struct intc_vect vectors_irlm[] __initdata = {
 365         INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0),
 366         INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360),
 367 };
 368
 369 static DECLARE_INTC_DESC(intc_desc_irlm, "sh7750_irlm", vectors_irlm, NULL,
 370                          NULL, prio_registers, NULL);
 371
 372 /* SH7751 and SH7751R both have PCI */
 373 #if defined(CONFIG_CPU_SUBTYPE_SH7751) || defined(CONFIG_CPU_SUBTYPE_SH7751R)
 374 static struct intc_vect vectors_pci[] __initdata = {
 375         INTC_VECT(PCIC0_PCISERR, 0xa00), INTC_VECT(PCIC1_PCIERR, 0xae0),
 376         INTC_VECT(PCIC1_PCIPWDWN, 0xac0), INTC_VECT(PCIC1_PCIPWON, 0xaa0),
 377         INTC_VECT(PCIC1_PCIDMA0, 0xa80), INTC_VECT(PCIC1_PCIDMA1, 0xa60),
 378         INTC_VECT(PCIC1_PCIDMA2, 0xa40), INTC_VECT(PCIC1_PCIDMA3, 0xa20),
 379 };
 380
 381 static struct intc_group groups_pci[] __initdata = {
 382         INTC_GROUP(PCIC1, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
 383                    PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3),
 384 };
 385
 386 static DECLARE_INTC_DESC(intc_desc_pci, "sh7750_pci", vectors_pci, groups_pci,
 387                          mask_registers, prio_registers, NULL);
 388 #endif
 389
 390 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
 391         defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
 392         defined(CONFIG_CPU_SUBTYPE_SH7091)
 393 void __init plat_irq_setup(void)
 394 {
 395         /*
 396          * same vectors for SH7750, SH7750S and SH7091 except for IRLM,
 397          * see below..
 398          */
 399         register_intc_controller(&intc_desc);
 400         register_intc_controller(&intc_desc_dma4);
 401 }
 402 #endif
 403
 404 #if defined(CONFIG_CPU_SUBTYPE_SH7750R)
 405 void __init plat_irq_setup(void)
 406 {
 407         register_intc_controller(&intc_desc);
 408         register_intc_controller(&intc_desc_dma8);
 409         register_intc_controller(&intc_desc_tmu34);
 410 }
 411 #endif
 412
 413 #if defined(CONFIG_CPU_SUBTYPE_SH7751)
 414 void __init plat_irq_setup(void)
 415 {
 416         register_intc_controller(&intc_desc);
 417         register_intc_controller(&intc_desc_dma4);
 418         register_intc_controller(&intc_desc_tmu34);
 419         register_intc_controller(&intc_desc_pci);
 420 }
 421 #endif
 422
 423 #if defined(CONFIG_CPU_SUBTYPE_SH7751R)
 424 void __init plat_irq_setup(void)
 425 {
 426         register_intc_controller(&intc_desc);
 427         register_intc_controller(&intc_desc_dma8);
 428         register_intc_controller(&intc_desc_tmu34);
 429         register_intc_controller(&intc_desc_pci);
 430 }
 431 #endif
 432
 433 #define INTC_ICR        0xffd00000UL
 434 #define INTC_ICR_IRLM   (1<<7)
 435
 436 void __init plat_irq_setup_pins(int mode)
 437 {
 438 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7091)
 439         BUG(); /* impossible to mask interrupts on SH7750 and SH7091 */
 440         return;
 441 #endif
 442
 443         switch (mode) {
 444         case IRQ_MODE_IRQ: /* individual interrupt mode for IRL3-0 */
 445                 __raw_writew(__raw_readw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
 446                 register_intc_controller(&intc_desc_irlm);
 447                 break;
 448         default:
 449                 BUG();
 450         }
 451 }