sh: Reworked SH7780 PCI initialization.
[linux-2.6.git] / arch / sh / include / cpu-sh3 / cpu / dma.h
1 #ifndef __ASM_CPU_SH3_DMA_H
2 #define __ASM_CPU_SH3_DMA_H
3
4 #if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
5     defined(CONFIG_CPU_SUBTYPE_SH7721) || \
6     defined(CONFIG_CPU_SUBTYPE_SH7710) || \
7     defined(CONFIG_CPU_SUBTYPE_SH7712)
8 #define SH_DMAC_BASE0   0xa4010020
9 #else /* SH7705/06/07/09 */
10 #define SH_DMAC_BASE0   0xa4000020
11 #endif
12
13 #define DMTE0_IRQ       48
14 #define DMTE4_IRQ       76
15
16 /* Definitions for the SuperH DMAC */
17 #define TM_BURST        0x00000020
18 #define TS_8            0x00000000
19 #define TS_16           0x00000008
20 #define TS_32           0x00000010
21 #define TS_128          0x00000018
22
23 #define CHCR_TS_MASK    0x18
24 #define CHCR_TS_SHIFT   3
25
26 #define DMAOR_INIT      DMAOR_DME
27
28 /*
29  * The SuperH DMAC supports a number of transmit sizes, we list them here,
30  * with their respective values as they appear in the CHCR registers.
31  */
32 enum {
33         XMIT_SZ_8BIT,
34         XMIT_SZ_16BIT,
35         XMIT_SZ_32BIT,
36         XMIT_SZ_128BIT,
37 };
38
39 static unsigned int ts_shift[] __maybe_unused = {
40         [XMIT_SZ_8BIT]          = 0,
41         [XMIT_SZ_16BIT]         = 1,
42         [XMIT_SZ_32BIT]         = 2,
43         [XMIT_SZ_128BIT]        = 4,
44 };
45
46 #endif /* __ASM_CPU_SH3_DMA_H */