sh: Add support for R7780RP and R7780MP boards.
[linux-2.6.git] / arch / sh / drivers / pci / pci-auto.c
1 /*
2  * PCI autoconfiguration library
3  *
4  * Author: Matt Porter <mporter@mvista.com>
5  *
6  * Copyright 2000, 2001 MontaVista Software Inc.
7  * Copyright 2001 Bradley D. LaRonde <brad@ltc.com>
8  * Copyright 2003 Paul Mundt <lethal@linux-sh.org>
9  *
10  * This program is free software; you can redistribute  it and/or modify it
11  * under  the terms of  the GNU General  Public License as published by the
12  * Free Software Foundation;  either version 2 of the  License, or (at your
13  * option) any later version.
14  */
15
16 /*
17  * Modified for MIPS by Jun Sun, jsun@mvista.com
18  *
19  * . Simplify the interface between pci_auto and the rest: a single function.
20  * . Assign resources from low address to upper address.
21  * . change most int to u32.
22  *
23  * Further modified to include it as mips generic code, ppopov@mvista.com.
24  *
25  * 2001-10-26  Bradley D. LaRonde <brad@ltc.com>
26  * - Add a top_bus argument to the "early config" functions so that
27  *   they can set a fake parent bus pointer to convince the underlying
28  *   pci ops to use type 1 configuration for sub busses.
29  * - Set bridge base and limit registers correctly.
30  * - Align io and memory base properly before and after bridge setup.
31  * - Don't fall through to pci_setup_bars for bridge.
32  * - Reformat the debug output to look more like lspci's output.
33  *
34  * Cloned for SuperH by M. R. Brown, mrbrown@0xd6.org
35  *
36  * 2003-08-05  Paul Mundt <lethal@linux-sh.org>
37  * - Don't update the BAR values on systems that already have valid addresses
38  *   and don't want these updated for whatever reason, by way of a new config
39  *   option check. However, we still read in the old BAR values so that they
40  *   can still be reported through the debug output.
41  */
42
43 #include <linux/kernel.h>
44 #include <linux/init.h>
45 #include <linux/types.h>
46 #include <linux/pci.h>
47
48 #define DEBUG
49 #ifdef  DEBUG
50 #define DBG(x...)       printk(x)
51 #else
52 #define DBG(x...)
53 #endif
54
55 /*
56  * These functions are used early on before PCI scanning is done
57  * and all of the pci_dev and pci_bus structures have been created.
58  */
59 static struct pci_dev *fake_pci_dev(struct pci_channel *hose,
60         int top_bus, int busnr, int devfn)
61 {
62         static struct pci_dev dev;
63         static struct pci_bus bus;
64
65         dev.bus = &bus;
66         dev.sysdata = hose;
67         dev.devfn = devfn;
68         bus.number = busnr;
69         bus.ops = hose->pci_ops;
70
71         if(busnr != top_bus)
72                 /* Fake a parent bus structure. */
73                 bus.parent = &bus;
74         else
75                 bus.parent = NULL;
76
77         return &dev;
78 }
79
80 #define EARLY_PCI_OP(rw, size, type)                                    \
81 int early_##rw##_config_##size(struct pci_channel *hose,                \
82         int top_bus, int bus, int devfn, int offset, type value)        \
83 {                                                                       \
84         return pci_##rw##_config_##size(                                \
85                 fake_pci_dev(hose, top_bus, bus, devfn),                \
86                 offset, value);                                         \
87 }
88
89 EARLY_PCI_OP(read, byte, u8 *)
90 EARLY_PCI_OP(read, word, u16 *)
91 EARLY_PCI_OP(read, dword, u32 *)
92 EARLY_PCI_OP(write, byte, u8)
93 EARLY_PCI_OP(write, word, u16)
94 EARLY_PCI_OP(write, dword, u32)
95
96 static struct resource *io_resource_inuse;
97 static struct resource *mem_resource_inuse;
98
99 static u32 pciauto_lower_iospc;
100 static u32 pciauto_upper_iospc;
101
102 static u32 pciauto_lower_memspc;
103 static u32 pciauto_upper_memspc;
104
105 static void __init
106 pciauto_setup_bars(struct pci_channel *hose,
107                    int top_bus,
108                    int current_bus,
109                    int pci_devfn,
110                    int bar_limit)
111 {
112         u32 bar_response, bar_size, bar_value;
113         u32 bar, addr_mask, bar_nr = 0;
114         u32 * upper_limit;
115         u32 * lower_limit;
116         int found_mem64 = 0;
117
118         for (bar = PCI_BASE_ADDRESS_0; bar <= bar_limit; bar+=4) {
119                 u32 bar_addr;
120
121                 /* Read the old BAR value */
122                 early_read_config_dword(hose, top_bus,
123                                         current_bus,
124                                         pci_devfn,
125                                         bar,
126                                         &bar_addr);
127
128                 /* Tickle the BAR and get the response */
129                 early_write_config_dword(hose, top_bus,
130                                          current_bus,
131                                          pci_devfn,
132                                          bar,
133                                          0xffffffff);
134
135                 early_read_config_dword(hose, top_bus,
136                                         current_bus,
137                                         pci_devfn,
138                                         bar,
139                                         &bar_response);
140
141                 /*
142                  * Write the old BAR value back out, only update the BAR
143                  * if we implicitly want resources to be updated, which
144                  * is done by the generic code further down. -- PFM.
145                  */
146                 early_write_config_dword(hose, top_bus,
147                                          current_bus,
148                                          pci_devfn,
149                                          bar,
150                                          bar_addr);
151
152                 /* If BAR is not implemented go to the next BAR */
153                 if (!bar_response)
154                         continue;
155
156                 /*
157                  * Workaround for a BAR that doesn't use its upper word,
158                  * like the ALi 1535D+ PCI DC-97 Controller Modem (M5457).
159                  * bdl <brad@ltc.com>
160                  */
161                 if (!(bar_response & 0xffff0000))
162                         bar_response |= 0xffff0000;
163
164 retry:
165                 /* Check the BAR type and set our address mask */
166                 if (bar_response & PCI_BASE_ADDRESS_SPACE) {
167                         addr_mask = PCI_BASE_ADDRESS_IO_MASK;
168                         upper_limit = &pciauto_upper_iospc;
169                         lower_limit = &pciauto_lower_iospc;
170                         DBG("        I/O");
171                 } else {
172                         if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
173                             PCI_BASE_ADDRESS_MEM_TYPE_64)
174                                 found_mem64 = 1;
175
176                         addr_mask = PCI_BASE_ADDRESS_MEM_MASK;
177                         upper_limit = &pciauto_upper_memspc;
178                         lower_limit = &pciauto_lower_memspc;
179                         DBG("        Mem");
180                 }
181
182
183                 /* Calculate requested size */
184                 bar_size = ~(bar_response & addr_mask) + 1;
185
186                 /* Allocate a base address */
187                 bar_value = ((*lower_limit - 1) & ~(bar_size - 1)) + bar_size;
188
189                 if ((bar_value + bar_size) > *upper_limit) {
190                         if (bar_response & PCI_BASE_ADDRESS_SPACE) {
191                                 if (io_resource_inuse->child) {
192                                         io_resource_inuse =
193                                                 io_resource_inuse->child;
194                                         pciauto_lower_iospc =
195                                                 io_resource_inuse->start;
196                                         pciauto_upper_iospc =
197                                                 io_resource_inuse->end + 1;
198                                         goto retry;
199                                 }
200
201                         } else {
202                                 if (mem_resource_inuse->child) {
203                                         mem_resource_inuse =
204                                                 mem_resource_inuse->child;
205                                         pciauto_lower_memspc =
206                                                 mem_resource_inuse->start;
207                                         pciauto_upper_memspc =
208                                                 mem_resource_inuse->end + 1;
209                                         goto retry;
210                                 }
211                         }
212                         DBG(" unavailable -- skipping, value %x size %x\n",
213                                         bar_value, bar_size);
214                         continue;
215                 }
216
217 #ifdef CONFIG_PCI_AUTO_UPDATE_RESOURCES
218                 /* Write it out and update our limit */
219                 early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
220                                          bar, bar_value);
221 #endif
222
223                 *lower_limit = bar_value + bar_size;
224
225                 /*
226                  * If we are a 64-bit decoder then increment to the
227                  * upper 32 bits of the bar and force it to locate
228                  * in the lower 4GB of memory.
229                  */
230                 if (found_mem64) {
231                         bar += 4;
232                         early_write_config_dword(hose, top_bus,
233                                                  current_bus,
234                                                  pci_devfn,
235                                                  bar,
236                                                  0x00000000);
237                 }
238
239                 DBG(" at 0x%.8x [size=0x%x]\n", bar_value, bar_size);
240
241                 bar_nr++;
242         }
243
244 }
245
246 static void __init
247 pciauto_prescan_setup_bridge(struct pci_channel *hose,
248                              int top_bus,
249                              int current_bus,
250                              int pci_devfn,
251                              int sub_bus)
252 {
253         /* Configure bus number registers */
254         early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
255                                 PCI_PRIMARY_BUS, current_bus);
256         early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
257                                 PCI_SECONDARY_BUS, sub_bus + 1);
258         early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
259                                 PCI_SUBORDINATE_BUS, 0xff);
260
261         /* Align memory and I/O to 1MB and 4KB boundaries. */
262         pciauto_lower_memspc = (pciauto_lower_memspc + (0x100000 - 1))
263                 & ~(0x100000 - 1);
264         pciauto_lower_iospc = (pciauto_lower_iospc + (0x1000 - 1))
265                 & ~(0x1000 - 1);
266
267         /* Set base (lower limit) of address range behind bridge. */
268         early_write_config_word(hose, top_bus, current_bus, pci_devfn,
269                 PCI_MEMORY_BASE, pciauto_lower_memspc >> 16);
270         early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
271                 PCI_IO_BASE, (pciauto_lower_iospc & 0x0000f000) >> 8);
272         early_write_config_word(hose, top_bus, current_bus, pci_devfn,
273                 PCI_IO_BASE_UPPER16, pciauto_lower_iospc >> 16);
274
275         /* We don't support prefetchable memory for now, so disable */
276         early_write_config_word(hose, top_bus, current_bus, pci_devfn,
277                                 PCI_PREF_MEMORY_BASE, 0);
278         early_write_config_word(hose, top_bus, current_bus, pci_devfn,
279                                 PCI_PREF_MEMORY_LIMIT, 0);
280 }
281
282 static void __init
283 pciauto_postscan_setup_bridge(struct pci_channel *hose,
284                               int top_bus,
285                               int current_bus,
286                               int pci_devfn,
287                               int sub_bus)
288 {
289         u32 temp;
290
291         /*
292          * [jsun] we always bump up baselines a little, so that if there
293          * nothing behind P2P bridge, we don't wind up overlapping IO/MEM
294          * spaces.
295          */
296         pciauto_lower_memspc += 1;
297         pciauto_lower_iospc += 1;
298
299         /* Configure bus number registers */
300         early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
301                                 PCI_SUBORDINATE_BUS, sub_bus);
302
303         /* Set upper limit of address range behind bridge. */
304         early_write_config_word(hose, top_bus, current_bus, pci_devfn,
305                 PCI_MEMORY_LIMIT, pciauto_lower_memspc >> 16);
306         early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
307                 PCI_IO_LIMIT, (pciauto_lower_iospc & 0x0000f000) >> 8);
308         early_write_config_word(hose, top_bus, current_bus, pci_devfn,
309                 PCI_IO_LIMIT_UPPER16, pciauto_lower_iospc >> 16);
310
311         /* Align memory and I/O to 1MB and 4KB boundaries. */
312         pciauto_lower_memspc = (pciauto_lower_memspc + (0x100000 - 1))
313                 & ~(0x100000 - 1);
314         pciauto_lower_iospc = (pciauto_lower_iospc + (0x1000 - 1))
315                 & ~(0x1000 - 1);
316
317         /* Enable memory and I/O accesses, enable bus master */
318         early_read_config_dword(hose, top_bus, current_bus, pci_devfn,
319                 PCI_COMMAND, &temp);
320         early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
321                 PCI_COMMAND, temp | PCI_COMMAND_IO | PCI_COMMAND_MEMORY
322                 | PCI_COMMAND_MASTER);
323 }
324
325 static void __init
326 pciauto_prescan_setup_cardbus_bridge(struct pci_channel *hose,
327                         int top_bus,
328                         int current_bus,
329                         int pci_devfn,
330                         int sub_bus)
331 {
332         /* Configure bus number registers */
333         early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
334                                 PCI_PRIMARY_BUS, current_bus);
335         early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
336                                 PCI_SECONDARY_BUS, sub_bus + 1);
337         early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
338                                 PCI_SUBORDINATE_BUS, 0xff);
339
340         /* Align memory and I/O to 4KB and 4 byte boundaries. */
341         pciauto_lower_memspc = (pciauto_lower_memspc + (0x1000 - 1))
342                 & ~(0x1000 - 1);
343         pciauto_lower_iospc = (pciauto_lower_iospc + (0x4 - 1))
344                 & ~(0x4 - 1);
345
346         early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
347                 PCI_CB_MEMORY_BASE_0, pciauto_lower_memspc);
348         early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
349                 PCI_CB_IO_BASE_0, pciauto_lower_iospc);
350 }
351
352 static void __init
353 pciauto_postscan_setup_cardbus_bridge(struct pci_channel *hose,
354                         int top_bus,
355                         int current_bus,
356                         int pci_devfn,
357                         int sub_bus)
358 {
359         u32 temp;
360
361 #if !defined(CONFIG_SH_HS7751RVOIP) && !defined(CONFIG_SH_RTS7751R2D) && !defined(CONFIG_SH_R7780RP)
362         /*
363          * [jsun] we always bump up baselines a little, so that if there
364          * nothing behind P2P bridge, we don't wind up overlapping IO/MEM
365          * spaces.
366          */
367         pciauto_lower_memspc += 1;
368         pciauto_lower_iospc += 1;
369 #endif
370
371         /*
372          * Configure subordinate bus number.  The PCI subsystem
373          * bus scan will renumber buses (reserving three additional
374          * for this PCI<->CardBus bridge for the case where a CardBus
375          * adapter contains a P2P or CB2CB bridge.
376          */
377
378         early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
379                                 PCI_SUBORDINATE_BUS, sub_bus);
380
381         /*
382          * Reserve an additional 4MB for mem space and 16KB for
383          * I/O space.  This should cover any additional space
384          * requirement of unusual CardBus devices with
385          * additional bridges that can consume more address space.
386          *
387          * Although pcmcia-cs currently will reprogram bridge
388          * windows, the goal is to add an option to leave them
389          * alone and use the bridge window ranges as the regions
390          * that are searched for free resources upon hot-insertion
391          * of a device.  This will allow a PCI<->CardBus bridge
392          * configured by this routine to happily live behind a
393          * P2P bridge in a system.
394          */
395 #if defined(CONFIG_SH_HS7751RVOIP) || defined(CONFIG_SH_RTS7751R2D) || defined(CONFIG_SH_R7780RP)
396         pciauto_lower_memspc += 0x00400000;
397         pciauto_lower_iospc += 0x00004000;
398 #endif
399
400         /* Align memory and I/O to 4KB and 4 byte boundaries. */
401         pciauto_lower_memspc = (pciauto_lower_memspc + (0x1000 - 1))
402                 & ~(0x1000 - 1);
403         pciauto_lower_iospc = (pciauto_lower_iospc + (0x4 - 1))
404                 & ~(0x4 - 1);
405         /* Set up memory and I/O filter limits, assume 32-bit I/O space */
406         early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
407                 PCI_CB_MEMORY_LIMIT_0, pciauto_lower_memspc - 1);
408         early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
409                 PCI_CB_IO_LIMIT_0, pciauto_lower_iospc - 1);
410
411         /* Enable memory and I/O accesses, enable bus master */
412         early_read_config_dword(hose, top_bus, current_bus, pci_devfn,
413                 PCI_COMMAND, &temp);
414         early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
415                 PCI_COMMAND, temp | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
416                 PCI_COMMAND_MASTER);
417 }
418
419 #define PCIAUTO_IDE_MODE_MASK           0x05
420
421 static int __init
422 pciauto_bus_scan(struct pci_channel *hose, int top_bus, int current_bus)
423 {
424         int sub_bus;
425         u32 pci_devfn, pci_class, cmdstat, found_multi=0;
426         unsigned short vid, did;
427         unsigned char header_type;
428         int devfn_start = 0;
429         int devfn_stop = 0xff;
430
431         sub_bus = current_bus;
432
433         if (hose->first_devfn)
434                 devfn_start = hose->first_devfn;
435         if (hose->last_devfn)
436                 devfn_stop = hose->last_devfn;
437
438         for (pci_devfn=devfn_start; pci_devfn<devfn_stop; pci_devfn++) {
439
440                 if (PCI_FUNC(pci_devfn) && !found_multi)
441                         continue;
442
443                 early_read_config_word(hose, top_bus, current_bus, pci_devfn,
444                                        PCI_VENDOR_ID, &vid);
445
446                 if (vid == 0xffff) continue;
447
448                 early_read_config_byte(hose, top_bus, current_bus, pci_devfn,
449                                        PCI_HEADER_TYPE, &header_type);
450
451                 if (!PCI_FUNC(pci_devfn))
452                         found_multi = header_type & 0x80;
453
454                 early_read_config_word(hose, top_bus, current_bus, pci_devfn,
455                                        PCI_DEVICE_ID, &did);
456
457                 early_read_config_dword(hose, top_bus, current_bus, pci_devfn,
458                                         PCI_CLASS_REVISION, &pci_class);
459
460                 DBG("%.2x:%.2x.%x Class %.4x: %.4x:%.4x",
461                         current_bus, PCI_SLOT(pci_devfn), PCI_FUNC(pci_devfn),
462                         pci_class >> 16, vid, did);
463                 if (pci_class & 0xff)
464                         DBG(" (rev %.2x)", pci_class & 0xff);
465                 DBG("\n");
466
467                 if ((pci_class >> 16) == PCI_CLASS_BRIDGE_PCI) {
468                         DBG("        Bridge: primary=%.2x, secondary=%.2x\n",
469                                 current_bus, sub_bus + 1);
470 #if defined(CONFIG_SH_HS7751RVOIP) || defined(CONFIG_SH_RTS7751R2D) || defined(CONFIG_SH_R7780RP)
471                         pciauto_setup_bars(hose, top_bus, current_bus, pci_devfn, PCI_BASE_ADDRESS_1);
472 #endif
473                         pciauto_prescan_setup_bridge(hose, top_bus, current_bus,
474                                                      pci_devfn, sub_bus);
475                         DBG("Scanning sub bus %.2x, I/O 0x%.8x, Mem 0x%.8x\n",
476                                 sub_bus + 1,
477                                 pciauto_lower_iospc, pciauto_lower_memspc);
478                         sub_bus = pciauto_bus_scan(hose, top_bus, sub_bus+1);
479                         DBG("Back to bus %.2x\n", current_bus);
480                         pciauto_postscan_setup_bridge(hose, top_bus, current_bus,
481                                                         pci_devfn, sub_bus);
482                         continue;
483                 } else if ((pci_class >> 16) == PCI_CLASS_BRIDGE_CARDBUS) {
484                         DBG("  CARDBUS  Bridge: primary=%.2x, secondary=%.2x\n",
485                                 current_bus, sub_bus + 1);
486                         DBG("PCI Autoconfig: Found CardBus bridge, device %d function %d\n", PCI_SLOT(pci_devfn), PCI_FUNC(pci_devfn));
487                         /* Place CardBus Socket/ExCA registers */
488                         pciauto_setup_bars(hose, top_bus, current_bus, pci_devfn, PCI_BASE_ADDRESS_0);
489
490                         pciauto_prescan_setup_cardbus_bridge(hose, top_bus,
491                                         current_bus, pci_devfn, sub_bus);
492
493                         DBG("Scanning sub bus %.2x, I/O 0x%.8x, Mem 0x%.8x\n",
494                                 sub_bus + 1,
495                                 pciauto_lower_iospc, pciauto_lower_memspc);
496                         sub_bus = pciauto_bus_scan(hose, top_bus, sub_bus+1);
497                         DBG("Back to bus %.2x, sub_bus is %x\n", current_bus, sub_bus);
498                         pciauto_postscan_setup_cardbus_bridge(hose, top_bus,
499                                         current_bus, pci_devfn, sub_bus);
500                         continue;
501                 } else if ((pci_class >> 16) == PCI_CLASS_STORAGE_IDE) {
502
503                         unsigned char prg_iface;
504
505                         early_read_config_byte(hose, top_bus, current_bus,
506                                 pci_devfn, PCI_CLASS_PROG, &prg_iface);
507                         if (!(prg_iface & PCIAUTO_IDE_MODE_MASK)) {
508                                 DBG("Skipping legacy mode IDE controller\n");
509                                 continue;
510                         }
511                 }
512
513                 /*
514                  * Found a peripheral, enable some standard
515                  * settings
516                  */
517                 early_read_config_dword(hose, top_bus, current_bus, pci_devfn,
518                                         PCI_COMMAND, &cmdstat);
519                 early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
520                                          PCI_COMMAND, cmdstat | PCI_COMMAND_IO |
521                                          PCI_COMMAND_MEMORY |
522                                          PCI_COMMAND_MASTER);
523 #if !defined(CONFIG_SH_HS7751RVOIP) && !defined(CONFIG_SH_RTS7751R2D)
524                 early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
525                                         PCI_LATENCY_TIMER, 0x80);
526 #endif
527
528                 /* Allocate PCI I/O and/or memory space */
529                 pciauto_setup_bars(hose, top_bus, current_bus, pci_devfn, PCI_BASE_ADDRESS_5);
530         }
531         return sub_bus;
532 }
533
534 int __init
535 pciauto_assign_resources(int busno, struct pci_channel *hose)
536 {
537         /* setup resource limits */
538         io_resource_inuse = hose->io_resource;
539         mem_resource_inuse = hose->mem_resource;
540
541         pciauto_lower_iospc = io_resource_inuse->start;
542         pciauto_upper_iospc = io_resource_inuse->end + 1;
543         pciauto_lower_memspc = mem_resource_inuse->start;
544         pciauto_upper_memspc = mem_resource_inuse->end + 1;
545         DBG("Autoconfig PCI channel 0x%p\n", hose);
546         DBG("Scanning bus %.2x, I/O 0x%.8x:0x%.8x, Mem 0x%.8x:0x%.8x\n",
547                 busno, pciauto_lower_iospc, pciauto_upper_iospc, 
548                 pciauto_lower_memspc, pciauto_upper_memspc);
549
550         return pciauto_bus_scan(hose, busno, busno);
551 }