cpm2: Rework baud rate generators configuration to support external clocks.
[linux-2.6.git] / arch / powerpc / sysdev / cpm2.c
1 /*
2  * General Purpose functions for the global management of the
3  * 8260 Communication Processor Module.
4  * Copyright (c) 1999-2001 Dan Malek <dan@embeddedalley.com>
5  * Copyright (c) 2000 MontaVista Software, Inc (source@mvista.com)
6  *      2.3.99 Updates
7  *
8  * 2006 (c) MontaVista Software, Inc.
9  * Vitaly Bordug <vbordug@ru.mvista.com>
10  *      Merged to arch/powerpc from arch/ppc/syslib/cpm2_common.c
11  *
12  * This file is licensed under the terms of the GNU General Public License
13  * version 2. This program is licensed "as is" without any warranty of any
14  * kind, whether express or implied.
15  */
16
17 /*
18  *
19  * In addition to the individual control of the communication
20  * channels, there are a few functions that globally affect the
21  * communication processor.
22  *
23  * Buffer descriptors must be allocated from the dual ported memory
24  * space.  The allocator for that is here.  When the communication
25  * process is reset, we reclaim the memory available.  There is
26  * currently no deallocator for this memory.
27  */
28 #include <linux/errno.h>
29 #include <linux/sched.h>
30 #include <linux/kernel.h>
31 #include <linux/param.h>
32 #include <linux/string.h>
33 #include <linux/mm.h>
34 #include <linux/interrupt.h>
35 #include <linux/module.h>
36 #include <linux/of.h>
37
38 #include <asm/io.h>
39 #include <asm/irq.h>
40 #include <asm/mpc8260.h>
41 #include <asm/page.h>
42 #include <asm/pgtable.h>
43 #include <asm/cpm2.h>
44 #include <asm/rheap.h>
45 #include <asm/fs_pd.h>
46
47 #include <sysdev/fsl_soc.h>
48
49 cpm_cpm2_t __iomem *cpmp; /* Pointer to comm processor space */
50
51 /* We allocate this here because it is used almost exclusively for
52  * the communication processor devices.
53  */
54 cpm2_map_t __iomem *cpm2_immr;
55
56 #define CPM_MAP_SIZE    (0x40000)       /* 256k - the PQ3 reserve this amount
57                                            of space for CPM as it is larger
58                                            than on PQ2 */
59
60 void __init cpm2_reset(void)
61 {
62 #ifdef CONFIG_PPC_85xx
63         cpm2_immr = ioremap(CPM_MAP_ADDR, CPM_MAP_SIZE);
64 #else
65         cpm2_immr = ioremap(get_immrbase(), CPM_MAP_SIZE);
66 #endif
67
68         /* Reclaim the DP memory for our use.
69          */
70         cpm_muram_init();
71
72         /* Tell everyone where the comm processor resides.
73          */
74         cpmp = &cpm2_immr->im_cpm;
75
76 #ifndef CONFIG_PPC_EARLY_DEBUG_CPM
77         /* Reset the CPM.
78          */
79         cpm_command(CPM_CR_RST, 0);
80 #endif
81 }
82
83 static DEFINE_SPINLOCK(cmd_lock);
84
85 #define MAX_CR_CMD_LOOPS        10000
86
87 int cpm_command(u32 command, u8 opcode)
88 {
89         int i, ret;
90         unsigned long flags;
91
92         spin_lock_irqsave(&cmd_lock, flags);
93
94         ret = 0;
95         out_be32(&cpmp->cp_cpcr, command | opcode | CPM_CR_FLG);
96         for (i = 0; i < MAX_CR_CMD_LOOPS; i++)
97                 if ((in_be32(&cpmp->cp_cpcr) & CPM_CR_FLG) == 0)
98                         goto out;
99
100         printk(KERN_ERR "%s(): Not able to issue CPM command\n", __func__);
101         ret = -EIO;
102 out:
103         spin_unlock_irqrestore(&cmd_lock, flags);
104         return ret;
105 }
106 EXPORT_SYMBOL(cpm_command);
107
108 /* Set a baud rate generator.  This needs lots of work.  There are
109  * eight BRGs, which can be connected to the CPM channels or output
110  * as clocks.  The BRGs are in two different block of internal
111  * memory mapped space.
112  * The baud rate clock is the system clock divided by something.
113  * It was set up long ago during the initial boot phase and is
114  * is given to us.
115  * Baud rate clocks are zero-based in the driver code (as that maps
116  * to port numbers).  Documentation uses 1-based numbering.
117  */
118 void __cpm2_setbrg(uint brg, uint rate, uint clk, int div16, int src)
119 {
120         u32 __iomem *bp;
121         u32 val;
122
123         /* This is good enough to get SMCs running.....
124         */
125         if (brg < 4) {
126                 bp = cpm2_map_size(im_brgc1, 16);
127         } else {
128                 bp = cpm2_map_size(im_brgc5, 16);
129                 brg -= 4;
130         }
131         bp += brg;
132         val = (((clk / rate) - 1) << 1) | CPM_BRG_EN | src;
133         if (div16)
134                 val |= CPM_BRG_DIV16;
135
136         out_be32(bp, val);
137         cpm2_unmap(bp);
138 }
139 EXPORT_SYMBOL(__cpm2_setbrg);
140
141 int cpm2_clk_setup(enum cpm_clk_target target, int clock, int mode)
142 {
143         int ret = 0;
144         int shift;
145         int i, bits = 0;
146         cpmux_t __iomem *im_cpmux;
147         u32 __iomem *reg;
148         u32 mask = 7;
149
150         u8 clk_map[][3] = {
151                 {CPM_CLK_FCC1, CPM_BRG5, 0},
152                 {CPM_CLK_FCC1, CPM_BRG6, 1},
153                 {CPM_CLK_FCC1, CPM_BRG7, 2},
154                 {CPM_CLK_FCC1, CPM_BRG8, 3},
155                 {CPM_CLK_FCC1, CPM_CLK9, 4},
156                 {CPM_CLK_FCC1, CPM_CLK10, 5},
157                 {CPM_CLK_FCC1, CPM_CLK11, 6},
158                 {CPM_CLK_FCC1, CPM_CLK12, 7},
159                 {CPM_CLK_FCC2, CPM_BRG5, 0},
160                 {CPM_CLK_FCC2, CPM_BRG6, 1},
161                 {CPM_CLK_FCC2, CPM_BRG7, 2},
162                 {CPM_CLK_FCC2, CPM_BRG8, 3},
163                 {CPM_CLK_FCC2, CPM_CLK13, 4},
164                 {CPM_CLK_FCC2, CPM_CLK14, 5},
165                 {CPM_CLK_FCC2, CPM_CLK15, 6},
166                 {CPM_CLK_FCC2, CPM_CLK16, 7},
167                 {CPM_CLK_FCC3, CPM_BRG5, 0},
168                 {CPM_CLK_FCC3, CPM_BRG6, 1},
169                 {CPM_CLK_FCC3, CPM_BRG7, 2},
170                 {CPM_CLK_FCC3, CPM_BRG8, 3},
171                 {CPM_CLK_FCC3, CPM_CLK13, 4},
172                 {CPM_CLK_FCC3, CPM_CLK14, 5},
173                 {CPM_CLK_FCC3, CPM_CLK15, 6},
174                 {CPM_CLK_FCC3, CPM_CLK16, 7},
175                 {CPM_CLK_SCC1, CPM_BRG1, 0},
176                 {CPM_CLK_SCC1, CPM_BRG2, 1},
177                 {CPM_CLK_SCC1, CPM_BRG3, 2},
178                 {CPM_CLK_SCC1, CPM_BRG4, 3},
179                 {CPM_CLK_SCC1, CPM_CLK11, 4},
180                 {CPM_CLK_SCC1, CPM_CLK12, 5},
181                 {CPM_CLK_SCC1, CPM_CLK3, 6},
182                 {CPM_CLK_SCC1, CPM_CLK4, 7},
183                 {CPM_CLK_SCC2, CPM_BRG1, 0},
184                 {CPM_CLK_SCC2, CPM_BRG2, 1},
185                 {CPM_CLK_SCC2, CPM_BRG3, 2},
186                 {CPM_CLK_SCC2, CPM_BRG4, 3},
187                 {CPM_CLK_SCC2, CPM_CLK11, 4},
188                 {CPM_CLK_SCC2, CPM_CLK12, 5},
189                 {CPM_CLK_SCC2, CPM_CLK3, 6},
190                 {CPM_CLK_SCC2, CPM_CLK4, 7},
191                 {CPM_CLK_SCC3, CPM_BRG1, 0},
192                 {CPM_CLK_SCC3, CPM_BRG2, 1},
193                 {CPM_CLK_SCC3, CPM_BRG3, 2},
194                 {CPM_CLK_SCC3, CPM_BRG4, 3},
195                 {CPM_CLK_SCC3, CPM_CLK5, 4},
196                 {CPM_CLK_SCC3, CPM_CLK6, 5},
197                 {CPM_CLK_SCC3, CPM_CLK7, 6},
198                 {CPM_CLK_SCC3, CPM_CLK8, 7},
199                 {CPM_CLK_SCC4, CPM_BRG1, 0},
200                 {CPM_CLK_SCC4, CPM_BRG2, 1},
201                 {CPM_CLK_SCC4, CPM_BRG3, 2},
202                 {CPM_CLK_SCC4, CPM_BRG4, 3},
203                 {CPM_CLK_SCC4, CPM_CLK5, 4},
204                 {CPM_CLK_SCC4, CPM_CLK6, 5},
205                 {CPM_CLK_SCC4, CPM_CLK7, 6},
206                 {CPM_CLK_SCC4, CPM_CLK8, 7},
207         };
208
209         im_cpmux = cpm2_map(im_cpmux);
210
211         switch (target) {
212         case CPM_CLK_SCC1:
213                 reg = &im_cpmux->cmx_scr;
214                 shift = 24;
215                 break;
216         case CPM_CLK_SCC2:
217                 reg = &im_cpmux->cmx_scr;
218                 shift = 16;
219                 break;
220         case CPM_CLK_SCC3:
221                 reg = &im_cpmux->cmx_scr;
222                 shift = 8;
223                 break;
224         case CPM_CLK_SCC4:
225                 reg = &im_cpmux->cmx_scr;
226                 shift = 0;
227                 break;
228         case CPM_CLK_FCC1:
229                 reg = &im_cpmux->cmx_fcr;
230                 shift = 24;
231                 break;
232         case CPM_CLK_FCC2:
233                 reg = &im_cpmux->cmx_fcr;
234                 shift = 16;
235                 break;
236         case CPM_CLK_FCC3:
237                 reg = &im_cpmux->cmx_fcr;
238                 shift = 8;
239                 break;
240         default:
241                 printk(KERN_ERR "cpm2_clock_setup: invalid clock target\n");
242                 return -EINVAL;
243         }
244
245         if (mode == CPM_CLK_RX)
246                 shift += 3;
247
248         for (i = 0; i < ARRAY_SIZE(clk_map); i++) {
249                 if (clk_map[i][0] == target && clk_map[i][1] == clock) {
250                         bits = clk_map[i][2];
251                         break;
252                 }
253         }
254         if (i == ARRAY_SIZE(clk_map))
255             ret = -EINVAL;
256
257         bits <<= shift;
258         mask <<= shift;
259
260         out_be32(reg, (in_be32(reg) & ~mask) | bits);
261
262         cpm2_unmap(im_cpmux);
263         return ret;
264 }
265
266 int cpm2_smc_clk_setup(enum cpm_clk_target target, int clock)
267 {
268         int ret = 0;
269         int shift;
270         int i, bits = 0;
271         cpmux_t __iomem *im_cpmux;
272         u8 __iomem *reg;
273         u8 mask = 3;
274
275         u8 clk_map[][3] = {
276                 {CPM_CLK_SMC1, CPM_BRG1, 0},
277                 {CPM_CLK_SMC1, CPM_BRG7, 1},
278                 {CPM_CLK_SMC1, CPM_CLK7, 2},
279                 {CPM_CLK_SMC1, CPM_CLK9, 3},
280                 {CPM_CLK_SMC2, CPM_BRG2, 0},
281                 {CPM_CLK_SMC2, CPM_BRG8, 1},
282                 {CPM_CLK_SMC2, CPM_CLK4, 2},
283                 {CPM_CLK_SMC2, CPM_CLK15, 3},
284         };
285
286         im_cpmux = cpm2_map(im_cpmux);
287
288         switch (target) {
289         case CPM_CLK_SMC1:
290                 reg = &im_cpmux->cmx_smr;
291                 mask = 3;
292                 shift = 4;
293                 break;
294         case CPM_CLK_SMC2:
295                 reg = &im_cpmux->cmx_smr;
296                 mask = 3;
297                 shift = 0;
298                 break;
299         default:
300                 printk(KERN_ERR "cpm2_smc_clock_setup: invalid clock target\n");
301                 return -EINVAL;
302         }
303
304         for (i = 0; i < ARRAY_SIZE(clk_map); i++) {
305                 if (clk_map[i][0] == target && clk_map[i][1] == clock) {
306                         bits = clk_map[i][2];
307                         break;
308                 }
309         }
310         if (i == ARRAY_SIZE(clk_map))
311             ret = -EINVAL;
312
313         bits <<= shift;
314         mask <<= shift;
315
316         out_8(reg, (in_8(reg) & ~mask) | bits);
317
318         cpm2_unmap(im_cpmux);
319         return ret;
320 }
321
322 struct cpm2_ioports {
323         u32 dir, par, sor, odr, dat;
324         u32 res[3];
325 };
326
327 void cpm2_set_pin(int port, int pin, int flags)
328 {
329         struct cpm2_ioports __iomem *iop =
330                 (struct cpm2_ioports __iomem *)&cpm2_immr->im_ioport;
331
332         pin = 1 << (31 - pin);
333
334         if (flags & CPM_PIN_OUTPUT)
335                 setbits32(&iop[port].dir, pin);
336         else
337                 clrbits32(&iop[port].dir, pin);
338
339         if (!(flags & CPM_PIN_GPIO))
340                 setbits32(&iop[port].par, pin);
341         else
342                 clrbits32(&iop[port].par, pin);
343
344         if (flags & CPM_PIN_SECONDARY)
345                 setbits32(&iop[port].sor, pin);
346         else
347                 clrbits32(&iop[port].sor, pin);
348
349         if (flags & CPM_PIN_OPENDRAIN)
350                 setbits32(&iop[port].odr, pin);
351         else
352                 clrbits32(&iop[port].odr, pin);
353 }
354
355 static int cpm_init_par_io(void)
356 {
357         struct device_node *np;
358
359         for_each_compatible_node(np, NULL, "fsl,cpm2-pario-bank")
360                 cpm2_gpiochip_add32(np);
361         return 0;
362 }
363 arch_initcall(cpm_init_par_io);
364