Merge git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc
[linux-2.6.git] / arch / powerpc / kernel / head_booke.h
1 #ifndef __HEAD_BOOKE_H__
2 #define __HEAD_BOOKE_H__
3
4 /*
5  * Macros used for common Book-e exception handling
6  */
7
8 #define SET_IVOR(vector_number, vector_label)           \
9                 li      r26,vector_label@l;             \
10                 mtspr   SPRN_IVOR##vector_number,r26;   \
11                 sync
12
13 #define NORMAL_EXCEPTION_PROLOG                                              \
14         mtspr   SPRN_SPRG0,r10;         /* save two registers to work with */\
15         mtspr   SPRN_SPRG1,r11;                                              \
16         mtspr   SPRN_SPRG4W,r1;                                              \
17         mfcr    r10;                    /* save CR in r10 for now          */\
18         mfspr   r11,SPRN_SRR1;          /* check whether user or kernel    */\
19         andi.   r11,r11,MSR_PR;                                              \
20         beq     1f;                                                          \
21         mfspr   r1,SPRN_SPRG3;          /* if from user, start at top of   */\
22         lwz     r1,THREAD_INFO-THREAD(r1); /* this thread's kernel stack   */\
23         addi    r1,r1,THREAD_SIZE;                                           \
24 1:      subi    r1,r1,INT_FRAME_SIZE;   /* Allocate an exception frame     */\
25         mr      r11,r1;                                                      \
26         stw     r10,_CCR(r11);          /* save various registers          */\
27         stw     r12,GPR12(r11);                                              \
28         stw     r9,GPR9(r11);                                                \
29         mfspr   r10,SPRN_SPRG0;                                              \
30         stw     r10,GPR10(r11);                                              \
31         mfspr   r12,SPRN_SPRG1;                                              \
32         stw     r12,GPR11(r11);                                              \
33         mflr    r10;                                                         \
34         stw     r10,_LINK(r11);                                              \
35         mfspr   r10,SPRN_SPRG4R;                                             \
36         mfspr   r12,SPRN_SRR0;                                               \
37         stw     r10,GPR1(r11);                                               \
38         mfspr   r9,SPRN_SRR1;                                                \
39         stw     r10,0(r11);                                                  \
40         rlwinm  r9,r9,0,14,12;          /* clear MSR_WE (necessary?)       */\
41         stw     r0,GPR0(r11);                                                \
42         SAVE_4GPRS(3, r11);                                                  \
43         SAVE_2GPRS(7, r11)
44
45 /* To handle the additional exception priority levels on 40x and Book-E
46  * processors we allocate a 4k stack per additional priority level. The various
47  * head_xxx.S files allocate space (exception_stack_top) for each priority's
48  * stack times the number of CPUs
49  *
50  * On 40x critical is the only additional level
51  * On 44x/e500 we have critical and machine check
52  * On e200 we have critical and debug (machine check occurs via critical)
53  *
54  * Additionally we reserve a SPRG for each priority level so we can free up a
55  * GPR to use as the base for indirect access to the exception stacks.  This
56  * is necessary since the MMU is always on, for Book-E parts, and the stacks
57  * are offset from KERNELBASE.
58  *
59  */
60 #define BOOKE_EXCEPTION_STACK_SIZE      (8192)
61
62 /* CRIT_SPRG only used in critical exception handling */
63 #define CRIT_SPRG       SPRN_SPRG2
64 /* MCHECK_SPRG only used in machine check exception handling */
65 #define MCHECK_SPRG     SPRN_SPRG6W
66
67 #define MCHECK_STACK_TOP        (exception_stack_top - 4096)
68 #define CRIT_STACK_TOP          (exception_stack_top)
69
70 /* only on e200 for now */
71 #define DEBUG_STACK_TOP         (exception_stack_top - 4096)
72 #define DEBUG_SPRG              SPRN_SPRG6W
73
74 #ifdef CONFIG_SMP
75 #define BOOKE_LOAD_EXC_LEVEL_STACK(level)               \
76         mfspr   r8,SPRN_PIR;                            \
77         mulli   r8,r8,BOOKE_EXCEPTION_STACK_SIZE;       \
78         neg     r8,r8;                                  \
79         addis   r8,r8,level##_STACK_TOP@ha;             \
80         addi    r8,r8,level##_STACK_TOP@l
81 #else
82 #define BOOKE_LOAD_EXC_LEVEL_STACK(level)               \
83         lis     r8,level##_STACK_TOP@h;                 \
84         ori     r8,r8,level##_STACK_TOP@l
85 #endif
86
87 /*
88  * Exception prolog for critical/machine check exceptions.  This is a
89  * little different from the normal exception prolog above since a
90  * critical/machine check exception can potentially occur at any point
91  * during normal exception processing. Thus we cannot use the same SPRG
92  * registers as the normal prolog above. Instead we use a portion of the
93  * critical/machine check exception stack at low physical addresses.
94  */
95 #define EXC_LEVEL_EXCEPTION_PROLOG(exc_level, exc_level_srr0, exc_level_srr1) \
96         mtspr   exc_level##_SPRG,r8;                                         \
97         BOOKE_LOAD_EXC_LEVEL_STACK(exc_level);/* r8 points to the exc_level stack*/ \
98         stw     r10,GPR10-INT_FRAME_SIZE(r8);                                \
99         stw     r11,GPR11-INT_FRAME_SIZE(r8);                                \
100         mfcr    r10;                    /* save CR in r10 for now          */\
101         mfspr   r11,exc_level_srr1;     /* check whether user or kernel    */\
102         andi.   r11,r11,MSR_PR;                                              \
103         mr      r11,r8;                                                      \
104         mfspr   r8,exc_level##_SPRG;                                         \
105         beq     1f;                                                          \
106         /* COMING FROM USER MODE */                                          \
107         mfspr   r11,SPRN_SPRG3;         /* if from user, start at top of   */\
108         lwz     r11,THREAD_INFO-THREAD(r11); /* this thread's kernel stack */\
109         addi    r11,r11,THREAD_SIZE;                                         \
110 1:      subi    r11,r11,INT_FRAME_SIZE; /* Allocate an exception frame     */\
111         stw     r10,_CCR(r11);          /* save various registers          */\
112         stw     r12,GPR12(r11);                                              \
113         stw     r9,GPR9(r11);                                                \
114         mflr    r10;                                                         \
115         stw     r10,_LINK(r11);                                              \
116         mfspr   r12,SPRN_DEAR;          /* save DEAR and ESR in the frame  */\
117         stw     r12,_DEAR(r11);         /* since they may have had stuff   */\
118         mfspr   r9,SPRN_ESR;            /* in them at the point where the  */\
119         stw     r9,_ESR(r11);           /* exception was taken             */\
120         mfspr   r12,exc_level_srr0;                                          \
121         stw     r1,GPR1(r11);                                                \
122         mfspr   r9,exc_level_srr1;                                           \
123         stw     r1,0(r11);                                                   \
124         mr      r1,r11;                                                      \
125         rlwinm  r9,r9,0,14,12;          /* clear MSR_WE (necessary?)       */\
126         stw     r0,GPR0(r11);                                                \
127         SAVE_4GPRS(3, r11);                                                  \
128         SAVE_2GPRS(7, r11)
129
130 #define CRITICAL_EXCEPTION_PROLOG \
131                 EXC_LEVEL_EXCEPTION_PROLOG(CRIT, SPRN_CSRR0, SPRN_CSRR1)
132 #define DEBUG_EXCEPTION_PROLOG \
133                 EXC_LEVEL_EXCEPTION_PROLOG(DEBUG, SPRN_DSRR0, SPRN_DSRR1)
134 #define MCHECK_EXCEPTION_PROLOG \
135                 EXC_LEVEL_EXCEPTION_PROLOG(MCHECK, SPRN_MCSRR0, SPRN_MCSRR1)
136
137 /*
138  * Exception vectors.
139  */
140 #define START_EXCEPTION(label)                                               \
141         .align 5;                                                            \
142 label:
143
144 #define FINISH_EXCEPTION(func)                                  \
145         bl      transfer_to_handler_full;                       \
146         .long   func;                                           \
147         .long   ret_from_except_full
148
149 #define EXCEPTION(n, label, hdlr, xfer)                         \
150         START_EXCEPTION(label);                                 \
151         NORMAL_EXCEPTION_PROLOG;                                \
152         addi    r3,r1,STACK_FRAME_OVERHEAD;                     \
153         xfer(n, hdlr)
154
155 #define CRITICAL_EXCEPTION(n, label, hdlr)                      \
156         START_EXCEPTION(label);                                 \
157         CRITICAL_EXCEPTION_PROLOG;                              \
158         addi    r3,r1,STACK_FRAME_OVERHEAD;                     \
159         EXC_XFER_TEMPLATE(hdlr, n+2, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \
160                           NOCOPY, crit_transfer_to_handler, \
161                           ret_from_crit_exc)
162
163 #define MCHECK_EXCEPTION(n, label, hdlr)                        \
164         START_EXCEPTION(label);                                 \
165         MCHECK_EXCEPTION_PROLOG;                                \
166         mfspr   r5,SPRN_ESR;                                    \
167         stw     r5,_ESR(r11);                                   \
168         addi    r3,r1,STACK_FRAME_OVERHEAD;                     \
169         EXC_XFER_TEMPLATE(hdlr, n+2, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \
170                           NOCOPY, mcheck_transfer_to_handler,   \
171                           ret_from_mcheck_exc)
172
173 #define EXC_XFER_TEMPLATE(hdlr, trap, msr, copyee, tfer, ret)   \
174         li      r10,trap;                                       \
175         stw     r10,_TRAP(r11);                                 \
176         lis     r10,msr@h;                                      \
177         ori     r10,r10,msr@l;                                  \
178         copyee(r10, r9);                                        \
179         bl      tfer;                                           \
180         .long   hdlr;                                           \
181         .long   ret
182
183 #define COPY_EE(d, s)           rlwimi d,s,0,16,16
184 #define NOCOPY(d, s)
185
186 #define EXC_XFER_STD(n, hdlr)           \
187         EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, NOCOPY, transfer_to_handler_full, \
188                           ret_from_except_full)
189
190 #define EXC_XFER_LITE(n, hdlr)          \
191         EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, NOCOPY, transfer_to_handler, \
192                           ret_from_except)
193
194 #define EXC_XFER_EE(n, hdlr)            \
195         EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, COPY_EE, transfer_to_handler_full, \
196                           ret_from_except_full)
197
198 #define EXC_XFER_EE_LITE(n, hdlr)       \
199         EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, COPY_EE, transfer_to_handler, \
200                           ret_from_except)
201
202 /* Check for a single step debug exception while in an exception
203  * handler before state has been saved.  This is to catch the case
204  * where an instruction that we are trying to single step causes
205  * an exception (eg ITLB/DTLB miss) and thus the first instruction of
206  * the exception handler generates a single step debug exception.
207  *
208  * If we get a debug trap on the first instruction of an exception handler,
209  * we reset the MSR_DE in the _exception handler's_ MSR (the debug trap is
210  * a critical exception, so we are using SPRN_CSRR1 to manipulate the MSR).
211  * The exception handler was handling a non-critical interrupt, so it will
212  * save (and later restore) the MSR via SPRN_CSRR1, which will still have
213  * the MSR_DE bit set.
214  */
215 #ifdef CONFIG_E200
216 #define DEBUG_EXCEPTION                                                       \
217         START_EXCEPTION(Debug);                                               \
218         DEBUG_EXCEPTION_PROLOG;                                               \
219                                                                               \
220         /*                                                                    \
221          * If there is a single step or branch-taken exception in an          \
222          * exception entry sequence, it was probably meant to apply to        \
223          * the code where the exception occurred (since exception entry       \
224          * doesn't turn off DE automatically).  We simulate the effect        \
225          * of turning off DE on entry to an exception handler by turning      \
226          * off DE in the CSRR1 value and clearing the debug status.           \
227          */                                                                   \
228         mfspr   r10,SPRN_DBSR;          /* check single-step/branch taken */  \
229         andis.  r10,r10,DBSR_IC@h;                                            \
230         beq+    2f;                                                           \
231                                                                               \
232         lis     r10,KERNELBASE@h;       /* check if exception in vectors */   \
233         ori     r10,r10,KERNELBASE@l;                                         \
234         cmplw   r12,r10;                                                      \
235         blt+    2f;                     /* addr below exception vectors */    \
236                                                                               \
237         lis     r10,Debug@h;                                                  \
238         ori     r10,r10,Debug@l;                                              \
239         cmplw   r12,r10;                                                      \
240         bgt+    2f;                     /* addr above exception vectors */    \
241                                                                               \
242         /* here it looks like we got an inappropriate debug exception. */     \
243 1:      rlwinm  r9,r9,0,~MSR_DE;        /* clear DE in the CDRR1 value */     \
244         lis     r10,DBSR_IC@h;          /* clear the IC event */              \
245         mtspr   SPRN_DBSR,r10;                                                \
246         /* restore state and get out */                                       \
247         lwz     r10,_CCR(r11);                                                \
248         lwz     r0,GPR0(r11);                                                 \
249         lwz     r1,GPR1(r11);                                                 \
250         mtcrf   0x80,r10;                                                     \
251         mtspr   SPRN_DSRR0,r12;                                               \
252         mtspr   SPRN_DSRR1,r9;                                                \
253         lwz     r9,GPR9(r11);                                                 \
254         lwz     r12,GPR12(r11);                                               \
255         mtspr   DEBUG_SPRG,r8;                                                \
256         BOOKE_LOAD_EXC_LEVEL_STACK(DEBUG); /* r8 points to the debug stack */ \
257         lwz     r10,GPR10-INT_FRAME_SIZE(r8);                                 \
258         lwz     r11,GPR11-INT_FRAME_SIZE(r8);                                 \
259         mfspr   r8,DEBUG_SPRG;                                                \
260                                                                               \
261         RFDI;                                                                 \
262         b       .;                                                            \
263                                                                               \
264         /* continue normal handling for a critical exception... */            \
265 2:      mfspr   r4,SPRN_DBSR;                                                 \
266         addi    r3,r1,STACK_FRAME_OVERHEAD;                                   \
267         EXC_XFER_TEMPLATE(DebugException, 0x2002, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), NOCOPY, debug_transfer_to_handler, ret_from_debug_exc)
268 #else
269 #define DEBUG_EXCEPTION                                                       \
270         START_EXCEPTION(Debug);                                               \
271         CRITICAL_EXCEPTION_PROLOG;                                            \
272                                                                               \
273         /*                                                                    \
274          * If there is a single step or branch-taken exception in an          \
275          * exception entry sequence, it was probably meant to apply to        \
276          * the code where the exception occurred (since exception entry       \
277          * doesn't turn off DE automatically).  We simulate the effect        \
278          * of turning off DE on entry to an exception handler by turning      \
279          * off DE in the CSRR1 value and clearing the debug status.           \
280          */                                                                   \
281         mfspr   r10,SPRN_DBSR;          /* check single-step/branch taken */  \
282         andis.  r10,r10,DBSR_IC@h;                                            \
283         beq+    2f;                                                           \
284                                                                               \
285         lis     r10,KERNELBASE@h;       /* check if exception in vectors */   \
286         ori     r10,r10,KERNELBASE@l;                                         \
287         cmplw   r12,r10;                                                      \
288         blt+    2f;                     /* addr below exception vectors */    \
289                                                                               \
290         lis     r10,Debug@h;                                                  \
291         ori     r10,r10,Debug@l;                                              \
292         cmplw   r12,r10;                                                      \
293         bgt+    2f;                     /* addr above exception vectors */    \
294                                                                               \
295         /* here it looks like we got an inappropriate debug exception. */     \
296 1:      rlwinm  r9,r9,0,~MSR_DE;        /* clear DE in the CSRR1 value */     \
297         lis     r10,DBSR_IC@h;          /* clear the IC event */              \
298         mtspr   SPRN_DBSR,r10;                                                \
299         /* restore state and get out */                                       \
300         lwz     r10,_CCR(r11);                                                \
301         lwz     r0,GPR0(r11);                                                 \
302         lwz     r1,GPR1(r11);                                                 \
303         mtcrf   0x80,r10;                                                     \
304         mtspr   SPRN_CSRR0,r12;                                               \
305         mtspr   SPRN_CSRR1,r9;                                                \
306         lwz     r9,GPR9(r11);                                                 \
307         lwz     r12,GPR12(r11);                                               \
308         mtspr   CRIT_SPRG,r8;                                                 \
309         BOOKE_LOAD_EXC_LEVEL_STACK(CRIT); /* r8 points to the debug stack */  \
310         lwz     r10,GPR10-INT_FRAME_SIZE(r8);                                 \
311         lwz     r11,GPR11-INT_FRAME_SIZE(r8);                                 \
312         mfspr   r8,CRIT_SPRG;                                                 \
313                                                                               \
314         rfci;                                                                 \
315         b       .;                                                            \
316                                                                               \
317         /* continue normal handling for a critical exception... */            \
318 2:      mfspr   r4,SPRN_DBSR;                                                 \
319         addi    r3,r1,STACK_FRAME_OVERHEAD;                                   \
320         EXC_XFER_TEMPLATE(DebugException, 0x2002, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), NOCOPY, crit_transfer_to_handler, ret_from_crit_exc)
321 #endif
322
323 #define INSTRUCTION_STORAGE_EXCEPTION                                         \
324         START_EXCEPTION(InstructionStorage)                                   \
325         NORMAL_EXCEPTION_PROLOG;                                              \
326         mfspr   r5,SPRN_ESR;            /* Grab the ESR and save it */        \
327         stw     r5,_ESR(r11);                                                 \
328         mr      r4,r12;                 /* Pass SRR0 as arg2 */               \
329         li      r5,0;                   /* Pass zero as arg3 */               \
330         EXC_XFER_EE_LITE(0x0400, handle_page_fault)
331
332 #define ALIGNMENT_EXCEPTION                                                   \
333         START_EXCEPTION(Alignment)                                            \
334         NORMAL_EXCEPTION_PROLOG;                                              \
335         mfspr   r4,SPRN_DEAR;           /* Grab the DEAR and save it */       \
336         stw     r4,_DEAR(r11);                                                \
337         addi    r3,r1,STACK_FRAME_OVERHEAD;                                   \
338         EXC_XFER_EE(0x0600, alignment_exception)
339
340 #define PROGRAM_EXCEPTION                                                     \
341         START_EXCEPTION(Program)                                              \
342         NORMAL_EXCEPTION_PROLOG;                                              \
343         mfspr   r4,SPRN_ESR;            /* Grab the ESR and save it */        \
344         stw     r4,_ESR(r11);                                                 \
345         addi    r3,r1,STACK_FRAME_OVERHEAD;                                   \
346         EXC_XFER_STD(0x0700, program_check_exception)
347
348 #define DECREMENTER_EXCEPTION                                                 \
349         START_EXCEPTION(Decrementer)                                          \
350         NORMAL_EXCEPTION_PROLOG;                                              \
351         lis     r0,TSR_DIS@h;           /* Setup the DEC interrupt mask */    \
352         mtspr   SPRN_TSR,r0;            /* Clear the DEC interrupt */         \
353         addi    r3,r1,STACK_FRAME_OVERHEAD;                                   \
354         EXC_XFER_LITE(0x0900, timer_interrupt)
355
356 #define FP_UNAVAILABLE_EXCEPTION                                              \
357         START_EXCEPTION(FloatingPointUnavailable)                             \
358         NORMAL_EXCEPTION_PROLOG;                                              \
359         bne     load_up_fpu;            /* if from user, just load it up */   \
360         addi    r3,r1,STACK_FRAME_OVERHEAD;                                   \
361         EXC_XFER_EE_LITE(0x800, KernelFP)
362
363 #endif /* __HEAD_BOOKE_H__ */