d3b8262df686b830ba921297bb1ba46d87ad9590
[linux-2.6.git] / arch / powerpc / boot / dts / mpc836x_mds.dts
1 /*
2  * MPC8360E EMDS Device Tree Source
3  *
4  * Copyright 2006 Freescale Semiconductor Inc.
5  *
6  * This program is free software; you can redistribute  it and/or modify it
7  * under  the terms of  the GNU General  Public License as published by the
8  * Free Software Foundation;  either version 2 of the  License, or (at your
9  * option) any later version.
10  */
11
12
13 /*
14 /memreserve/    00000000 1000000;
15 */
16
17 / {
18         model = "MPC8360MDS";
19         compatible = "MPC8360EMDS", "MPC836xMDS", "MPC83xxMDS";
20         #address-cells = <1>;
21         #size-cells = <1>;
22
23         aliases {
24                 ethernet0 = &enet0;
25                 ethernet1 = &enet1;
26                 serial0 = &serial0;
27                 serial1 = &serial1;
28                 pci0 = &pci0;
29         };
30
31         cpus {
32                 #address-cells = <1>;
33                 #size-cells = <0>;
34
35                 PowerPC,8360@0 {
36                         device_type = "cpu";
37                         reg = <0>;
38                         d-cache-line-size = <20>;       // 32 bytes
39                         i-cache-line-size = <20>;       // 32 bytes
40                         d-cache-size = <8000>;          // L1, 32K
41                         i-cache-size = <8000>;          // L1, 32K
42                         timebase-frequency = <3EF1480>;
43                         bus-frequency = <FBC5200>;
44                         clock-frequency = <1F78A400>;
45                 };
46         };
47
48         memory {
49                 device_type = "memory";
50                 reg = <00000000 10000000>;
51         };
52
53         bcsr@f8000000 {
54                 device_type = "board-control";
55                 reg = <f8000000 8000>;
56         };
57
58         soc8360@e0000000 {
59                 #address-cells = <1>;
60                 #size-cells = <1>;
61                 device_type = "soc";
62                 ranges = <0 e0000000 00100000>;
63                 reg = <e0000000 00000200>;
64                 bus-frequency = <FBC5200>;
65
66                 wdt@200 {
67                         device_type = "watchdog";
68                         compatible = "mpc83xx_wdt";
69                         reg = <200 100>;
70                 };
71
72                 i2c@3000 {
73                         #address-cells = <1>;
74                         #size-cells = <0>;
75                         cell-index = <0>;
76                         compatible = "fsl-i2c";
77                         reg = <3000 100>;
78                         interrupts = <e 8>;
79                         interrupt-parent = < &ipic >;
80                         dfsrr;
81
82                         rtc@68 {
83                                 compatible = "dallas,ds1374";
84                                 reg = <68>;
85                         };
86                 };
87
88                 i2c@3100 {
89                         #address-cells = <1>;
90                         #size-cells = <0>;
91                         cell-index = <1>;
92                         compatible = "fsl-i2c";
93                         reg = <3100 100>;
94                         interrupts = <f 8>;
95                         interrupt-parent = < &ipic >;
96                         dfsrr;
97                 };
98
99                 serial0: serial@4500 {
100                         cell-index = <0>;
101                         device_type = "serial";
102                         compatible = "ns16550";
103                         reg = <4500 100>;
104                         clock-frequency = <FBC5200>;
105                         interrupts = <9 8>;
106                         interrupt-parent = < &ipic >;
107                 };
108
109                 serial1: serial@4600 {
110                         cell-index = <1>;
111                         device_type = "serial";
112                         compatible = "ns16550";
113                         reg = <4600 100>;
114                         clock-frequency = <FBC5200>;
115                         interrupts = <a 8>;
116                         interrupt-parent = < &ipic >;
117                 };
118
119                 crypto@30000 {
120                         device_type = "crypto";
121                         model = "SEC2";
122                         compatible = "talitos";
123                         reg = <30000 10000>;
124                         interrupts = <b 8>;
125                         interrupt-parent = < &ipic >;
126                         num-channels = <4>;
127                         channel-fifo-len = <18>;
128                         exec-units-mask = <0000007e>;
129                         /* desc mask is for rev1.x, we need runtime fixup for >=2.x */
130                         descriptor-types-mask = <01010ebf>;
131                 };
132
133                 ipic: pic@700 {
134                         interrupt-controller;
135                         #address-cells = <0>;
136                         #interrupt-cells = <2>;
137                         reg = <700 100>;
138                         device_type = "ipic";
139                 };
140
141                 par_io@1400 {
142                         reg = <1400 100>;
143                         device_type = "par_io";
144                         num-ports = <7>;
145
146                         pio1: ucc_pin@01 {
147                                 pio-map = <
148                         /* port  pin  dir  open_drain  assignment  has_irq */
149                                         0  3  1  0  1  0        /* TxD0 */
150                                         0  4  1  0  1  0        /* TxD1 */
151                                         0  5  1  0  1  0        /* TxD2 */
152                                         0  6  1  0  1  0        /* TxD3 */
153                                         1  6  1  0  3  0        /* TxD4 */
154                                         1  7  1  0  1  0        /* TxD5 */
155                                         1  9  1  0  2  0        /* TxD6 */
156                                         1  a  1  0  2  0        /* TxD7 */
157                                         0  9  2  0  1  0        /* RxD0 */
158                                         0  a  2  0  1  0        /* RxD1 */
159                                         0  b  2  0  1  0        /* RxD2 */
160                                         0  c  2  0  1  0        /* RxD3 */
161                                         0  d  2  0  1  0        /* RxD4 */
162                                         1  1  2  0  2  0        /* RxD5 */
163                                         1  0  2  0  2  0        /* RxD6 */
164                                         1  4  2  0  2  0        /* RxD7 */
165                                         0  7  1  0  1  0        /* TX_EN */
166                                         0  8  1  0  1  0        /* TX_ER */
167                                         0  f  2  0  1  0        /* RX_DV */
168                                         0  10 2  0  1  0        /* RX_ER */
169                                         0  0  2  0  1  0        /* RX_CLK */
170                                         2  9  1  0  3  0        /* GTX_CLK - CLK10 */
171                                         2  8  2  0  1  0>;      /* GTX125 - CLK9 */
172                         };
173                         pio2: ucc_pin@02 {
174                                 pio-map = <
175                         /* port  pin  dir  open_drain  assignment  has_irq */
176                                         0  11 1  0  1  0   /* TxD0 */
177                                         0  12 1  0  1  0   /* TxD1 */
178                                         0  13 1  0  1  0   /* TxD2 */
179                                         0  14 1  0  1  0   /* TxD3 */
180                                         1  2  1  0  1  0   /* TxD4 */
181                                         1  3  1  0  2  0   /* TxD5 */
182                                         1  5  1  0  3  0   /* TxD6 */
183                                         1  8  1  0  3  0   /* TxD7 */
184                                         0  17 2  0  1  0   /* RxD0 */
185                                         0  18 2  0  1  0   /* RxD1 */
186                                         0  19 2  0  1  0   /* RxD2 */
187                                         0  1a 2  0  1  0   /* RxD3 */
188                                         0  1b 2  0  1  0   /* RxD4 */
189                                         1  c  2  0  2  0   /* RxD5 */
190                                         1  d  2  0  3  0   /* RxD6 */
191                                         1  b  2  0  2  0   /* RxD7 */
192                                         0  15 1  0  1  0   /* TX_EN */
193                                         0  16 1  0  1  0   /* TX_ER */
194                                         0  1d 2  0  1  0   /* RX_DV */
195                                         0  1e 2  0  1  0   /* RX_ER */
196                                         0  1f 2  0  1  0   /* RX_CLK */
197                                         2  2  1  0  2  0   /* GTX_CLK - CLK10 */
198                                         2  3  2  0  1  0   /* GTX125 - CLK4 */
199                                         0  1  3  0  2  0   /* MDIO */
200                                         0  2  1  0  1  0>; /* MDC */
201                         };
202
203                 };
204         };
205
206         qe@e0100000 {
207                 #address-cells = <1>;
208                 #size-cells = <1>;
209                 device_type = "qe";
210                 compatible = "fsl,qe";
211                 ranges = <0 e0100000 00100000>;
212                 reg = <e0100000 480>;
213                 brg-frequency = <0>;
214                 bus-frequency = <179A7B00>;
215
216                 muram@10000 {
217                         compatible = "fsl,qe-muram", "fsl,cpm-muram";
218                         ranges = <0 00010000 0000c000>;
219
220                         data-only@0{
221                                 compatible = "fsl,qe-muram-data",
222                                              "fsl,cpm-muram-data";
223                                 reg = <0 c000>;
224                         };
225                 };
226
227                 spi@4c0 {
228                         cell-index = <0>;
229                         compatible = "fsl,spi";
230                         reg = <4c0 40>;
231                         interrupts = <2>;
232                         interrupt-parent = < &qeic >;
233                         mode = "cpu";
234                 };
235
236                 spi@500 {
237                         cell-index = <1>;
238                         compatible = "fsl,spi";
239                         reg = <500 40>;
240                         interrupts = <1>;
241                         interrupt-parent = < &qeic >;
242                         mode = "cpu";
243                 };
244
245                 usb@6c0 {
246                         compatible = "qe_udc";
247                         reg = <6c0 40 8B00 100>;
248                         interrupts = <b>;
249                         interrupt-parent = < &qeic >;
250                         mode = "slave";
251                 };
252
253                 enet0: ucc@2000 {
254                         device_type = "network";
255                         compatible = "ucc_geth";
256                         model = "UCC";
257                         cell-index = <1>;
258                         device-id = <1>;
259                         reg = <2000 200>;
260                         interrupts = <20>;
261                         interrupt-parent = < &qeic >;
262                         local-mac-address = [ 00 00 00 00 00 00 ];
263                         rx-clock-name = "none";
264                         tx-clock-name = "clk9";
265                         phy-handle = < &phy0 >;
266                         phy-connection-type = "rgmii-id";
267                         pio-handle = < &pio1 >;
268                 };
269
270                 enet1: ucc@3000 {
271                         device_type = "network";
272                         compatible = "ucc_geth";
273                         model = "UCC";
274                         cell-index = <2>;
275                         device-id = <2>;
276                         reg = <3000 200>;
277                         interrupts = <21>;
278                         interrupt-parent = < &qeic >;
279                         local-mac-address = [ 00 00 00 00 00 00 ];
280                         rx-clock-name = "none";
281                         tx-clock-name = "clk4";
282                         phy-handle = < &phy1 >;
283                         phy-connection-type = "rgmii-id";
284                         pio-handle = < &pio2 >;
285                 };
286
287                 mdio@2120 {
288                         #address-cells = <1>;
289                         #size-cells = <0>;
290                         reg = <2120 18>;
291                         compatible = "fsl,ucc-mdio";
292
293                         phy0: ethernet-phy@00 {
294                                 interrupt-parent = < &ipic >;
295                                 interrupts = <11 8>;
296                                 reg = <0>;
297                                 device_type = "ethernet-phy";
298                         };
299                         phy1: ethernet-phy@01 {
300                                 interrupt-parent = < &ipic >;
301                                 interrupts = <12 8>;
302                                 reg = <1>;
303                                 device_type = "ethernet-phy";
304                         };
305                 };
306
307                 qeic: interrupt-controller@80 {
308                         interrupt-controller;
309                         compatible = "fsl,qe-ic";
310                         #address-cells = <0>;
311                         #interrupt-cells = <1>;
312                         reg = <80 80>;
313                         big-endian;
314                         interrupts = <20 8 21 8>; //high:32 low:33
315                         interrupt-parent = < &ipic >;
316                 };
317         };
318
319         pci0: pci@e0008500 {
320                 cell-index = <1>;
321                 interrupt-map-mask = <f800 0 0 7>;
322                 interrupt-map = <
323
324                                 /* IDSEL 0x11 AD17 */
325                                  8800 0 0 1 &ipic 14 8
326                                  8800 0 0 2 &ipic 15 8
327                                  8800 0 0 3 &ipic 16 8
328                                  8800 0 0 4 &ipic 17 8
329
330                                 /* IDSEL 0x12 AD18 */
331                                  9000 0 0 1 &ipic 16 8
332                                  9000 0 0 2 &ipic 17 8
333                                  9000 0 0 3 &ipic 14 8
334                                  9000 0 0 4 &ipic 15 8
335
336                                 /* IDSEL 0x13 AD19 */
337                                  9800 0 0 1 &ipic 17 8
338                                  9800 0 0 2 &ipic 14 8
339                                  9800 0 0 3 &ipic 15 8
340                                  9800 0 0 4 &ipic 16 8
341
342                                 /* IDSEL 0x15 AD21*/
343                                  a800 0 0 1 &ipic 14 8
344                                  a800 0 0 2 &ipic 15 8
345                                  a800 0 0 3 &ipic 16 8
346                                  a800 0 0 4 &ipic 17 8
347
348                                 /* IDSEL 0x16 AD22*/
349                                  b000 0 0 1 &ipic 17 8
350                                  b000 0 0 2 &ipic 14 8
351                                  b000 0 0 3 &ipic 15 8
352                                  b000 0 0 4 &ipic 16 8
353
354                                 /* IDSEL 0x17 AD23*/
355                                  b800 0 0 1 &ipic 16 8
356                                  b800 0 0 2 &ipic 17 8
357                                  b800 0 0 3 &ipic 14 8
358                                  b800 0 0 4 &ipic 15 8
359
360                                 /* IDSEL 0x18 AD24*/
361                                  c000 0 0 1 &ipic 15 8
362                                  c000 0 0 2 &ipic 16 8
363                                  c000 0 0 3 &ipic 17 8
364                                  c000 0 0 4 &ipic 14 8>;
365                 interrupt-parent = < &ipic >;
366                 interrupts = <42 8>;
367                 bus-range = <0 0>;
368                 ranges = <02000000 0 a0000000 a0000000 0 10000000
369                           42000000 0 80000000 80000000 0 10000000
370                           01000000 0 00000000 e2000000 0 00100000>;
371                 clock-frequency = <3f940aa>;
372                 #interrupt-cells = <1>;
373                 #size-cells = <2>;
374                 #address-cells = <3>;
375                 reg = <e0008500 100>;
376                 compatible = "fsl,mpc8349-pci";
377                 device_type = "pci";
378         };
379 };