[POWERPC] QE: Explicitly set address-cells and size cells for muram
[linux-2.6.git] / arch / powerpc / boot / dts / mpc832x_mds.dts
1 /*
2  * MPC8323E EMDS Device Tree Source
3  *
4  * Copyright 2006 Freescale Semiconductor Inc.
5  *
6  * This program is free software; you can redistribute  it and/or modify it
7  * under  the terms of  the GNU General  Public License as published by the
8  * Free Software Foundation;  either version 2 of the  License, or (at your
9  * option) any later version.
10
11  * To enable external serial I/O on a Freescale MPC 8323 SYS/MDS board, do
12  * this:
13  *
14  * 1) On chip U61, lift (disconnect) pins 21 (TXD) and 22 (RXD) from the board.
15  * 2) Solder a wire from U61-21 to P19A-23.  P19 is a grid of pins on the board
16  *    next to the serial ports.
17  * 3) Solder a wire from U61-22 to P19K-22.
18  *
19  * Note that there's a typo in the schematic.  The board labels the last column
20  * of pins "P19K", but in the schematic, that column is called "P19J".  So if
21  * you're going by the schematic, the pin is called "P19J-K22".
22  */
23
24 / {
25         model = "MPC8323EMDS";
26         compatible = "MPC8323EMDS", "MPC832xMDS", "MPC83xxMDS";
27         #address-cells = <1>;
28         #size-cells = <1>;
29
30         aliases {
31                 ethernet0 = &enet0;
32                 ethernet1 = &enet1;
33                 serial0 = &serial0;
34                 serial1 = &serial1;
35                 pci0 = &pci0;
36         };
37
38         cpus {
39                 #address-cells = <1>;
40                 #size-cells = <0>;
41
42                 PowerPC,8323@0 {
43                         device_type = "cpu";
44                         reg = <0>;
45                         d-cache-line-size = <20>;       // 32 bytes
46                         i-cache-line-size = <20>;       // 32 bytes
47                         d-cache-size = <4000>;          // L1, 16K
48                         i-cache-size = <4000>;          // L1, 16K
49                         timebase-frequency = <0>;
50                         bus-frequency = <0>;
51                         clock-frequency = <0>;
52                 };
53         };
54
55         memory {
56                 device_type = "memory";
57                 reg = <00000000 08000000>;
58         };
59
60         bcsr@f8000000 {
61                 device_type = "board-control";
62                 reg = <f8000000 8000>;
63         };
64
65         soc8323@e0000000 {
66                 #address-cells = <1>;
67                 #size-cells = <1>;
68                 device_type = "soc";
69                 ranges = <0 e0000000 00100000>;
70                 reg = <e0000000 00000200>;
71                 bus-frequency = <7DE2900>;
72
73                 wdt@200 {
74                         device_type = "watchdog";
75                         compatible = "mpc83xx_wdt";
76                         reg = <200 100>;
77                 };
78
79                 i2c@3000 {
80                         #address-cells = <1>;
81                         #size-cells = <0>;
82                         cell-index = <0>;
83                         compatible = "fsl-i2c";
84                         reg = <3000 100>;
85                         interrupts = <e 8>;
86                         interrupt-parent = < &ipic >;
87                         dfsrr;
88
89                         rtc@68 {
90                                 compatible = "dallas,ds1374";
91                                 reg = <68>;
92                         };
93                 };
94
95                 serial0: serial@4500 {
96                         cell-index = <0>;
97                         device_type = "serial";
98                         compatible = "ns16550";
99                         reg = <4500 100>;
100                         clock-frequency = <0>;
101                         interrupts = <9 8>;
102                         interrupt-parent = < &ipic >;
103                 };
104
105                 serial1: serial@4600 {
106                         cell-index = <1>;
107                         device_type = "serial";
108                         compatible = "ns16550";
109                         reg = <4600 100>;
110                         clock-frequency = <0>;
111                         interrupts = <a 8>;
112                         interrupt-parent = < &ipic >;
113                 };
114
115                 crypto@30000 {
116                         device_type = "crypto";
117                         model = "SEC2";
118                         compatible = "talitos";
119                         reg = <30000 7000>;
120                         interrupts = <b 8>;
121                         interrupt-parent = < &ipic >;
122                         /* Rev. 2.2 */
123                         num-channels = <1>;
124                         channel-fifo-len = <18>;
125                         exec-units-mask = <0000004c>;
126                         descriptor-types-mask = <0122003f>;
127                 };
128
129                 ipic: pic@700 {
130                         interrupt-controller;
131                         #address-cells = <0>;
132                         #interrupt-cells = <2>;
133                         reg = <700 100>;
134                         device_type = "ipic";
135                 };
136
137                 par_io@1400 {
138                         reg = <1400 100>;
139                         device_type = "par_io";
140                         num-ports = <7>;
141
142                         pio3: ucc_pin@03 {
143                                 pio-map = <
144                         /* port  pin  dir  open_drain  assignment  has_irq */
145                                         3  4  3  0  2  0  /* MDIO */
146                                         3  5  1  0  2  0  /* MDC */
147                                         0  d  2  0  1  0        /* RX_CLK (CLK9) */
148                                         3 18  2  0  1  0        /* TX_CLK (CLK10) */
149                                         1  0  1  0  1  0        /* TxD0 */
150                                         1  1  1  0  1  0        /* TxD1 */
151                                         1  2  1  0  1  0        /* TxD2 */
152                                         1  3  1  0  1  0        /* TxD3 */
153                                         1  4  2  0  1  0        /* RxD0 */
154                                         1  5  2  0  1  0        /* RxD1 */
155                                         1  6  2  0  1  0        /* RxD2 */
156                                         1  7  2  0  1  0        /* RxD3 */
157                                         1  8  2  0  1  0        /* RX_ER */
158                                         1  9  1  0  1  0        /* TX_ER */
159                                         1  a  2  0  1  0        /* RX_DV */
160                                         1  b  2  0  1  0        /* COL */
161                                         1  c  1  0  1  0        /* TX_EN */
162                                         1  d  2  0  1  0>;/* CRS */
163                         };
164                         pio4: ucc_pin@04 {
165                                 pio-map = <
166                         /* port  pin  dir  open_drain  assignment  has_irq */
167                                         3 1f  2  0  1  0        /* RX_CLK (CLK7) */
168                                         3  6  2  0  1  0        /* TX_CLK (CLK8) */
169                                         1 12  1  0  1  0        /* TxD0 */
170                                         1 13  1  0  1  0        /* TxD1 */
171                                         1 14  1  0  1  0        /* TxD2 */
172                                         1 15  1  0  1  0        /* TxD3 */
173                                         1 16  2  0  1  0        /* RxD0 */
174                                         1 17  2  0  1  0        /* RxD1 */
175                                         1 18  2  0  1  0        /* RxD2 */
176                                         1 19  2  0  1  0        /* RxD3 */
177                                         1 1a  2  0  1  0        /* RX_ER */
178                                         1 1b  1  0  1  0        /* TX_ER */
179                                         1 1c  2  0  1  0        /* RX_DV */
180                                         1 1d  2  0  1  0        /* COL */
181                                         1 1e  1  0  1  0        /* TX_EN */
182                                         1 1f  2  0  1  0>;/* CRS */
183                         };
184                         pio5: ucc_pin@05 {
185                                 pio-map = <
186                                 /*
187                                  *                    open       has
188                                  *   port  pin  dir  drain  sel  irq
189                                  */
190                                         2    0    1      0    2    0  /* TxD5 */
191                                         2    8    2      0    2    0  /* RxD5 */
192
193                                         2   1d    2      0    0    0  /* CTS5 */
194                                         2   1f    1      0    2    0  /* RTS5 */
195
196                                         2   18    2      0    0    0  /* CD */
197
198                                 >;
199                         };
200
201                 };
202         };
203
204         qe@e0100000 {
205                 #address-cells = <1>;
206                 #size-cells = <1>;
207                 device_type = "qe";
208                 compatible = "fsl,qe";
209                 ranges = <0 e0100000 00100000>;
210                 reg = <e0100000 480>;
211                 brg-frequency = <0>;
212                 bus-frequency = <BCD3D80>;
213
214                 muram@10000 {
215                         #address-cells = <1>;
216                         #size-cells = <1>;
217                         compatible = "fsl,qe-muram", "fsl,cpm-muram";
218                         ranges = <0 00010000 00004000>;
219
220                         data-only@0 {
221                                 compatible = "fsl,qe-muram-data",
222                                              "fsl,cpm-muram-data";
223                                 reg = <0 4000>;
224                         };
225                 };
226
227                 spi@4c0 {
228                         cell-index = <0>;
229                         compatible = "fsl,spi";
230                         reg = <4c0 40>;
231                         interrupts = <2>;
232                         interrupt-parent = < &qeic >;
233                         mode = "cpu";
234                 };
235
236                 spi@500 {
237                         cell-index = <1>;
238                         compatible = "fsl,spi";
239                         reg = <500 40>;
240                         interrupts = <1>;
241                         interrupt-parent = < &qeic >;
242                         mode = "cpu";
243                 };
244
245                 usb@6c0 {
246                         compatible = "qe_udc";
247                         reg = <6c0 40 8B00 100>;
248                         interrupts = <b>;
249                         interrupt-parent = < &qeic >;
250                         mode = "slave";
251                 };
252
253                 enet0: ucc@2200 {
254                         device_type = "network";
255                         compatible = "ucc_geth";
256                         model = "UCC";
257                         cell-index = <3>;
258                         device-id = <3>;
259                         reg = <2200 200>;
260                         interrupts = <22>;
261                         interrupt-parent = < &qeic >;
262                         local-mac-address = [ 00 00 00 00 00 00 ];
263                         rx-clock-name = "clk9";
264                         tx-clock-name = "clk10";
265                         phy-handle = < &phy3 >;
266                         pio-handle = < &pio3 >;
267                 };
268
269                 enet1: ucc@3200 {
270                         device_type = "network";
271                         compatible = "ucc_geth";
272                         model = "UCC";
273                         cell-index = <4>;
274                         device-id = <4>;
275                         reg = <3200 200>;
276                         interrupts = <23>;
277                         interrupt-parent = < &qeic >;
278                         local-mac-address = [ 00 00 00 00 00 00 ];
279                         rx-clock-name = "clk7";
280                         tx-clock-name = "clk8";
281                         phy-handle = < &phy4 >;
282                         pio-handle = < &pio4 >;
283                 };
284
285                 ucc@2400 {
286                         device_type = "serial";
287                         compatible = "ucc_uart";
288                         model = "UCC";
289                         device-id = <5>;        /* The UCC number, 1-7*/
290                         port-number = <0>;      /* Which ttyQEx device */
291                         soft-uart;              /* We need Soft-UART */
292                         reg = <2400 200>;
293                         interrupts = <28>;      /* From Table 18-12 */
294                         interrupt-parent = < &qeic >;
295                         /*
296                          * For Soft-UART, we need to set TX to 1X, which
297                          * means specifying separate clock sources.
298                          */
299                         rx-clock-name = "brg5";
300                         tx-clock-name = "brg6";
301                         pio-handle = < &pio5 >;
302                 };
303
304
305                 mdio@2320 {
306                         #address-cells = <1>;
307                         #size-cells = <0>;
308                         reg = <2320 18>;
309                         compatible = "fsl,ucc-mdio";
310
311                         phy3: ethernet-phy@03 {
312                                 interrupt-parent = < &ipic >;
313                                 interrupts = <11 8>;
314                                 reg = <3>;
315                                 device_type = "ethernet-phy";
316                         };
317                         phy4: ethernet-phy@04 {
318                                 interrupt-parent = < &ipic >;
319                                 interrupts = <12 8>;
320                                 reg = <4>;
321                                 device_type = "ethernet-phy";
322                         };
323                 };
324
325                 qeic: interrupt-controller@80 {
326                         interrupt-controller;
327                         compatible = "fsl,qe-ic";
328                         #address-cells = <0>;
329                         #interrupt-cells = <1>;
330                         reg = <80 80>;
331                         big-endian;
332                         interrupts = <20 8 21 8>; //high:32 low:33
333                         interrupt-parent = < &ipic >;
334                 };
335         };
336
337         pci0: pci@e0008500 {
338                 cell-index = <1>;
339                 interrupt-map-mask = <f800 0 0 7>;
340                 interrupt-map = <
341                                 /* IDSEL 0x11 AD17 */
342                                  8800 0 0 1 &ipic 14 8
343                                  8800 0 0 2 &ipic 15 8
344                                  8800 0 0 3 &ipic 16 8
345                                  8800 0 0 4 &ipic 17 8
346
347                                 /* IDSEL 0x12 AD18 */
348                                  9000 0 0 1 &ipic 16 8
349                                  9000 0 0 2 &ipic 17 8
350                                  9000 0 0 3 &ipic 14 8
351                                  9000 0 0 4 &ipic 15 8
352
353                                 /* IDSEL 0x13 AD19 */
354                                  9800 0 0 1 &ipic 17 8
355                                  9800 0 0 2 &ipic 14 8
356                                  9800 0 0 3 &ipic 15 8
357                                  9800 0 0 4 &ipic 16 8
358
359                                 /* IDSEL 0x15 AD21*/
360                                  a800 0 0 1 &ipic 14 8
361                                  a800 0 0 2 &ipic 15 8
362                                  a800 0 0 3 &ipic 16 8
363                                  a800 0 0 4 &ipic 17 8
364
365                                 /* IDSEL 0x16 AD22*/
366                                  b000 0 0 1 &ipic 17 8
367                                  b000 0 0 2 &ipic 14 8
368                                  b000 0 0 3 &ipic 15 8
369                                  b000 0 0 4 &ipic 16 8
370
371                                 /* IDSEL 0x17 AD23*/
372                                  b800 0 0 1 &ipic 16 8
373                                  b800 0 0 2 &ipic 17 8
374                                  b800 0 0 3 &ipic 14 8
375                                  b800 0 0 4 &ipic 15 8
376
377                                 /* IDSEL 0x18 AD24*/
378                                  c000 0 0 1 &ipic 15 8
379                                  c000 0 0 2 &ipic 16 8
380                                  c000 0 0 3 &ipic 17 8
381                                  c000 0 0 4 &ipic 14 8>;
382                 interrupt-parent = < &ipic >;
383                 interrupts = <42 8>;
384                 bus-range = <0 0>;
385                 ranges = <02000000 0 90000000 90000000 0 10000000
386                           42000000 0 80000000 80000000 0 10000000
387                           01000000 0 00000000 d0000000 0 00100000>;
388                 clock-frequency = <0>;
389                 #interrupt-cells = <1>;
390                 #size-cells = <2>;
391                 #address-cells = <3>;
392                 reg = <e0008500 100>;
393                 compatible = "fsl,mpc8349-pci";
394                 device_type = "pci";
395         };
396 };