[MIPS] time: SMP-proofing of Sibyte clockevent/clocksource code.
[linux-2.6.git] / arch / mips / sibyte / sb1250 / time.c
1 /*
2  * Copyright (C) 2000, 2001 Broadcom Corporation
3  *
4  * This program is free software; you can redistribute it and/or
5  * modify it under the terms of the GNU General Public License
6  * as published by the Free Software Foundation; either version 2
7  * of the License, or (at your option) any later version.
8  *
9  * This program is distributed in the hope that it will be useful,
10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12  * GNU General Public License for more details.
13  *
14  * You should have received a copy of the GNU General Public License
15  * along with this program; if not, write to the Free Software
16  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
17  */
18
19 /*
20  * These are routines to set up and handle interrupts from the
21  * sb1250 general purpose timer 0.  We're using the timer as a
22  * system clock, so we set it up to run at 100 Hz.  On every
23  * interrupt, we update our idea of what the time of day is,
24  * then call do_timer() in the architecture-independent kernel
25  * code to do general bookkeeping (e.g. update jiffies, run
26  * bottom halves, etc.)
27  */
28 #include <linux/clockchips.h>
29 #include <linux/interrupt.h>
30 #include <linux/sched.h>
31 #include <linux/spinlock.h>
32 #include <linux/kernel_stat.h>
33
34 #include <asm/irq.h>
35 #include <asm/addrspace.h>
36 #include <asm/time.h>
37 #include <asm/io.h>
38
39 #include <asm/sibyte/sb1250.h>
40 #include <asm/sibyte/sb1250_regs.h>
41 #include <asm/sibyte/sb1250_int.h>
42 #include <asm/sibyte/sb1250_scd.h>
43
44
45 #define IMR_IP2_VAL     K_INT_MAP_I0
46 #define IMR_IP3_VAL     K_INT_MAP_I1
47 #define IMR_IP4_VAL     K_INT_MAP_I2
48
49 #define SB1250_HPT_NUM          3
50 #define SB1250_HPT_VALUE        M_SCD_TIMER_CNT /* max value */
51
52
53 extern int sb1250_steal_irq(int irq);
54
55 /*
56  * The general purpose timer ticks at 1 Mhz independent if
57  * the rest of the system
58  */
59 static void sibyte_set_mode(enum clock_event_mode mode,
60                            struct clock_event_device *evt)
61 {
62         unsigned int cpu = smp_processor_id();
63         void __iomem *timer_cfg, *timer_init;
64
65         timer_cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
66         timer_init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT));
67
68         switch(mode) {
69         case CLOCK_EVT_MODE_PERIODIC:
70                 __raw_writeq(0, timer_cfg);
71                 __raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1, timer_init);
72                 __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
73                              timer_cfg);
74                 break;
75
76         case CLOCK_EVT_MODE_ONESHOT:
77                 /* Stop the timer until we actually program a shot */
78         case CLOCK_EVT_MODE_SHUTDOWN:
79                 __raw_writeq(0, timer_cfg);
80                 break;
81
82         case CLOCK_EVT_MODE_UNUSED:     /* shuddup gcc */
83         case CLOCK_EVT_MODE_RESUME:
84                 ;
85         }
86 }
87
88 static int
89 sibyte_next_event(unsigned long delta, struct clock_event_device *evt)
90 {
91         unsigned int cpu = smp_processor_id();
92         void __iomem *timer_cfg, *timer_init;
93
94         timer_cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
95         timer_init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT));
96
97         __raw_writeq(0, timer_cfg);
98         __raw_writeq(delta, timer_init);
99         __raw_writeq(M_SCD_TIMER_ENABLE, timer_cfg);
100
101         return 0;
102 }
103
104 static irqreturn_t sibyte_counter_handler(int irq, void *dev_id)
105 {
106         unsigned int cpu = smp_processor_id();
107         struct clock_event_device *cd = dev_id;
108
109         /* ACK interrupt */
110         ____raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
111                        IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
112
113         cd->event_handler(cd);
114
115         return IRQ_HANDLED;
116 }
117
118 static struct irqaction sibyte_irqaction = {
119         .handler        = sibyte_counter_handler,
120         .flags          = IRQF_DISABLED | IRQF_PERCPU,
121         .name           = "timer",
122 };
123
124 static DEFINE_PER_CPU(struct clock_event_device, sibyte_hpt_clockevent);
125 static DEFINE_PER_CPU(struct irqaction, sibyte_hpt_irqaction);
126 static DEFINE_PER_CPU(char [18], sibyte_hpt_name);
127
128 void __cpuinit sb1250_clockevent_init(void)
129 {
130         unsigned int cpu = smp_processor_id();
131         unsigned int irq = K_INT_TIMER_0 + cpu;
132         struct irqaction *action = &per_cpu(sibyte_hpt_irqaction, cpu);
133         struct clock_event_device *cd = &per_cpu(sibyte_hpt_clockevent, cpu);
134         unsigned char *name = per_cpu(sibyte_hpt_name, cpu);
135
136         /* Only have 4 general purpose timers, and we use last one as hpt */
137         BUG_ON(cpu > 2);
138
139         sprintf(name, "bcm1480-counter %d", cpu);
140         cd->name                = name;
141         cd->features            = CLOCK_EVT_FEAT_PERIODIC |
142                                   CLOCK_EVT_MODE_ONESHOT;
143         clockevent_set_clock(cd, V_SCD_TIMER_FREQ);
144         cd->max_delta_ns        = clockevent_delta2ns(0x7fffff, cd);
145         cd->min_delta_ns        = clockevent_delta2ns(1, cd);
146         cd->rating              = 200;
147         cd->irq                 = irq;
148         cd->cpumask             = cpumask_of_cpu(cpu);
149         cd->set_next_event      = sibyte_next_event;
150         cd->set_mode            = sibyte_set_mode;
151         clockevents_register_device(cd);
152
153         sb1250_mask_irq(cpu, irq);
154
155         /* Map the timer interrupt to ip[4] of this cpu */
156         __raw_writeq(IMR_IP4_VAL,
157                      IOADDR(A_IMR_REGISTER(cpu, R_IMR_INTERRUPT_MAP_BASE) +
158                             (irq << 3)));
159         cd->cpumask = cpumask_of_cpu(0);
160
161         sb1250_unmask_irq(cpu, irq);
162         sb1250_steal_irq(irq);
163
164         action->handler = sibyte_counter_handler;
165         action->flags   = IRQF_DISABLED | IRQF_PERCPU;
166         action->name    = name;
167         action->dev_id  = cd;
168         setup_irq(irq, &sibyte_irqaction);
169 }
170
171 /*
172  * The HPT is free running from SB1250_HPT_VALUE down to 0 then starts over
173  * again.
174  */
175 static cycle_t sb1250_hpt_read(void)
176 {
177         unsigned int count;
178
179         count = G_SCD_TIMER_CNT(__raw_readq(IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_CNT))));
180
181         return SB1250_HPT_VALUE - count;
182 }
183
184 struct clocksource bcm1250_clocksource = {
185         .name   = "MIPS",
186         .rating = 200,
187         .read   = sb1250_hpt_read,
188         .mask   = CLOCKSOURCE_MASK(23),
189         .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
190 };
191
192 void __init sb1250_clocksource_init(void)
193 {
194         struct clocksource *cs = &bcm1250_clocksource;
195
196         /* Setup hpt using timer #3 but do not enable irq for it */
197         __raw_writeq(0,
198                      IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM,
199                                                  R_SCD_TIMER_CFG)));
200         __raw_writeq(SB1250_HPT_VALUE,
201                      IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM,
202                                                  R_SCD_TIMER_INIT)));
203         __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
204                      IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM,
205                                                  R_SCD_TIMER_CFG)));
206
207         clocksource_set_clock(cs, V_SCD_TIMER_FREQ);
208         clocksource_register(cs);
209 }
210
211 void __init plat_time_init(void)
212 {
213         sb1250_clocksource_init();
214         sb1250_clockevent_init();
215 }