[MIPS] Oprofile: Support VSMP on 34K.
[linux-2.6.git] / arch / mips / oprofile / op_model_mipsxx.c
1 /*
2  * This file is subject to the terms and conditions of the GNU General Public
3  * License.  See the file "COPYING" in the main directory of this archive
4  * for more details.
5  *
6  * Copyright (C) 2004, 2005 by Ralf Baechle
7  * Copyright (C) 2005 by MIPS Technologies, Inc.
8  */
9 #include <linux/oprofile.h>
10 #include <linux/interrupt.h>
11 #include <linux/smp.h>
12
13 #include "op_impl.h"
14
15 #define M_PERFCTL_EXL                   (1UL      <<  0)
16 #define M_PERFCTL_KERNEL                (1UL      <<  1)
17 #define M_PERFCTL_SUPERVISOR            (1UL      <<  2)
18 #define M_PERFCTL_USER                  (1UL      <<  3)
19 #define M_PERFCTL_INTERRUPT_ENABLE      (1UL      <<  4)
20 #define M_PERFCTL_EVENT(event)          ((event)  << 5)
21 #define M_PERFCTL_VPEID(vpe)            ((vpe)    << 16)
22 #define M_PERFCTL_MT_EN(filter)         ((filter) << 20)
23 #define    M_TC_EN_ALL                  M_PERFCTL_MT_EN(0)
24 #define    M_TC_EN_VPE                  M_PERFCTL_MT_EN(1)
25 #define    M_TC_EN_TC                   M_PERFCTL_MT_EN(2)
26 #define M_PERFCTL_TCID(tcid)            ((tcid)   << 22)
27 #define M_PERFCTL_WIDE                  (1UL      << 30)
28 #define M_PERFCTL_MORE                  (1UL      << 31)
29
30 #define M_COUNTER_OVERFLOW              (1UL      << 31)
31
32 #ifdef CONFIG_MIPS_MT_SMP
33 #define WHAT    (M_TC_EN_VPE | M_PERFCTL_VPEID(smp_processor_id()))
34 #else
35 #define WHAT    0
36 #endif
37
38 #define __define_perf_accessors(r, n, np)                               \
39                                                                         \
40 static inline unsigned int r_c0_ ## r ## n(void)                        \
41 {                                                                       \
42         unsigned int cpu = smp_processor_id();                          \
43                                                                         \
44         switch (cpu) {                                                  \
45         case 0:                                                         \
46                 return read_c0_ ## r ## n();                            \
47         case 1:                                                         \
48                 return read_c0_ ## r ## np();                           \
49         default:                                                        \
50                 BUG();                                                  \
51         }                                                               \
52 }                                                                       \
53                                                                         \
54 static inline void w_c0_ ## r ## n(unsigned int value)                  \
55 {                                                                       \
56         unsigned int cpu = smp_processor_id();                          \
57                                                                         \
58         switch (cpu) {                                                  \
59         case 0:                                                         \
60                 write_c0_ ## r ## n(value);                             \
61                 return;                                                 \
62         case 1:                                                         \
63                 write_c0_ ## r ## np(value);                            \
64                 return;                                                 \
65         default:                                                        \
66                 BUG();                                                  \
67         }                                                               \
68 }                                                                       \
69
70 __define_perf_accessors(perfcntr, 0, 2)
71 __define_perf_accessors(perfcntr, 1, 3)
72 __define_perf_accessors(perfcntr, 2, 2)
73 __define_perf_accessors(perfcntr, 3, 2)
74
75 __define_perf_accessors(perfctrl, 0, 2)
76 __define_perf_accessors(perfctrl, 1, 3)
77 __define_perf_accessors(perfctrl, 2, 2)
78 __define_perf_accessors(perfctrl, 3, 2)
79
80 struct op_mips_model op_model_mipsxx_ops;
81
82 static struct mipsxx_register_config {
83         unsigned int control[4];
84         unsigned int counter[4];
85 } reg;
86
87 /* Compute all of the registers in preparation for enabling profiling.  */
88
89 static void mipsxx_reg_setup(struct op_counter_config *ctr)
90 {
91         unsigned int counters = op_model_mipsxx_ops.num_counters;
92         int i;
93
94         /* Compute the performance counter control word.  */
95         /* For now count kernel and user mode */
96         for (i = 0; i < counters; i++) {
97                 reg.control[i] = 0;
98                 reg.counter[i] = 0;
99
100                 if (!ctr[i].enabled)
101                         continue;
102
103                 reg.control[i] = M_PERFCTL_EVENT(ctr[i].event) |
104                                  M_PERFCTL_INTERRUPT_ENABLE;
105                 if (ctr[i].kernel)
106                         reg.control[i] |= M_PERFCTL_KERNEL;
107                 if (ctr[i].user)
108                         reg.control[i] |= M_PERFCTL_USER;
109                 if (ctr[i].exl)
110                         reg.control[i] |= M_PERFCTL_EXL;
111                 reg.counter[i] = 0x80000000 - ctr[i].count;
112         }
113 }
114
115 /* Program all of the registers in preparation for enabling profiling.  */
116
117 static void mipsxx_cpu_setup (void *args)
118 {
119         unsigned int counters = op_model_mipsxx_ops.num_counters;
120
121         switch (counters) {
122         case 4:
123                 w_c0_perfctrl3(0);
124                 w_c0_perfcntr3(reg.counter[3]);
125         case 3:
126                 w_c0_perfctrl2(0);
127                 w_c0_perfcntr2(reg.counter[2]);
128         case 2:
129                 w_c0_perfctrl1(0);
130                 w_c0_perfcntr1(reg.counter[1]);
131         case 1:
132                 w_c0_perfctrl0(0);
133                 w_c0_perfcntr0(reg.counter[0]);
134         }
135 }
136
137 /* Start all counters on current CPU */
138 static void mipsxx_cpu_start(void *args)
139 {
140         unsigned int counters = op_model_mipsxx_ops.num_counters;
141
142         switch (counters) {
143         case 4:
144                 w_c0_perfctrl3(WHAT | reg.control[3]);
145         case 3:
146                 w_c0_perfctrl2(WHAT | reg.control[2]);
147         case 2:
148                 w_c0_perfctrl1(WHAT | reg.control[1]);
149         case 1:
150                 w_c0_perfctrl0(WHAT | reg.control[0]);
151         }
152 }
153
154 /* Stop all counters on current CPU */
155 static void mipsxx_cpu_stop(void *args)
156 {
157         unsigned int counters = op_model_mipsxx_ops.num_counters;
158
159         switch (counters) {
160         case 4:
161                 w_c0_perfctrl3(0);
162         case 3:
163                 w_c0_perfctrl2(0);
164         case 2:
165                 w_c0_perfctrl1(0);
166         case 1:
167                 w_c0_perfctrl0(0);
168         }
169 }
170
171 static int mipsxx_perfcount_handler(struct pt_regs *regs)
172 {
173         unsigned int counters = op_model_mipsxx_ops.num_counters;
174         unsigned int control;
175         unsigned int counter;
176         int handled = 0;
177
178         switch (counters) {
179 #define HANDLE_COUNTER(n)                                               \
180         case n + 1:                                                     \
181                 control = r_c0_perfctrl ## n();                         \
182                 counter = r_c0_perfcntr ## n();                         \
183                 if ((control & M_PERFCTL_INTERRUPT_ENABLE) &&           \
184                     (counter & M_COUNTER_OVERFLOW)) {                   \
185                         oprofile_add_sample(regs, n);                   \
186                         w_c0_perfcntr ## n(reg.counter[n]);             \
187                         handled = 1;                                    \
188                 }
189         HANDLE_COUNTER(3)
190         HANDLE_COUNTER(2)
191         HANDLE_COUNTER(1)
192         HANDLE_COUNTER(0)
193         }
194
195         return handled;
196 }
197
198 #define M_CONFIG1_PC    (1 << 4)
199
200 static inline int __n_counters(void)
201 {
202         if (!(read_c0_config1() & M_CONFIG1_PC))
203                 return 0;
204         if (!(r_c0_perfctrl0() & M_PERFCTL_MORE))
205                 return 1;
206         if (!(r_c0_perfctrl1() & M_PERFCTL_MORE))
207                 return 2;
208         if (!(r_c0_perfctrl2() & M_PERFCTL_MORE))
209                 return 3;
210
211         return 4;
212 }
213
214 static inline int n_counters(void)
215 {
216         int counters = __n_counters();
217
218 #ifndef CONFIG_SMP
219         if (current_cpu_data.cputype == CPU_34K)
220                 return counters >> 1;
221 #endif
222
223         return counters;
224 }
225
226 static inline void reset_counters(int counters)
227 {
228         switch (counters) {
229         case 4:
230                 w_c0_perfctrl3(0);
231                 w_c0_perfcntr3(0);
232         case 3:
233                 w_c0_perfctrl2(0);
234                 w_c0_perfcntr2(0);
235         case 2:
236                 w_c0_perfctrl1(0);
237                 w_c0_perfcntr1(0);
238         case 1:
239                 w_c0_perfctrl0(0);
240                 w_c0_perfcntr0(0);
241         }
242 }
243
244 static int __init mipsxx_init(void)
245 {
246         int counters;
247
248         counters = n_counters();
249         if (counters == 0) {
250                 printk(KERN_ERR "Oprofile: CPU has no performance counters\n");
251                 return -ENODEV;
252         }
253
254         reset_counters(counters);
255
256         op_model_mipsxx_ops.num_counters = counters;
257         switch (current_cpu_data.cputype) {
258         case CPU_20KC:
259                 op_model_mipsxx_ops.cpu_type = "mips/20K";
260                 break;
261
262         case CPU_24K:
263                 op_model_mipsxx_ops.cpu_type = "mips/24K";
264                 break;
265
266         case CPU_25KF:
267                 op_model_mipsxx_ops.cpu_type = "mips/25K";
268                 break;
269
270         case CPU_34K:
271                 op_model_mipsxx_ops.cpu_type = "mips/34K";
272                 break;
273
274         case CPU_74K:
275                 op_model_mipsxx_ops.cpu_type = "mips/74K";
276                 break;
277
278         case CPU_5KC:
279                 op_model_mipsxx_ops.cpu_type = "mips/5K";
280                 break;
281
282         case CPU_SB1:
283         case CPU_SB1A:
284                 op_model_mipsxx_ops.cpu_type = "mips/sb1";
285                 break;
286
287         default:
288                 printk(KERN_ERR "Profiling unsupported for this CPU\n");
289
290                 return -ENODEV;
291         }
292
293         perf_irq = mipsxx_perfcount_handler;
294
295         return 0;
296 }
297
298 static void mipsxx_exit(void)
299 {
300         reset_counters(op_model_mipsxx_ops.num_counters);
301
302         perf_irq = null_perf_irq;
303 }
304
305 struct op_mips_model op_model_mipsxx_ops = {
306         .reg_setup      = mipsxx_reg_setup,
307         .cpu_setup      = mipsxx_cpu_setup,
308         .init           = mipsxx_init,
309         .exit           = mipsxx_exit,
310         .cpu_start      = mipsxx_cpu_start,
311         .cpu_stop       = mipsxx_cpu_stop,
312 };