[PATCH] m32r: framebuffer device support
[linux-2.6.git] / arch / m32r / kernel / setup_m32700ut.c
1 /*
2  *  linux/arch/m32r/kernel/setup_m32700ut.c
3  *
4  *  Setup routines for Renesas M32700UT Board
5  *
6  *  Copyright (c) 2002-2005  Hiroyuki Kondo, Hirokazu Takata,
7  *                           Hitoshi Yamamoto, Takeo Takahashi
8  *
9  *  This file is subject to the terms and conditions of the GNU General
10  *  Public License.  See the file "COPYING" in the main directory of this
11  *  archive for more details.
12  */
13
14 #include <linux/config.h>
15 #include <linux/irq.h>
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/device.h>
19
20 #include <asm/system.h>
21 #include <asm/m32r.h>
22 #include <asm/io.h>
23
24 /*
25  * M32700 Interrupt Control Unit (Level 1)
26  */
27 #define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))
28
29 #ifndef CONFIG_SMP
30 typedef struct {
31         unsigned long icucr;  /* ICU Control Register */
32 } icu_data_t;
33 #endif /* CONFIG_SMP */
34
35 static icu_data_t icu_data[M32700UT_NUM_CPU_IRQ];
36
37 static void disable_m32700ut_irq(unsigned int irq)
38 {
39         unsigned long port, data;
40
41         port = irq2port(irq);
42         data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7;
43         outl(data, port);
44 }
45
46 static void enable_m32700ut_irq(unsigned int irq)
47 {
48         unsigned long port, data;
49
50         port = irq2port(irq);
51         data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6;
52         outl(data, port);
53 }
54
55 static void mask_and_ack_m32700ut(unsigned int irq)
56 {
57         disable_m32700ut_irq(irq);
58 }
59
60 static void end_m32700ut_irq(unsigned int irq)
61 {
62         enable_m32700ut_irq(irq);
63 }
64
65 static unsigned int startup_m32700ut_irq(unsigned int irq)
66 {
67         enable_m32700ut_irq(irq);
68         return (0);
69 }
70
71 static void shutdown_m32700ut_irq(unsigned int irq)
72 {
73         unsigned long port;
74
75         port = irq2port(irq);
76         outl(M32R_ICUCR_ILEVEL7, port);
77 }
78
79 static struct hw_interrupt_type m32700ut_irq_type =
80 {
81         .typename = "M32700UT-IRQ",
82         .startup = startup_m32700ut_irq,
83         .shutdown = shutdown_m32700ut_irq,
84         .enable = enable_m32700ut_irq,
85         .disable = disable_m32700ut_irq,
86         .ack = mask_and_ack_m32700ut,
87         .end = end_m32700ut_irq
88 };
89
90 /*
91  * Interrupt Control Unit of PLD on M32700UT (Level 2)
92  */
93 #define irq2pldirq(x)           ((x) - M32700UT_PLD_IRQ_BASE)
94 #define pldirq2port(x)          (unsigned long)((int)PLD_ICUCR1 + \
95                                  (((x) - 1) * sizeof(unsigned short)))
96
97 typedef struct {
98         unsigned short icucr;  /* ICU Control Register */
99 } pld_icu_data_t;
100
101 static pld_icu_data_t pld_icu_data[M32700UT_NUM_PLD_IRQ];
102
103 static void disable_m32700ut_pld_irq(unsigned int irq)
104 {
105         unsigned long port, data;
106         unsigned int pldirq;
107
108         pldirq = irq2pldirq(irq);
109 //      disable_m32700ut_irq(M32R_IRQ_INT1);
110         port = pldirq2port(pldirq);
111         data = pld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
112         outw(data, port);
113 }
114
115 static void enable_m32700ut_pld_irq(unsigned int irq)
116 {
117         unsigned long port, data;
118         unsigned int pldirq;
119
120         pldirq = irq2pldirq(irq);
121 //      enable_m32700ut_irq(M32R_IRQ_INT1);
122         port = pldirq2port(pldirq);
123         data = pld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
124         outw(data, port);
125 }
126
127 static void mask_and_ack_m32700ut_pld(unsigned int irq)
128 {
129         disable_m32700ut_pld_irq(irq);
130 //      mask_and_ack_m32700ut(M32R_IRQ_INT1);
131 }
132
133 static void end_m32700ut_pld_irq(unsigned int irq)
134 {
135         enable_m32700ut_pld_irq(irq);
136         end_m32700ut_irq(M32R_IRQ_INT1);
137 }
138
139 static unsigned int startup_m32700ut_pld_irq(unsigned int irq)
140 {
141         enable_m32700ut_pld_irq(irq);
142         return (0);
143 }
144
145 static void shutdown_m32700ut_pld_irq(unsigned int irq)
146 {
147         unsigned long port;
148         unsigned int pldirq;
149
150         pldirq = irq2pldirq(irq);
151 //      shutdown_m32700ut_irq(M32R_IRQ_INT1);
152         port = pldirq2port(pldirq);
153         outw(PLD_ICUCR_ILEVEL7, port);
154 }
155
156 static struct hw_interrupt_type m32700ut_pld_irq_type =
157 {
158         .typename = "M32700UT-PLD-IRQ",
159         .startup = startup_m32700ut_pld_irq,
160         .shutdown = shutdown_m32700ut_pld_irq,
161         .enable = enable_m32700ut_pld_irq,
162         .disable = disable_m32700ut_pld_irq,
163         .ack = mask_and_ack_m32700ut_pld,
164         .end = end_m32700ut_pld_irq
165 };
166
167 /*
168  * Interrupt Control Unit of PLD on M32700UT-LAN (Level 2)
169  */
170 #define irq2lanpldirq(x)        ((x) - M32700UT_LAN_PLD_IRQ_BASE)
171 #define lanpldirq2port(x)       (unsigned long)((int)M32700UT_LAN_ICUCR1 + \
172                                  (((x) - 1) * sizeof(unsigned short)))
173
174 static pld_icu_data_t lanpld_icu_data[M32700UT_NUM_LAN_PLD_IRQ];
175
176 static void disable_m32700ut_lanpld_irq(unsigned int irq)
177 {
178         unsigned long port, data;
179         unsigned int pldirq;
180
181         pldirq = irq2lanpldirq(irq);
182         port = lanpldirq2port(pldirq);
183         data = lanpld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
184         outw(data, port);
185 }
186
187 static void enable_m32700ut_lanpld_irq(unsigned int irq)
188 {
189         unsigned long port, data;
190         unsigned int pldirq;
191
192         pldirq = irq2lanpldirq(irq);
193         port = lanpldirq2port(pldirq);
194         data = lanpld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
195         outw(data, port);
196 }
197
198 static void mask_and_ack_m32700ut_lanpld(unsigned int irq)
199 {
200         disable_m32700ut_lanpld_irq(irq);
201 }
202
203 static void end_m32700ut_lanpld_irq(unsigned int irq)
204 {
205         enable_m32700ut_lanpld_irq(irq);
206         end_m32700ut_irq(M32R_IRQ_INT0);
207 }
208
209 static unsigned int startup_m32700ut_lanpld_irq(unsigned int irq)
210 {
211         enable_m32700ut_lanpld_irq(irq);
212         return (0);
213 }
214
215 static void shutdown_m32700ut_lanpld_irq(unsigned int irq)
216 {
217         unsigned long port;
218         unsigned int pldirq;
219
220         pldirq = irq2lanpldirq(irq);
221         port = lanpldirq2port(pldirq);
222         outw(PLD_ICUCR_ILEVEL7, port);
223 }
224
225 static struct hw_interrupt_type m32700ut_lanpld_irq_type =
226 {
227         .typename = "M32700UT-PLD-LAN-IRQ",
228         .startup = startup_m32700ut_lanpld_irq,
229         .shutdown = shutdown_m32700ut_lanpld_irq,
230         .enable = enable_m32700ut_lanpld_irq,
231         .disable = disable_m32700ut_lanpld_irq,
232         .ack = mask_and_ack_m32700ut_lanpld,
233         .end = end_m32700ut_lanpld_irq
234 };
235
236 /*
237  * Interrupt Control Unit of PLD on M32700UT-LCD (Level 2)
238  */
239 #define irq2lcdpldirq(x)        ((x) - M32700UT_LCD_PLD_IRQ_BASE)
240 #define lcdpldirq2port(x)       (unsigned long)((int)M32700UT_LCD_ICUCR1 + \
241                                  (((x) - 1) * sizeof(unsigned short)))
242
243 static pld_icu_data_t lcdpld_icu_data[M32700UT_NUM_LCD_PLD_IRQ];
244
245 static void disable_m32700ut_lcdpld_irq(unsigned int irq)
246 {
247         unsigned long port, data;
248         unsigned int pldirq;
249
250         pldirq = irq2lcdpldirq(irq);
251         port = lcdpldirq2port(pldirq);
252         data = lcdpld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
253         outw(data, port);
254 }
255
256 static void enable_m32700ut_lcdpld_irq(unsigned int irq)
257 {
258         unsigned long port, data;
259         unsigned int pldirq;
260
261         pldirq = irq2lcdpldirq(irq);
262         port = lcdpldirq2port(pldirq);
263         data = lcdpld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
264         outw(data, port);
265 }
266
267 static void mask_and_ack_m32700ut_lcdpld(unsigned int irq)
268 {
269         disable_m32700ut_lcdpld_irq(irq);
270 }
271
272 static void end_m32700ut_lcdpld_irq(unsigned int irq)
273 {
274         enable_m32700ut_lcdpld_irq(irq);
275         end_m32700ut_irq(M32R_IRQ_INT2);
276 }
277
278 static unsigned int startup_m32700ut_lcdpld_irq(unsigned int irq)
279 {
280         enable_m32700ut_lcdpld_irq(irq);
281         return (0);
282 }
283
284 static void shutdown_m32700ut_lcdpld_irq(unsigned int irq)
285 {
286         unsigned long port;
287         unsigned int pldirq;
288
289         pldirq = irq2lcdpldirq(irq);
290         port = lcdpldirq2port(pldirq);
291         outw(PLD_ICUCR_ILEVEL7, port);
292 }
293
294 static struct hw_interrupt_type m32700ut_lcdpld_irq_type =
295 {
296         .typename = "M32700UT-PLD-LCD-IRQ",
297         .startup = startup_m32700ut_lcdpld_irq,
298         .shutdown = shutdown_m32700ut_lcdpld_irq,
299         .enable = enable_m32700ut_lcdpld_irq,
300         .disable = disable_m32700ut_lcdpld_irq,
301         .ack = mask_and_ack_m32700ut_lcdpld,
302         .end = end_m32700ut_lcdpld_irq
303 };
304
305 void __init init_IRQ(void)
306 {
307 #if defined(CONFIG_SMC91X)
308         /* INT#0: LAN controller on M32700UT-LAN (SMC91C111)*/
309         irq_desc[M32700UT_LAN_IRQ_LAN].status = IRQ_DISABLED;
310         irq_desc[M32700UT_LAN_IRQ_LAN].handler = &m32700ut_lanpld_irq_type;
311         irq_desc[M32700UT_LAN_IRQ_LAN].action = 0;
312         irq_desc[M32700UT_LAN_IRQ_LAN].depth = 1;       /* disable nested irq */
313         lanpld_icu_data[irq2lanpldirq(M32700UT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02;   /* "H" edge sense */
314         disable_m32700ut_lanpld_irq(M32700UT_LAN_IRQ_LAN);
315 #endif  /* CONFIG_SMC91X */
316
317         /* MFT2 : system timer */
318         irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED;
319         irq_desc[M32R_IRQ_MFT2].handler = &m32700ut_irq_type;
320         irq_desc[M32R_IRQ_MFT2].action = 0;
321         irq_desc[M32R_IRQ_MFT2].depth = 1;
322         icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
323         disable_m32700ut_irq(M32R_IRQ_MFT2);
324
325         /* SIO0 : receive */
326         irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED;
327         irq_desc[M32R_IRQ_SIO0_R].handler = &m32700ut_irq_type;
328         irq_desc[M32R_IRQ_SIO0_R].action = 0;
329         irq_desc[M32R_IRQ_SIO0_R].depth = 1;
330         icu_data[M32R_IRQ_SIO0_R].icucr = 0;
331         disable_m32700ut_irq(M32R_IRQ_SIO0_R);
332
333         /* SIO0 : send */
334         irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED;
335         irq_desc[M32R_IRQ_SIO0_S].handler = &m32700ut_irq_type;
336         irq_desc[M32R_IRQ_SIO0_S].action = 0;
337         irq_desc[M32R_IRQ_SIO0_S].depth = 1;
338         icu_data[M32R_IRQ_SIO0_S].icucr = 0;
339         disable_m32700ut_irq(M32R_IRQ_SIO0_S);
340
341         /* SIO1 : receive */
342         irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED;
343         irq_desc[M32R_IRQ_SIO1_R].handler = &m32700ut_irq_type;
344         irq_desc[M32R_IRQ_SIO1_R].action = 0;
345         irq_desc[M32R_IRQ_SIO1_R].depth = 1;
346         icu_data[M32R_IRQ_SIO1_R].icucr = 0;
347         disable_m32700ut_irq(M32R_IRQ_SIO1_R);
348
349         /* SIO1 : send */
350         irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED;
351         irq_desc[M32R_IRQ_SIO1_S].handler = &m32700ut_irq_type;
352         irq_desc[M32R_IRQ_SIO1_S].action = 0;
353         irq_desc[M32R_IRQ_SIO1_S].depth = 1;
354         icu_data[M32R_IRQ_SIO1_S].icucr = 0;
355         disable_m32700ut_irq(M32R_IRQ_SIO1_S);
356
357         /* DMA1 : */
358         irq_desc[M32R_IRQ_DMA1].status = IRQ_DISABLED;
359         irq_desc[M32R_IRQ_DMA1].handler = &m32700ut_irq_type;
360         irq_desc[M32R_IRQ_DMA1].action = 0;
361         irq_desc[M32R_IRQ_DMA1].depth = 1;
362         icu_data[M32R_IRQ_DMA1].icucr = 0;
363         disable_m32700ut_irq(M32R_IRQ_DMA1);
364
365 #ifdef CONFIG_SERIAL_M32R_PLDSIO
366         /* INT#1: SIO0 Receive on PLD */
367         irq_desc[PLD_IRQ_SIO0_RCV].status = IRQ_DISABLED;
368         irq_desc[PLD_IRQ_SIO0_RCV].handler = &m32700ut_pld_irq_type;
369         irq_desc[PLD_IRQ_SIO0_RCV].action = 0;
370         irq_desc[PLD_IRQ_SIO0_RCV].depth = 1;   /* disable nested irq */
371         pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
372         disable_m32700ut_pld_irq(PLD_IRQ_SIO0_RCV);
373
374         /* INT#1: SIO0 Send on PLD */
375         irq_desc[PLD_IRQ_SIO0_SND].status = IRQ_DISABLED;
376         irq_desc[PLD_IRQ_SIO0_SND].handler = &m32700ut_pld_irq_type;
377         irq_desc[PLD_IRQ_SIO0_SND].action = 0;
378         irq_desc[PLD_IRQ_SIO0_SND].depth = 1;   /* disable nested irq */
379         pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
380         disable_m32700ut_pld_irq(PLD_IRQ_SIO0_SND);
381 #endif  /* CONFIG_SERIAL_M32R_PLDSIO */
382
383         /* INT#1: CFC IREQ on PLD */
384         irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED;
385         irq_desc[PLD_IRQ_CFIREQ].handler = &m32700ut_pld_irq_type;
386         irq_desc[PLD_IRQ_CFIREQ].action = 0;
387         irq_desc[PLD_IRQ_CFIREQ].depth = 1;     /* disable nested irq */
388         pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01;       /* 'L' level sense */
389         disable_m32700ut_pld_irq(PLD_IRQ_CFIREQ);
390
391         /* INT#1: CFC Insert on PLD */
392         irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED;
393         irq_desc[PLD_IRQ_CFC_INSERT].handler = &m32700ut_pld_irq_type;
394         irq_desc[PLD_IRQ_CFC_INSERT].action = 0;
395         irq_desc[PLD_IRQ_CFC_INSERT].depth = 1; /* disable nested irq */
396         pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00;   /* 'L' edge sense */
397         disable_m32700ut_pld_irq(PLD_IRQ_CFC_INSERT);
398
399         /* INT#1: CFC Eject on PLD */
400         irq_desc[PLD_IRQ_CFC_EJECT].status = IRQ_DISABLED;
401         irq_desc[PLD_IRQ_CFC_EJECT].handler = &m32700ut_pld_irq_type;
402         irq_desc[PLD_IRQ_CFC_EJECT].action = 0;
403         irq_desc[PLD_IRQ_CFC_EJECT].depth = 1;  /* disable nested irq */
404         pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02;    /* 'H' edge sense */
405         disable_m32700ut_pld_irq(PLD_IRQ_CFC_EJECT);
406
407         /*
408          * INT0# is used for LAN, DIO
409          * We enable it here.
410          */
411         icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;
412         enable_m32700ut_irq(M32R_IRQ_INT0);
413
414         /*
415          * INT1# is used for UART, MMC, CF Controller in FPGA.
416          * We enable it here.
417          */
418         icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;
419         enable_m32700ut_irq(M32R_IRQ_INT1);
420
421 #if defined(CONFIG_USB)
422         outw(USBCR_OTGS, USBCR);        /* USBCR: non-OTG */
423
424     irq_desc[M32700UT_LCD_IRQ_USB_INT1].status = IRQ_DISABLED;
425     irq_desc[M32700UT_LCD_IRQ_USB_INT1].handler = &m32700ut_lcdpld_irq_type;
426     irq_desc[M32700UT_LCD_IRQ_USB_INT1].action = 0;
427     irq_desc[M32700UT_LCD_IRQ_USB_INT1].depth = 1;
428     lcdpld_icu_data[irq2lcdpldirq(M32700UT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01;  /* "L" level sense */
429     disable_m32700ut_lcdpld_irq(M32700UT_LCD_IRQ_USB_INT1);
430 #endif
431         /*
432          * INT2# is used for BAT, USB, AUDIO
433          * We enable it here.
434          */
435         icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01;
436         enable_m32700ut_irq(M32R_IRQ_INT2);
437
438 #if defined(CONFIG_VIDEO_M32R_AR)
439         /*
440          * INT3# is used for AR
441          */
442         irq_desc[M32R_IRQ_INT3].status = IRQ_DISABLED;
443         irq_desc[M32R_IRQ_INT3].handler = &m32700ut_irq_type;
444         irq_desc[M32R_IRQ_INT3].action = 0;
445         irq_desc[M32R_IRQ_INT3].depth = 1;
446         icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
447         disable_m32700ut_irq(M32R_IRQ_INT3);
448 #endif  /* CONFIG_VIDEO_M32R_AR */
449 }
450
451 #if defined(CONFIG_SMC91X)
452
453 #define LAN_IOSTART     0x300
454 #define LAN_IOEND       0x320
455 static struct resource smc91x_resources[] = {
456         [0] = {
457                 .start  = (LAN_IOSTART),
458                 .end    = (LAN_IOEND),
459                 .flags  = IORESOURCE_MEM,
460         },
461         [1] = {
462                 .start  = M32700UT_LAN_IRQ_LAN,
463                 .end    = M32700UT_LAN_IRQ_LAN,
464                 .flags  = IORESOURCE_IRQ,
465         }
466 };
467
468 static struct platform_device smc91x_device = {
469         .name           = "smc91x",
470         .id             = 0,
471         .num_resources  = ARRAY_SIZE(smc91x_resources),
472         .resource       = smc91x_resources,
473 };
474 #endif
475
476 #if defined(CONFIG_FB_S1D13XXX)
477
478 #include <video/s1d13xxxfb.h>
479 #include <asm/s1d13806.h>
480
481 static struct s1d13xxxfb_pdata s1d13xxxfb_data = {
482         .initregs               = s1d13xxxfb_initregs,
483         .initregssize           = ARRAY_SIZE(s1d13xxxfb_initregs),
484         .platform_init_video    = NULL,
485 #ifdef CONFIG_PM
486         .platform_suspend_video = NULL,
487         .platform_resume_video  = NULL,
488 #endif
489 };
490
491 static struct resource s1d13xxxfb_resources[] = {
492         [0] = {
493                 .start  = 0x10600000UL,
494                 .end    = 0x1073FFFFUL,
495                 .flags  = IORESOURCE_MEM,
496         },
497         [1] = {
498                 .start  = 0x10400000UL,
499                 .end    = 0x104001FFUL,
500                 .flags  = IORESOURCE_MEM,
501         }
502 };
503
504 static struct platform_device s1d13xxxfb_device = {
505         .name           = S1D_DEVICENAME,
506         .id             = 0,
507         .dev            = {
508                 .platform_data  = &s1d13xxxfb_data,
509         },
510         .num_resources  = ARRAY_SIZE(s1d13xxxfb_resources),
511         .resource       = s1d13xxxfb_resources,
512 };
513 #endif
514
515 static int __init platform_init(void)
516 {
517 #if defined(CONFIG_SMC91X)
518         platform_device_register(&smc91x_device);
519 #endif
520 #if defined(CONFIG_FB_S1D13XXX)
521         platform_device_register(&s1d13xxxfb_device);
522 #endif
523         return 0;
524 }
525 arch_initcall(platform_init);