powerpc: Fix some compile problems with the VDSO stuff
[linux-2.6.git] / arch / m32r / boot / setup.S
1 /*
2  *  linux/arch/m32r/boot/setup.S -- A setup code.
3  *
4  *  Copyright (C) 2001, 2002  Hiroyuki Kondo, Hirokazu Takata,
5  *  and Hitoshi Yamamoto
6  *
7  */
8 /* $Id$ */
9
10 #include <linux/linkage.h>
11 #include <asm/segment.h>
12 #include <asm/page.h>
13 #include <asm/pgtable.h>
14
15 #include <linux/config.h>
16 #include <asm/assembler.h>
17 #include <asm/mmu_context.h>
18 #include <asm/m32r.h>
19
20 /*
21  * References to members of the boot_cpu_data structure.
22  */
23
24 #define CPU_PARAMS      boot_cpu_data
25 #define M32R_MCICAR      0xfffffff0
26 #define M32R_MCDCAR      0xfffffff4
27 #define M32R_MCCR        0xfffffffc
28 #define M32R_BSCR0       0xffffffd2
29
30 ;BSEL
31 #define BSEL0CR0         0x00ef5000
32 #define BSEL0CR1         0x00ef5004
33 #define BSEL1CR0         0x00ef5100
34 #define BSEL1CR1         0x00ef5104
35 #define BSEL0CR0_VAL     0x00000000
36 #define BSEL0CR1_VAL     0x01200100
37 #define BSEL1CR0_VAL     0x01018000
38 #define BSEL1CR1_VAL     0x00200001
39
40 ;SDRAMC
41 #define SDRAMC_SDRF0     0x00ef6000
42 #define SDRAMC_SDRF1     0x00ef6004
43 #define SDRAMC_SDIR0     0x00ef6008
44 #define SDRAMC_SDIR1     0x00ef600c
45 #define SDRAMC_SD0ADR    0x00ef6020
46 #define SDRAMC_SD0ER     0x00ef6024
47 #define SDRAMC_SD0TR     0x00ef6028
48 #define SDRAMC_SD0MOD    0x00ef602c
49 #define SDRAMC_SD1ADR    0x00ef6040
50 #define SDRAMC_SD1ER     0x00ef6044
51 #define SDRAMC_SD1TR     0x00ef6048
52 #define SDRAMC_SD1MOD    0x00ef604c
53 #define SDRAM0           0x18000000
54 #define SDRAM1           0x1c000000
55
56 /*------------------------------------------------------------------------
57  * start up
58  */
59
60 /*------------------------------------------------------------------------
61  * Kernel entry
62  */
63         .section .boot, "ax"
64 ENTRY(boot)
65
66 /* Set cache mode */
67 #if defined(CONFIG_CHIP_XNUX2)
68         ldi     r0, #-2              ;LDIMM     (r0, M32R_MCCR)
69         ldi     r1, #0x0101             ; cache on (with invalidation)
70 ;       ldi     r1, #0x00               ; cache off
71         sth     r1, @r0
72 #elif defined(CONFIG_CHIP_M32700) || defined(CONFIG_CHIP_VDEC2) \
73     || defined(CONFIG_CHIP_OPSP)
74         ldi     r0, #-4              ;LDIMM     (r0, M32R_MCCR)
75         ldi     r1, #0x73               ; cache on (with invalidation)
76 ;       ldi     r1, #0x00               ; cache off
77         st      r1, @r0
78 #elif defined(CONFIG_CHIP_M32102)
79         ldi     r0, #-4              ;LDIMM     (r0, M32R_MCCR)
80         ldi     r1, #0x101              ; cache on (with invalidation)
81 ;       ldi     r1, #0x00               ; cache off
82         st      r1, @r0
83 #else
84 #error unknown chip configuration
85 #endif
86
87 #ifdef CONFIG_SMP
88         ;; if not BSP (CPU#0) goto AP_loop
89         seth    r5, #shigh(M32R_CPUID_PORTL)
90         ld      r5, @(low(M32R_CPUID_PORTL), r5)
91         bnez    r5, AP_loop
92 #if !defined(CONFIG_PLAT_USRV)
93         ;; boot AP
94         ld24    r5, #0xeff2f8           ; IPICR7
95         ldi     r6, #0x2                ; IPI to CPU1
96         st      r6, @r5
97 #endif
98 #endif
99
100 /*
101  *  Now, Jump to stext
102  *        if with MMU,    TLB on.
103  *        if with no MMU, only jump.
104  */
105         .global eit_vector
106 mmu_on:
107         LDIMM   (r13, stext)
108 #ifdef CONFIG_MMU
109         bl      init_tlb
110         LDIMM   (r2, eit_vector)                ; set EVB(cr5)
111         mvtc    r2, cr5
112         seth    r0, #high(MMU_REG_BASE)         ; Set MMU_REG_BASE higher
113         or3     r0, r0, #low(MMU_REG_BASE)      ; Set MMU_REG_BASE lower
114         ldi     r1, #0x01
115         st      r1, @(MATM_offset,r0)           ; Set MATM (T bit ON)
116         ld      r0, @(MATM_offset,r0)           ; Check
117 #else
118         seth    r0,#high(M32R_MCDCAR)
119         or3     r0,r0,#low(M32R_MCDCAR)
120         ld24    r1,#0x8080
121         st      r1,@r0
122 #endif  /* CONFIG_MMU */
123         jmp     r13
124         nop
125         nop
126
127 #ifdef CONFIG_SMP
128 /*
129  * AP wait loop
130  */
131 ENTRY(AP_loop)
132         ;; disable interrupt
133         clrpsw  #0x40
134         ;; reset EVB
135         LDIMM   (r4, _AP_RE)
136         seth    r5, #high(__PAGE_OFFSET)
137         or3     r5, r5, #low(__PAGE_OFFSET)
138         not     r5, r5
139         and     r4, r5
140         mvtc    r4, cr5
141         ;; disable maskable interrupt
142         seth    r4, #high(M32R_ICU_IMASK_PORTL)
143         or3     r4, r4, #low(M32R_ICU_IMASK_PORTL)
144         ldi     r5, #0
145         st      r5, @r4
146         ld      r5, @r4
147         ;; enable only IPI
148         setpsw  #0x40
149         ;; LOOOOOOOOOOOOOOP!!!
150         .fillinsn
151 2:
152         nop
153         nop
154         bra     2b
155         nop
156         nop
157
158 #ifdef CONFIG_CHIP_M32700_TS1
159         .global dcache_dummy
160         .balign 16, 0
161 dcache_dummy:
162         .byte   16
163 #endif  /* CONFIG_CHIP_M32700_TS1 */
164 #endif  /* CONFIG_SMP */
165
166         .end
167