f6d8a010d99beacb04dc2d3a9cf8af2e14237a3e
[linux-2.6.git] / arch / ia64 / kernel / minstate.h
1 #include <linux/config.h>
2
3 #include <asm/cache.h>
4
5 #include "entry.h"
6
7 /*
8  * For ivt.s we want to access the stack virtually so we don't have to disable translation
9  * on interrupts.
10  *
11  *  On entry:
12  *      r1:     pointer to current task (ar.k6)
13  */
14 #define MINSTATE_START_SAVE_MIN_VIRT                                                            \
15 (pUStk) mov ar.rsc=0;           /* set enforced lazy mode, pl 0, little-endian, loadrs=0 */     \
16         ;;                                                                                      \
17 (pUStk) mov.m r24=ar.rnat;                                                                      \
18 (pUStk) addl r22=IA64_RBS_OFFSET,r1;                    /* compute base of RBS */               \
19 (pKStk) mov r1=sp;                                      /* get sp  */                           \
20         ;;                                                                                      \
21 (pUStk) lfetch.fault.excl.nt1 [r22];                                                            \
22 (pUStk) addl r1=IA64_STK_OFFSET-IA64_PT_REGS_SIZE,r1;   /* compute base of memory stack */      \
23 (pUStk) mov r23=ar.bspstore;                            /* save ar.bspstore */                  \
24         ;;                                                                                      \
25 (pUStk) mov ar.bspstore=r22;                            /* switch to kernel RBS */              \
26 (pKStk) addl r1=-IA64_PT_REGS_SIZE,r1;                  /* if in kernel mode, use sp (r12) */   \
27         ;;                                                                                      \
28 (pUStk) mov r18=ar.bsp;                                                                         \
29 (pUStk) mov ar.rsc=0x3;         /* set eager mode, pl 0, little-endian, loadrs=0 */
30
31 #define MINSTATE_END_SAVE_MIN_VIRT                                                              \
32         bsw.1;                  /* switch back to bank 1 (must be last in insn group) */        \
33         ;;
34
35 /*
36  * For mca_asm.S we want to access the stack physically since the state is saved before we
37  * go virtual and don't want to destroy the iip or ipsr.
38  */
39 #define MINSTATE_START_SAVE_MIN_PHYS                                                            \
40 (pKStk) mov r3=IA64_KR(PER_CPU_DATA);;                                                          \
41 (pKStk) addl r3=THIS_CPU(ia64_mca_data),r3;;                                                    \
42 (pKStk) ld8 r3 = [r3];;                                                                         \
43 (pKStk) addl r3=IA64_MCA_CPU_INIT_STACK_OFFSET,r3;;                                             \
44 (pKStk) addl r1=IA64_STK_OFFSET-IA64_PT_REGS_SIZE,r3;                                           \
45 (pUStk) mov ar.rsc=0;           /* set enforced lazy mode, pl 0, little-endian, loadrs=0 */     \
46 (pUStk) addl r22=IA64_RBS_OFFSET,r1;            /* compute base of register backing store */    \
47         ;;                                                                                      \
48 (pUStk) mov r24=ar.rnat;                                                                        \
49 (pUStk) addl r1=IA64_STK_OFFSET-IA64_PT_REGS_SIZE,r1;   /* compute base of memory stack */      \
50 (pUStk) mov r23=ar.bspstore;                            /* save ar.bspstore */                  \
51 (pUStk) dep r22=-1,r22,61,3;                    /* compute kernel virtual addr of RBS */        \
52         ;;                                                                                      \
53 (pUStk) mov ar.bspstore=r22;                    /* switch to kernel RBS */                      \
54         ;;                                                                                      \
55 (pUStk) mov r18=ar.bsp;                                                                         \
56 (pUStk) mov ar.rsc=0x3;         /* set eager mode, pl 0, little-endian, loadrs=0 */             \
57
58 #define MINSTATE_END_SAVE_MIN_PHYS                                                              \
59         dep r12=-1,r12,61,3;            /* make sp a kernel virtual address */                  \
60         ;;
61
62 #ifdef MINSTATE_VIRT
63 # define MINSTATE_GET_CURRENT(reg)      mov reg=IA64_KR(CURRENT)
64 # define MINSTATE_START_SAVE_MIN        MINSTATE_START_SAVE_MIN_VIRT
65 # define MINSTATE_END_SAVE_MIN          MINSTATE_END_SAVE_MIN_VIRT
66 #endif
67
68 #ifdef MINSTATE_PHYS
69 # define MINSTATE_GET_CURRENT(reg)      mov reg=IA64_KR(CURRENT);; tpa reg=reg
70 # define MINSTATE_START_SAVE_MIN        MINSTATE_START_SAVE_MIN_PHYS
71 # define MINSTATE_END_SAVE_MIN          MINSTATE_END_SAVE_MIN_PHYS
72 #endif
73
74 /*
75  * DO_SAVE_MIN switches to the kernel stacks (if necessary) and saves
76  * the minimum state necessary that allows us to turn psr.ic back
77  * on.
78  *
79  * Assumed state upon entry:
80  *      psr.ic: off
81  *      r31:    contains saved predicates (pr)
82  *
83  * Upon exit, the state is as follows:
84  *      psr.ic: off
85  *       r2 = points to &pt_regs.r16
86  *       r8 = contents of ar.ccv
87  *       r9 = contents of ar.csd
88  *      r10 = contents of ar.ssd
89  *      r11 = FPSR_DEFAULT
90  *      r12 = kernel sp (kernel virtual address)
91  *      r13 = points to current task_struct (kernel virtual address)
92  *      p15 = TRUE if psr.i is set in cr.ipsr
93  *      predicate registers (other than p2, p3, and p15), b6, r3, r14, r15:
94  *              preserved
95  *
96  * Note that psr.ic is NOT turned on by this macro.  This is so that
97  * we can pass interruption state as arguments to a handler.
98  */
99 #define DO_SAVE_MIN(COVER,SAVE_IFS,EXTRA)                                                       \
100         MINSTATE_GET_CURRENT(r16);      /* M (or M;;I) */                                       \
101         mov r27=ar.rsc;                 /* M */                                                 \
102         mov r20=r1;                     /* A */                                                 \
103         mov r25=ar.unat;                /* M */                                                 \
104         mov r29=cr.ipsr;                /* M */                                                 \
105         mov r26=ar.pfs;                 /* I */                                                 \
106         mov r28=cr.iip;                 /* M */                                                 \
107         mov r21=ar.fpsr;                /* M */                                                 \
108         COVER;                          /* B;; (or nothing) */                                  \
109         ;;                                                                                      \
110         adds r16=IA64_TASK_THREAD_ON_USTACK_OFFSET,r16;                                         \
111         ;;                                                                                      \
112         ld1 r17=[r16];                          /* load current->thread.on_ustack flag */       \
113         st1 [r16]=r0;                           /* clear current->thread.on_ustack flag */      \
114         adds r1=-IA64_TASK_THREAD_ON_USTACK_OFFSET,r16                                          \
115         /* switch from user to kernel RBS: */                                                   \
116         ;;                                                                                      \
117         invala;                         /* M */                                                 \
118         SAVE_IFS;                                                                               \
119         cmp.eq pKStk,pUStk=r0,r17;              /* are we in kernel mode already? */            \
120         ;;                                                                                      \
121         MINSTATE_START_SAVE_MIN                                                                 \
122         adds r17=2*L1_CACHE_BYTES,r1;           /* really: biggest cache-line size */           \
123         adds r16=PT(CR_IPSR),r1;                                                                \
124         ;;                                                                                      \
125         lfetch.fault.excl.nt1 [r17],L1_CACHE_BYTES;                                             \
126         st8 [r16]=r29;          /* save cr.ipsr */                                              \
127         ;;                                                                                      \
128         lfetch.fault.excl.nt1 [r17];                                                            \
129         tbit.nz p15,p0=r29,IA64_PSR_I_BIT;                                                      \
130         mov r29=b0                                                                              \
131         ;;                                                                                      \
132         adds r16=PT(R8),r1;     /* initialize first base pointer */                             \
133         adds r17=PT(R9),r1;     /* initialize second base pointer */                            \
134 (pKStk) mov r18=r0;             /* make sure r18 isn't NaT */                                   \
135         ;;                                                                                      \
136 .mem.offset 0,0; st8.spill [r16]=r8,16;                                                         \
137 .mem.offset 8,0; st8.spill [r17]=r9,16;                                                         \
138         ;;                                                                                      \
139 .mem.offset 0,0; st8.spill [r16]=r10,24;                                                        \
140 .mem.offset 8,0; st8.spill [r17]=r11,24;                                                        \
141         ;;                                                                                      \
142         st8 [r16]=r28,16;       /* save cr.iip */                                               \
143         st8 [r17]=r30,16;       /* save cr.ifs */                                               \
144 (pUStk) sub r18=r18,r22;        /* r18=RSE.ndirty*8 */                                          \
145         mov r8=ar.ccv;                                                                          \
146         mov r9=ar.csd;                                                                          \
147         mov r10=ar.ssd;                                                                         \
148         movl r11=FPSR_DEFAULT;   /* L-unit */                                                   \
149         ;;                                                                                      \
150         st8 [r16]=r25,16;       /* save ar.unat */                                              \
151         st8 [r17]=r26,16;       /* save ar.pfs */                                               \
152         shl r18=r18,16;         /* compute ar.rsc to be used for "loadrs" */                    \
153         ;;                                                                                      \
154         st8 [r16]=r27,16;       /* save ar.rsc */                                               \
155 (pUStk) st8 [r17]=r24,16;       /* save ar.rnat */                                              \
156 (pKStk) adds r17=16,r17;        /* skip over ar_rnat field */                                   \
157         ;;                      /* avoid RAW on r16 & r17 */                                    \
158 (pUStk) st8 [r16]=r23,16;       /* save ar.bspstore */                                          \
159         st8 [r17]=r31,16;       /* save predicates */                                           \
160 (pKStk) adds r16=16,r16;        /* skip over ar_bspstore field */                               \
161         ;;                                                                                      \
162         st8 [r16]=r29,16;       /* save b0 */                                                   \
163         st8 [r17]=r18,16;       /* save ar.rsc value for "loadrs" */                            \
164         cmp.eq pNonSys,pSys=r0,r0       /* initialize pSys=0, pNonSys=1 */                      \
165         ;;                                                                                      \
166 .mem.offset 0,0; st8.spill [r16]=r20,16;        /* save original r1 */                          \
167 .mem.offset 8,0; st8.spill [r17]=r12,16;                                                        \
168         adds r12=-16,r1;        /* switch to kernel memory stack (with 16 bytes of scratch) */  \
169         ;;                                                                                      \
170 .mem.offset 0,0; st8.spill [r16]=r13,16;                                                        \
171 .mem.offset 8,0; st8.spill [r17]=r21,16;        /* save ar.fpsr */                              \
172         mov r13=IA64_KR(CURRENT);       /* establish `current' */                               \
173         ;;                                                                                      \
174 .mem.offset 0,0; st8.spill [r16]=r15,16;                                                        \
175 .mem.offset 8,0; st8.spill [r17]=r14,16;                                                        \
176         ;;                                                                                      \
177 .mem.offset 0,0; st8.spill [r16]=r2,16;                                                         \
178 .mem.offset 8,0; st8.spill [r17]=r3,16;                                                         \
179         adds r2=IA64_PT_REGS_R16_OFFSET,r1;                                                     \
180         ;;                                                                                      \
181         EXTRA;                                                                                  \
182         movl r1=__gp;           /* establish kernel global pointer */                           \
183         ;;                                                                                      \
184         MINSTATE_END_SAVE_MIN
185
186 /*
187  * SAVE_REST saves the remainder of pt_regs (with psr.ic on).
188  *
189  * Assumed state upon entry:
190  *      psr.ic: on
191  *      r2:     points to &pt_regs.r16
192  *      r3:     points to &pt_regs.r17
193  *      r8:     contents of ar.ccv
194  *      r9:     contents of ar.csd
195  *      r10:    contents of ar.ssd
196  *      r11:    FPSR_DEFAULT
197  *
198  * Registers r14 and r15 are guaranteed not to be touched by SAVE_REST.
199  */
200 #define SAVE_REST                               \
201 .mem.offset 0,0; st8.spill [r2]=r16,16;         \
202 .mem.offset 8,0; st8.spill [r3]=r17,16;         \
203         ;;                                      \
204 .mem.offset 0,0; st8.spill [r2]=r18,16;         \
205 .mem.offset 8,0; st8.spill [r3]=r19,16;         \
206         ;;                                      \
207 .mem.offset 0,0; st8.spill [r2]=r20,16;         \
208 .mem.offset 8,0; st8.spill [r3]=r21,16;         \
209         mov r18=b6;                             \
210         ;;                                      \
211 .mem.offset 0,0; st8.spill [r2]=r22,16;         \
212 .mem.offset 8,0; st8.spill [r3]=r23,16;         \
213         mov r19=b7;                             \
214         ;;                                      \
215 .mem.offset 0,0; st8.spill [r2]=r24,16;         \
216 .mem.offset 8,0; st8.spill [r3]=r25,16;         \
217         ;;                                      \
218 .mem.offset 0,0; st8.spill [r2]=r26,16;         \
219 .mem.offset 8,0; st8.spill [r3]=r27,16;         \
220         ;;                                      \
221 .mem.offset 0,0; st8.spill [r2]=r28,16;         \
222 .mem.offset 8,0; st8.spill [r3]=r29,16;         \
223         ;;                                      \
224 .mem.offset 0,0; st8.spill [r2]=r30,16;         \
225 .mem.offset 8,0; st8.spill [r3]=r31,32;         \
226         ;;                                      \
227         mov ar.fpsr=r11;        /* M-unit */    \
228         st8 [r2]=r8,8;          /* ar.ccv */    \
229         adds r24=PT(B6)-PT(F7),r3;              \
230         ;;                                      \
231         stf.spill [r2]=f6,32;                   \
232         stf.spill [r3]=f7,32;                   \
233         ;;                                      \
234         stf.spill [r2]=f8,32;                   \
235         stf.spill [r3]=f9,32;                   \
236         ;;                                      \
237         stf.spill [r2]=f10;                     \
238         stf.spill [r3]=f11;                     \
239         adds r25=PT(B7)-PT(F11),r3;             \
240         ;;                                      \
241         st8 [r24]=r18,16;       /* b6 */        \
242         st8 [r25]=r19,16;       /* b7 */        \
243         ;;                                      \
244         st8 [r24]=r9;           /* ar.csd */    \
245         st8 [r25]=r10;          /* ar.ssd */    \
246         ;;
247
248 #define SAVE_MIN_WITH_COVER     DO_SAVE_MIN(cover, mov r30=cr.ifs,)
249 #define SAVE_MIN_WITH_COVER_R19 DO_SAVE_MIN(cover, mov r30=cr.ifs, mov r15=r19)
250 #define SAVE_MIN                DO_SAVE_MIN(     , mov r30=r0, )