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[linux-2.6.git] / arch / i386 / kernel / io_apic.c
1 /*
2  *      Intel IO-APIC support for multi-Pentium hosts.
3  *
4  *      Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5  *
6  *      Many thanks to Stig Venaas for trying out countless experimental
7  *      patches and reporting/debugging problems patiently!
8  *
9  *      (c) 1999, Multiple IO-APIC support, developed by
10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
13  *      and Ingo Molnar <mingo@redhat.com>
14  *
15  *      Fixes
16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
17  *                                      thanks to Eric Gilmore
18  *                                      and Rolf G. Tews
19  *                                      for testing these extensively
20  *      Paul Diefenbaugh        :       Added full ACPI support
21  */
22
23 #include <linux/mm.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/config.h>
29 #include <linux/smp_lock.h>
30 #include <linux/mc146818rtc.h>
31 #include <linux/compiler.h>
32 #include <linux/acpi.h>
33 #include <linux/module.h>
34 #include <linux/sysdev.h>
35
36 #include <asm/io.h>
37 #include <asm/smp.h>
38 #include <asm/desc.h>
39 #include <asm/timer.h>
40 #include <asm/i8259.h>
41
42 #include <mach_apic.h>
43
44 #include "io_ports.h"
45
46 int (*ioapic_renumber_irq)(int ioapic, int irq);
47 atomic_t irq_mis_count;
48
49 /* Where if anywhere is the i8259 connect in external int mode */
50 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
51
52 static DEFINE_SPINLOCK(ioapic_lock);
53
54 int timer_over_8254 __initdata = 1;
55
56 /*
57  *      Is the SiS APIC rmw bug present ?
58  *      -1 = don't know, 0 = no, 1 = yes
59  */
60 int sis_apic_bug = -1;
61
62 /*
63  * # of IRQ routing registers
64  */
65 int nr_ioapic_registers[MAX_IO_APICS];
66
67 int disable_timer_pin_1 __initdata;
68
69 /*
70  * Rough estimation of how many shared IRQs there are, can
71  * be changed anytime.
72  */
73 #define MAX_PLUS_SHARED_IRQS NR_IRQS
74 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
75
76 /*
77  * This is performance-critical, we want to do it O(1)
78  *
79  * the indexing order of this array favors 1:1 mappings
80  * between pins and IRQs.
81  */
82
83 static struct irq_pin_list {
84         int apic, pin, next;
85 } irq_2_pin[PIN_MAP_SIZE];
86
87 int vector_irq[NR_VECTORS] __read_mostly = { [0 ... NR_VECTORS - 1] = -1};
88 #ifdef CONFIG_PCI_MSI
89 #define vector_to_irq(vector)   \
90         (platform_legacy_irq(vector) ? vector : vector_irq[vector])
91 #else
92 #define vector_to_irq(vector)   (vector)
93 #endif
94
95 /*
96  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
97  * shared ISA-space IRQs, so we have to support them. We are super
98  * fast in the common case, and fast for shared ISA-space IRQs.
99  */
100 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
101 {
102         static int first_free_entry = NR_IRQS;
103         struct irq_pin_list *entry = irq_2_pin + irq;
104
105         while (entry->next)
106                 entry = irq_2_pin + entry->next;
107
108         if (entry->pin != -1) {
109                 entry->next = first_free_entry;
110                 entry = irq_2_pin + entry->next;
111                 if (++first_free_entry >= PIN_MAP_SIZE)
112                         panic("io_apic.c: whoops");
113         }
114         entry->apic = apic;
115         entry->pin = pin;
116 }
117
118 /*
119  * Reroute an IRQ to a different pin.
120  */
121 static void __init replace_pin_at_irq(unsigned int irq,
122                                       int oldapic, int oldpin,
123                                       int newapic, int newpin)
124 {
125         struct irq_pin_list *entry = irq_2_pin + irq;
126
127         while (1) {
128                 if (entry->apic == oldapic && entry->pin == oldpin) {
129                         entry->apic = newapic;
130                         entry->pin = newpin;
131                 }
132                 if (!entry->next)
133                         break;
134                 entry = irq_2_pin + entry->next;
135         }
136 }
137
138 static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable)
139 {
140         struct irq_pin_list *entry = irq_2_pin + irq;
141         unsigned int pin, reg;
142
143         for (;;) {
144                 pin = entry->pin;
145                 if (pin == -1)
146                         break;
147                 reg = io_apic_read(entry->apic, 0x10 + pin*2);
148                 reg &= ~disable;
149                 reg |= enable;
150                 io_apic_modify(entry->apic, 0x10 + pin*2, reg);
151                 if (!entry->next)
152                         break;
153                 entry = irq_2_pin + entry->next;
154         }
155 }
156
157 /* mask = 1 */
158 static void __mask_IO_APIC_irq (unsigned int irq)
159 {
160         __modify_IO_APIC_irq(irq, 0x00010000, 0);
161 }
162
163 /* mask = 0 */
164 static void __unmask_IO_APIC_irq (unsigned int irq)
165 {
166         __modify_IO_APIC_irq(irq, 0, 0x00010000);
167 }
168
169 /* mask = 1, trigger = 0 */
170 static void __mask_and_edge_IO_APIC_irq (unsigned int irq)
171 {
172         __modify_IO_APIC_irq(irq, 0x00010000, 0x00008000);
173 }
174
175 /* mask = 0, trigger = 1 */
176 static void __unmask_and_level_IO_APIC_irq (unsigned int irq)
177 {
178         __modify_IO_APIC_irq(irq, 0x00008000, 0x00010000);
179 }
180
181 static void mask_IO_APIC_irq (unsigned int irq)
182 {
183         unsigned long flags;
184
185         spin_lock_irqsave(&ioapic_lock, flags);
186         __mask_IO_APIC_irq(irq);
187         spin_unlock_irqrestore(&ioapic_lock, flags);
188 }
189
190 static void unmask_IO_APIC_irq (unsigned int irq)
191 {
192         unsigned long flags;
193
194         spin_lock_irqsave(&ioapic_lock, flags);
195         __unmask_IO_APIC_irq(irq);
196         spin_unlock_irqrestore(&ioapic_lock, flags);
197 }
198
199 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
200 {
201         struct IO_APIC_route_entry entry;
202         unsigned long flags;
203         
204         /* Check delivery_mode to be sure we're not clearing an SMI pin */
205         spin_lock_irqsave(&ioapic_lock, flags);
206         *(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
207         *(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
208         spin_unlock_irqrestore(&ioapic_lock, flags);
209         if (entry.delivery_mode == dest_SMI)
210                 return;
211
212         /*
213          * Disable it in the IO-APIC irq-routing table:
214          */
215         memset(&entry, 0, sizeof(entry));
216         entry.mask = 1;
217         spin_lock_irqsave(&ioapic_lock, flags);
218         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
219         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
220         spin_unlock_irqrestore(&ioapic_lock, flags);
221 }
222
223 static void clear_IO_APIC (void)
224 {
225         int apic, pin;
226
227         for (apic = 0; apic < nr_ioapics; apic++)
228                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
229                         clear_IO_APIC_pin(apic, pin);
230 }
231
232 #ifdef CONFIG_SMP
233 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
234 {
235         unsigned long flags;
236         int pin;
237         struct irq_pin_list *entry = irq_2_pin + irq;
238         unsigned int apicid_value;
239         cpumask_t tmp;
240         
241         cpus_and(tmp, cpumask, cpu_online_map);
242         if (cpus_empty(tmp))
243                 tmp = TARGET_CPUS;
244
245         cpus_and(cpumask, tmp, CPU_MASK_ALL);
246
247         apicid_value = cpu_mask_to_apicid(cpumask);
248         /* Prepare to do the io_apic_write */
249         apicid_value = apicid_value << 24;
250         spin_lock_irqsave(&ioapic_lock, flags);
251         for (;;) {
252                 pin = entry->pin;
253                 if (pin == -1)
254                         break;
255                 io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
256                 if (!entry->next)
257                         break;
258                 entry = irq_2_pin + entry->next;
259         }
260         set_irq_info(irq, cpumask);
261         spin_unlock_irqrestore(&ioapic_lock, flags);
262 }
263
264 #if defined(CONFIG_IRQBALANCE)
265 # include <asm/processor.h>     /* kernel_thread() */
266 # include <linux/kernel_stat.h> /* kstat */
267 # include <linux/slab.h>                /* kmalloc() */
268 # include <linux/timer.h>       /* time_after() */
269  
270 # ifdef CONFIG_BALANCED_IRQ_DEBUG
271 #  define TDprintk(x...) do { printk("<%ld:%s:%d>: ", jiffies, __FILE__, __LINE__); printk(x); } while (0)
272 #  define Dprintk(x...) do { TDprintk(x); } while (0)
273 # else
274 #  define TDprintk(x...) 
275 #  define Dprintk(x...) 
276 # endif
277
278
279 #define IRQBALANCE_CHECK_ARCH -999
280 static int irqbalance_disabled = IRQBALANCE_CHECK_ARCH;
281 static int physical_balance = 0;
282
283 static struct irq_cpu_info {
284         unsigned long * last_irq;
285         unsigned long * irq_delta;
286         unsigned long irq;
287 } irq_cpu_data[NR_CPUS];
288
289 #define CPU_IRQ(cpu)            (irq_cpu_data[cpu].irq)
290 #define LAST_CPU_IRQ(cpu,irq)   (irq_cpu_data[cpu].last_irq[irq])
291 #define IRQ_DELTA(cpu,irq)      (irq_cpu_data[cpu].irq_delta[irq])
292
293 #define IDLE_ENOUGH(cpu,now) \
294         (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
295
296 #define IRQ_ALLOWED(cpu, allowed_mask)  cpu_isset(cpu, allowed_mask)
297
298 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(cpu_sibling_map[i]))
299
300 #define MAX_BALANCED_IRQ_INTERVAL       (5*HZ)
301 #define MIN_BALANCED_IRQ_INTERVAL       (HZ/2)
302 #define BALANCED_IRQ_MORE_DELTA         (HZ/10)
303 #define BALANCED_IRQ_LESS_DELTA         (HZ)
304
305 static long balanced_irq_interval = MAX_BALANCED_IRQ_INTERVAL;
306
307 static unsigned long move(int curr_cpu, cpumask_t allowed_mask,
308                         unsigned long now, int direction)
309 {
310         int search_idle = 1;
311         int cpu = curr_cpu;
312
313         goto inside;
314
315         do {
316                 if (unlikely(cpu == curr_cpu))
317                         search_idle = 0;
318 inside:
319                 if (direction == 1) {
320                         cpu++;
321                         if (cpu >= NR_CPUS)
322                                 cpu = 0;
323                 } else {
324                         cpu--;
325                         if (cpu == -1)
326                                 cpu = NR_CPUS-1;
327                 }
328         } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu,allowed_mask) ||
329                         (search_idle && !IDLE_ENOUGH(cpu,now)));
330
331         return cpu;
332 }
333
334 static inline void balance_irq(int cpu, int irq)
335 {
336         unsigned long now = jiffies;
337         cpumask_t allowed_mask;
338         unsigned int new_cpu;
339                 
340         if (irqbalance_disabled)
341                 return; 
342
343         cpus_and(allowed_mask, cpu_online_map, irq_affinity[irq]);
344         new_cpu = move(cpu, allowed_mask, now, 1);
345         if (cpu != new_cpu) {
346                 set_pending_irq(irq, cpumask_of_cpu(new_cpu));
347         }
348 }
349
350 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold)
351 {
352         int i, j;
353         Dprintk("Rotating IRQs among CPUs.\n");
354         for (i = 0; i < NR_CPUS; i++) {
355                 for (j = 0; cpu_online(i) && (j < NR_IRQS); j++) {
356                         if (!irq_desc[j].action)
357                                 continue;
358                         /* Is it a significant load ?  */
359                         if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i),j) <
360                                                 useful_load_threshold)
361                                 continue;
362                         balance_irq(i, j);
363                 }
364         }
365         balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
366                 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);       
367         return;
368 }
369
370 static void do_irq_balance(void)
371 {
372         int i, j;
373         unsigned long max_cpu_irq = 0, min_cpu_irq = (~0);
374         unsigned long move_this_load = 0;
375         int max_loaded = 0, min_loaded = 0;
376         int load;
377         unsigned long useful_load_threshold = balanced_irq_interval + 10;
378         int selected_irq;
379         int tmp_loaded, first_attempt = 1;
380         unsigned long tmp_cpu_irq;
381         unsigned long imbalance = 0;
382         cpumask_t allowed_mask, target_cpu_mask, tmp;
383
384         for (i = 0; i < NR_CPUS; i++) {
385                 int package_index;
386                 CPU_IRQ(i) = 0;
387                 if (!cpu_online(i))
388                         continue;
389                 package_index = CPU_TO_PACKAGEINDEX(i);
390                 for (j = 0; j < NR_IRQS; j++) {
391                         unsigned long value_now, delta;
392                         /* Is this an active IRQ? */
393                         if (!irq_desc[j].action)
394                                 continue;
395                         if ( package_index == i )
396                                 IRQ_DELTA(package_index,j) = 0;
397                         /* Determine the total count per processor per IRQ */
398                         value_now = (unsigned long) kstat_cpu(i).irqs[j];
399
400                         /* Determine the activity per processor per IRQ */
401                         delta = value_now - LAST_CPU_IRQ(i,j);
402
403                         /* Update last_cpu_irq[][] for the next time */
404                         LAST_CPU_IRQ(i,j) = value_now;
405
406                         /* Ignore IRQs whose rate is less than the clock */
407                         if (delta < useful_load_threshold)
408                                 continue;
409                         /* update the load for the processor or package total */
410                         IRQ_DELTA(package_index,j) += delta;
411
412                         /* Keep track of the higher numbered sibling as well */
413                         if (i != package_index)
414                                 CPU_IRQ(i) += delta;
415                         /*
416                          * We have sibling A and sibling B in the package
417                          *
418                          * cpu_irq[A] = load for cpu A + load for cpu B
419                          * cpu_irq[B] = load for cpu B
420                          */
421                         CPU_IRQ(package_index) += delta;
422                 }
423         }
424         /* Find the least loaded processor package */
425         for (i = 0; i < NR_CPUS; i++) {
426                 if (!cpu_online(i))
427                         continue;
428                 if (i != CPU_TO_PACKAGEINDEX(i))
429                         continue;
430                 if (min_cpu_irq > CPU_IRQ(i)) {
431                         min_cpu_irq = CPU_IRQ(i);
432                         min_loaded = i;
433                 }
434         }
435         max_cpu_irq = ULONG_MAX;
436
437 tryanothercpu:
438         /* Look for heaviest loaded processor.
439          * We may come back to get the next heaviest loaded processor.
440          * Skip processors with trivial loads.
441          */
442         tmp_cpu_irq = 0;
443         tmp_loaded = -1;
444         for (i = 0; i < NR_CPUS; i++) {
445                 if (!cpu_online(i))
446                         continue;
447                 if (i != CPU_TO_PACKAGEINDEX(i))
448                         continue;
449                 if (max_cpu_irq <= CPU_IRQ(i)) 
450                         continue;
451                 if (tmp_cpu_irq < CPU_IRQ(i)) {
452                         tmp_cpu_irq = CPU_IRQ(i);
453                         tmp_loaded = i;
454                 }
455         }
456
457         if (tmp_loaded == -1) {
458          /* In the case of small number of heavy interrupt sources, 
459           * loading some of the cpus too much. We use Ingo's original 
460           * approach to rotate them around.
461           */
462                 if (!first_attempt && imbalance >= useful_load_threshold) {
463                         rotate_irqs_among_cpus(useful_load_threshold);
464                         return;
465                 }
466                 goto not_worth_the_effort;
467         }
468         
469         first_attempt = 0;              /* heaviest search */
470         max_cpu_irq = tmp_cpu_irq;      /* load */
471         max_loaded = tmp_loaded;        /* processor */
472         imbalance = (max_cpu_irq - min_cpu_irq) / 2;
473         
474         Dprintk("max_loaded cpu = %d\n", max_loaded);
475         Dprintk("min_loaded cpu = %d\n", min_loaded);
476         Dprintk("max_cpu_irq load = %ld\n", max_cpu_irq);
477         Dprintk("min_cpu_irq load = %ld\n", min_cpu_irq);
478         Dprintk("load imbalance = %lu\n", imbalance);
479
480         /* if imbalance is less than approx 10% of max load, then
481          * observe diminishing returns action. - quit
482          */
483         if (imbalance < (max_cpu_irq >> 3)) {
484                 Dprintk("Imbalance too trivial\n");
485                 goto not_worth_the_effort;
486         }
487
488 tryanotherirq:
489         /* if we select an IRQ to move that can't go where we want, then
490          * see if there is another one to try.
491          */
492         move_this_load = 0;
493         selected_irq = -1;
494         for (j = 0; j < NR_IRQS; j++) {
495                 /* Is this an active IRQ? */
496                 if (!irq_desc[j].action)
497                         continue;
498                 if (imbalance <= IRQ_DELTA(max_loaded,j))
499                         continue;
500                 /* Try to find the IRQ that is closest to the imbalance
501                  * without going over.
502                  */
503                 if (move_this_load < IRQ_DELTA(max_loaded,j)) {
504                         move_this_load = IRQ_DELTA(max_loaded,j);
505                         selected_irq = j;
506                 }
507         }
508         if (selected_irq == -1) {
509                 goto tryanothercpu;
510         }
511
512         imbalance = move_this_load;
513         
514         /* For physical_balance case, we accumlated both load
515          * values in the one of the siblings cpu_irq[],
516          * to use the same code for physical and logical processors
517          * as much as possible. 
518          *
519          * NOTE: the cpu_irq[] array holds the sum of the load for
520          * sibling A and sibling B in the slot for the lowest numbered
521          * sibling (A), _AND_ the load for sibling B in the slot for
522          * the higher numbered sibling.
523          *
524          * We seek the least loaded sibling by making the comparison
525          * (A+B)/2 vs B
526          */
527         load = CPU_IRQ(min_loaded) >> 1;
528         for_each_cpu_mask(j, cpu_sibling_map[min_loaded]) {
529                 if (load > CPU_IRQ(j)) {
530                         /* This won't change cpu_sibling_map[min_loaded] */
531                         load = CPU_IRQ(j);
532                         min_loaded = j;
533                 }
534         }
535
536         cpus_and(allowed_mask, cpu_online_map, irq_affinity[selected_irq]);
537         target_cpu_mask = cpumask_of_cpu(min_loaded);
538         cpus_and(tmp, target_cpu_mask, allowed_mask);
539
540         if (!cpus_empty(tmp)) {
541
542                 Dprintk("irq = %d moved to cpu = %d\n",
543                                 selected_irq, min_loaded);
544                 /* mark for change destination */
545                 set_pending_irq(selected_irq, cpumask_of_cpu(min_loaded));
546
547                 /* Since we made a change, come back sooner to 
548                  * check for more variation.
549                  */
550                 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
551                         balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);       
552                 return;
553         }
554         goto tryanotherirq;
555
556 not_worth_the_effort:
557         /*
558          * if we did not find an IRQ to move, then adjust the time interval
559          * upward
560          */
561         balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL,
562                 balanced_irq_interval + BALANCED_IRQ_MORE_DELTA);       
563         Dprintk("IRQ worth rotating not found\n");
564         return;
565 }
566
567 static int balanced_irq(void *unused)
568 {
569         int i;
570         unsigned long prev_balance_time = jiffies;
571         long time_remaining = balanced_irq_interval;
572
573         daemonize("kirqd");
574         
575         /* push everything to CPU 0 to give us a starting point.  */
576         for (i = 0 ; i < NR_IRQS ; i++) {
577                 pending_irq_cpumask[i] = cpumask_of_cpu(0);
578                 set_pending_irq(i, cpumask_of_cpu(0));
579         }
580
581         for ( ; ; ) {
582                 time_remaining = schedule_timeout_interruptible(time_remaining);
583                 try_to_freeze();
584                 if (time_after(jiffies,
585                                 prev_balance_time+balanced_irq_interval)) {
586                         preempt_disable();
587                         do_irq_balance();
588                         prev_balance_time = jiffies;
589                         time_remaining = balanced_irq_interval;
590                         preempt_enable();
591                 }
592         }
593         return 0;
594 }
595
596 static int __init balanced_irq_init(void)
597 {
598         int i;
599         struct cpuinfo_x86 *c;
600         cpumask_t tmp;
601
602         cpus_shift_right(tmp, cpu_online_map, 2);
603         c = &boot_cpu_data;
604         /* When not overwritten by the command line ask subarchitecture. */
605         if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH)
606                 irqbalance_disabled = NO_BALANCE_IRQ;
607         if (irqbalance_disabled)
608                 return 0;
609         
610          /* disable irqbalance completely if there is only one processor online */
611         if (num_online_cpus() < 2) {
612                 irqbalance_disabled = 1;
613                 return 0;
614         }
615         /*
616          * Enable physical balance only if more than 1 physical processor
617          * is present
618          */
619         if (smp_num_siblings > 1 && !cpus_empty(tmp))
620                 physical_balance = 1;
621
622         for (i = 0; i < NR_CPUS; i++) {
623                 if (!cpu_online(i))
624                         continue;
625                 irq_cpu_data[i].irq_delta = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
626                 irq_cpu_data[i].last_irq = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
627                 if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) {
628                         printk(KERN_ERR "balanced_irq_init: out of memory");
629                         goto failed;
630                 }
631                 memset(irq_cpu_data[i].irq_delta,0,sizeof(unsigned long) * NR_IRQS);
632                 memset(irq_cpu_data[i].last_irq,0,sizeof(unsigned long) * NR_IRQS);
633         }
634         
635         printk(KERN_INFO "Starting balanced_irq\n");
636         if (kernel_thread(balanced_irq, NULL, CLONE_KERNEL) >= 0) 
637                 return 0;
638         else 
639                 printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq");
640 failed:
641         for (i = 0; i < NR_CPUS; i++) {
642                 kfree(irq_cpu_data[i].irq_delta);
643                 kfree(irq_cpu_data[i].last_irq);
644         }
645         return 0;
646 }
647
648 int __init irqbalance_disable(char *str)
649 {
650         irqbalance_disabled = 1;
651         return 0;
652 }
653
654 __setup("noirqbalance", irqbalance_disable);
655
656 late_initcall(balanced_irq_init);
657 #endif /* CONFIG_IRQBALANCE */
658 #endif /* CONFIG_SMP */
659
660 #ifndef CONFIG_SMP
661 void fastcall send_IPI_self(int vector)
662 {
663         unsigned int cfg;
664
665         /*
666          * Wait for idle.
667          */
668         apic_wait_icr_idle();
669         cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
670         /*
671          * Send the IPI. The write to APIC_ICR fires this off.
672          */
673         apic_write_around(APIC_ICR, cfg);
674 }
675 #endif /* !CONFIG_SMP */
676
677
678 /*
679  * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
680  * specific CPU-side IRQs.
681  */
682
683 #define MAX_PIRQS 8
684 static int pirq_entries [MAX_PIRQS];
685 static int pirqs_enabled;
686 int skip_ioapic_setup;
687
688 static int __init ioapic_setup(char *str)
689 {
690         skip_ioapic_setup = 1;
691         return 1;
692 }
693
694 __setup("noapic", ioapic_setup);
695
696 static int __init ioapic_pirq_setup(char *str)
697 {
698         int i, max;
699         int ints[MAX_PIRQS+1];
700
701         get_options(str, ARRAY_SIZE(ints), ints);
702
703         for (i = 0; i < MAX_PIRQS; i++)
704                 pirq_entries[i] = -1;
705
706         pirqs_enabled = 1;
707         apic_printk(APIC_VERBOSE, KERN_INFO
708                         "PIRQ redirection, working around broken MP-BIOS.\n");
709         max = MAX_PIRQS;
710         if (ints[0] < MAX_PIRQS)
711                 max = ints[0];
712
713         for (i = 0; i < max; i++) {
714                 apic_printk(APIC_VERBOSE, KERN_DEBUG
715                                 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
716                 /*
717                  * PIRQs are mapped upside down, usually.
718                  */
719                 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
720         }
721         return 1;
722 }
723
724 __setup("pirq=", ioapic_pirq_setup);
725
726 /*
727  * Find the IRQ entry number of a certain pin.
728  */
729 static int find_irq_entry(int apic, int pin, int type)
730 {
731         int i;
732
733         for (i = 0; i < mp_irq_entries; i++)
734                 if (mp_irqs[i].mpc_irqtype == type &&
735                     (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
736                      mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
737                     mp_irqs[i].mpc_dstirq == pin)
738                         return i;
739
740         return -1;
741 }
742
743 /*
744  * Find the pin to which IRQ[irq] (ISA) is connected
745  */
746 static int __init find_isa_irq_pin(int irq, int type)
747 {
748         int i;
749
750         for (i = 0; i < mp_irq_entries; i++) {
751                 int lbus = mp_irqs[i].mpc_srcbus;
752
753                 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
754                      mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
755                      mp_bus_id_to_type[lbus] == MP_BUS_MCA ||
756                      mp_bus_id_to_type[lbus] == MP_BUS_NEC98
757                     ) &&
758                     (mp_irqs[i].mpc_irqtype == type) &&
759                     (mp_irqs[i].mpc_srcbusirq == irq))
760
761                         return mp_irqs[i].mpc_dstirq;
762         }
763         return -1;
764 }
765
766 static int __init find_isa_irq_apic(int irq, int type)
767 {
768         int i;
769
770         for (i = 0; i < mp_irq_entries; i++) {
771                 int lbus = mp_irqs[i].mpc_srcbus;
772
773                 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
774                      mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
775                      mp_bus_id_to_type[lbus] == MP_BUS_MCA ||
776                      mp_bus_id_to_type[lbus] == MP_BUS_NEC98
777                     ) &&
778                     (mp_irqs[i].mpc_irqtype == type) &&
779                     (mp_irqs[i].mpc_srcbusirq == irq))
780                         break;
781         }
782         if (i < mp_irq_entries) {
783                 int apic;
784                 for(apic = 0; apic < nr_ioapics; apic++) {
785                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
786                                 return apic;
787                 }
788         }
789
790         return -1;
791 }
792
793 /*
794  * Find a specific PCI IRQ entry.
795  * Not an __init, possibly needed by modules
796  */
797 static int pin_2_irq(int idx, int apic, int pin);
798
799 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
800 {
801         int apic, i, best_guess = -1;
802
803         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, "
804                 "slot:%d, pin:%d.\n", bus, slot, pin);
805         if (mp_bus_id_to_pci_bus[bus] == -1) {
806                 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
807                 return -1;
808         }
809         for (i = 0; i < mp_irq_entries; i++) {
810                 int lbus = mp_irqs[i].mpc_srcbus;
811
812                 for (apic = 0; apic < nr_ioapics; apic++)
813                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
814                             mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
815                                 break;
816
817                 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
818                     !mp_irqs[i].mpc_irqtype &&
819                     (bus == lbus) &&
820                     (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
821                         int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
822
823                         if (!(apic || IO_APIC_IRQ(irq)))
824                                 continue;
825
826                         if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
827                                 return irq;
828                         /*
829                          * Use the first all-but-pin matching entry as a
830                          * best-guess fuzzy result for broken mptables.
831                          */
832                         if (best_guess < 0)
833                                 best_guess = irq;
834                 }
835         }
836         return best_guess;
837 }
838 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
839
840 /*
841  * This function currently is only a helper for the i386 smp boot process where 
842  * we need to reprogram the ioredtbls to cater for the cpus which have come online
843  * so mask in all cases should simply be TARGET_CPUS
844  */
845 #ifdef CONFIG_SMP
846 void __init setup_ioapic_dest(void)
847 {
848         int pin, ioapic, irq, irq_entry;
849
850         if (skip_ioapic_setup == 1)
851                 return;
852
853         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
854                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
855                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
856                         if (irq_entry == -1)
857                                 continue;
858                         irq = pin_2_irq(irq_entry, ioapic, pin);
859                         set_ioapic_affinity_irq(irq, TARGET_CPUS);
860                 }
861
862         }
863 }
864 #endif
865
866 /*
867  * EISA Edge/Level control register, ELCR
868  */
869 static int EISA_ELCR(unsigned int irq)
870 {
871         if (irq < 16) {
872                 unsigned int port = 0x4d0 + (irq >> 3);
873                 return (inb(port) >> (irq & 7)) & 1;
874         }
875         apic_printk(APIC_VERBOSE, KERN_INFO
876                         "Broken MPtable reports ISA irq %d\n", irq);
877         return 0;
878 }
879
880 /* EISA interrupts are always polarity zero and can be edge or level
881  * trigger depending on the ELCR value.  If an interrupt is listed as
882  * EISA conforming in the MP table, that means its trigger type must
883  * be read in from the ELCR */
884
885 #define default_EISA_trigger(idx)       (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
886 #define default_EISA_polarity(idx)      (0)
887
888 /* ISA interrupts are always polarity zero edge triggered,
889  * when listed as conforming in the MP table. */
890
891 #define default_ISA_trigger(idx)        (0)
892 #define default_ISA_polarity(idx)       (0)
893
894 /* PCI interrupts are always polarity one level triggered,
895  * when listed as conforming in the MP table. */
896
897 #define default_PCI_trigger(idx)        (1)
898 #define default_PCI_polarity(idx)       (1)
899
900 /* MCA interrupts are always polarity zero level triggered,
901  * when listed as conforming in the MP table. */
902
903 #define default_MCA_trigger(idx)        (1)
904 #define default_MCA_polarity(idx)       (0)
905
906 /* NEC98 interrupts are always polarity zero edge triggered,
907  * when listed as conforming in the MP table. */
908
909 #define default_NEC98_trigger(idx)     (0)
910 #define default_NEC98_polarity(idx)    (0)
911
912 static int __init MPBIOS_polarity(int idx)
913 {
914         int bus = mp_irqs[idx].mpc_srcbus;
915         int polarity;
916
917         /*
918          * Determine IRQ line polarity (high active or low active):
919          */
920         switch (mp_irqs[idx].mpc_irqflag & 3)
921         {
922                 case 0: /* conforms, ie. bus-type dependent polarity */
923                 {
924                         switch (mp_bus_id_to_type[bus])
925                         {
926                                 case MP_BUS_ISA: /* ISA pin */
927                                 {
928                                         polarity = default_ISA_polarity(idx);
929                                         break;
930                                 }
931                                 case MP_BUS_EISA: /* EISA pin */
932                                 {
933                                         polarity = default_EISA_polarity(idx);
934                                         break;
935                                 }
936                                 case MP_BUS_PCI: /* PCI pin */
937                                 {
938                                         polarity = default_PCI_polarity(idx);
939                                         break;
940                                 }
941                                 case MP_BUS_MCA: /* MCA pin */
942                                 {
943                                         polarity = default_MCA_polarity(idx);
944                                         break;
945                                 }
946                                 case MP_BUS_NEC98: /* NEC 98 pin */
947                                 {
948                                         polarity = default_NEC98_polarity(idx);
949                                         break;
950                                 }
951                                 default:
952                                 {
953                                         printk(KERN_WARNING "broken BIOS!!\n");
954                                         polarity = 1;
955                                         break;
956                                 }
957                         }
958                         break;
959                 }
960                 case 1: /* high active */
961                 {
962                         polarity = 0;
963                         break;
964                 }
965                 case 2: /* reserved */
966                 {
967                         printk(KERN_WARNING "broken BIOS!!\n");
968                         polarity = 1;
969                         break;
970                 }
971                 case 3: /* low active */
972                 {
973                         polarity = 1;
974                         break;
975                 }
976                 default: /* invalid */
977                 {
978                         printk(KERN_WARNING "broken BIOS!!\n");
979                         polarity = 1;
980                         break;
981                 }
982         }
983         return polarity;
984 }
985
986 static int MPBIOS_trigger(int idx)
987 {
988         int bus = mp_irqs[idx].mpc_srcbus;
989         int trigger;
990
991         /*
992          * Determine IRQ trigger mode (edge or level sensitive):
993          */
994         switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
995         {
996                 case 0: /* conforms, ie. bus-type dependent */
997                 {
998                         switch (mp_bus_id_to_type[bus])
999                         {
1000                                 case MP_BUS_ISA: /* ISA pin */
1001                                 {
1002                                         trigger = default_ISA_trigger(idx);
1003                                         break;
1004                                 }
1005                                 case MP_BUS_EISA: /* EISA pin */
1006                                 {
1007                                         trigger = default_EISA_trigger(idx);
1008                                         break;
1009                                 }
1010                                 case MP_BUS_PCI: /* PCI pin */
1011                                 {
1012                                         trigger = default_PCI_trigger(idx);
1013                                         break;
1014                                 }
1015                                 case MP_BUS_MCA: /* MCA pin */
1016                                 {
1017                                         trigger = default_MCA_trigger(idx);
1018                                         break;
1019                                 }
1020                                 case MP_BUS_NEC98: /* NEC 98 pin */
1021                                 {
1022                                         trigger = default_NEC98_trigger(idx);
1023                                         break;
1024                                 }
1025                                 default:
1026                                 {
1027                                         printk(KERN_WARNING "broken BIOS!!\n");
1028                                         trigger = 1;
1029                                         break;
1030                                 }
1031                         }
1032                         break;
1033                 }
1034                 case 1: /* edge */
1035                 {
1036                         trigger = 0;
1037                         break;
1038                 }
1039                 case 2: /* reserved */
1040                 {
1041                         printk(KERN_WARNING "broken BIOS!!\n");
1042                         trigger = 1;
1043                         break;
1044                 }
1045                 case 3: /* level */
1046                 {
1047                         trigger = 1;
1048                         break;
1049                 }
1050                 default: /* invalid */
1051                 {
1052                         printk(KERN_WARNING "broken BIOS!!\n");
1053                         trigger = 0;
1054                         break;
1055                 }
1056         }
1057         return trigger;
1058 }
1059
1060 static inline int irq_polarity(int idx)
1061 {
1062         return MPBIOS_polarity(idx);
1063 }
1064
1065 static inline int irq_trigger(int idx)
1066 {
1067         return MPBIOS_trigger(idx);
1068 }
1069
1070 static int pin_2_irq(int idx, int apic, int pin)
1071 {
1072         int irq, i;
1073         int bus = mp_irqs[idx].mpc_srcbus;
1074
1075         /*
1076          * Debugging check, we are in big trouble if this message pops up!
1077          */
1078         if (mp_irqs[idx].mpc_dstirq != pin)
1079                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1080
1081         switch (mp_bus_id_to_type[bus])
1082         {
1083                 case MP_BUS_ISA: /* ISA pin */
1084                 case MP_BUS_EISA:
1085                 case MP_BUS_MCA:
1086                 case MP_BUS_NEC98:
1087                 {
1088                         irq = mp_irqs[idx].mpc_srcbusirq;
1089                         break;
1090                 }
1091                 case MP_BUS_PCI: /* PCI pin */
1092                 {
1093                         /*
1094                          * PCI IRQs are mapped in order
1095                          */
1096                         i = irq = 0;
1097                         while (i < apic)
1098                                 irq += nr_ioapic_registers[i++];
1099                         irq += pin;
1100
1101                         /*
1102                          * For MPS mode, so far only needed by ES7000 platform
1103                          */
1104                         if (ioapic_renumber_irq)
1105                                 irq = ioapic_renumber_irq(apic, irq);
1106
1107                         break;
1108                 }
1109                 default:
1110                 {
1111                         printk(KERN_ERR "unknown bus type %d.\n",bus); 
1112                         irq = 0;
1113                         break;
1114                 }
1115         }
1116
1117         /*
1118          * PCI IRQ command line redirection. Yes, limits are hardcoded.
1119          */
1120         if ((pin >= 16) && (pin <= 23)) {
1121                 if (pirq_entries[pin-16] != -1) {
1122                         if (!pirq_entries[pin-16]) {
1123                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1124                                                 "disabling PIRQ%d\n", pin-16);
1125                         } else {
1126                                 irq = pirq_entries[pin-16];
1127                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1128                                                 "using PIRQ%d -> IRQ %d\n",
1129                                                 pin-16, irq);
1130                         }
1131                 }
1132         }
1133         return irq;
1134 }
1135
1136 static inline int IO_APIC_irq_trigger(int irq)
1137 {
1138         int apic, idx, pin;
1139
1140         for (apic = 0; apic < nr_ioapics; apic++) {
1141                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1142                         idx = find_irq_entry(apic,pin,mp_INT);
1143                         if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
1144                                 return irq_trigger(idx);
1145                 }
1146         }
1147         /*
1148          * nonexistent IRQs are edge default
1149          */
1150         return 0;
1151 }
1152
1153 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1154 u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 };
1155
1156 int assign_irq_vector(int irq)
1157 {
1158         static int current_vector = FIRST_DEVICE_VECTOR, offset = 0;
1159
1160         BUG_ON(irq >= NR_IRQ_VECTORS);
1161         if (irq != AUTO_ASSIGN && IO_APIC_VECTOR(irq) > 0)
1162                 return IO_APIC_VECTOR(irq);
1163 next:
1164         current_vector += 8;
1165         if (current_vector == SYSCALL_VECTOR)
1166                 goto next;
1167
1168         if (current_vector >= FIRST_SYSTEM_VECTOR) {
1169                 offset++;
1170                 if (!(offset%8))
1171                         return -ENOSPC;
1172                 current_vector = FIRST_DEVICE_VECTOR + offset;
1173         }
1174
1175         vector_irq[current_vector] = irq;
1176         if (irq != AUTO_ASSIGN)
1177                 IO_APIC_VECTOR(irq) = current_vector;
1178
1179         return current_vector;
1180 }
1181
1182 static struct hw_interrupt_type ioapic_level_type;
1183 static struct hw_interrupt_type ioapic_edge_type;
1184
1185 #define IOAPIC_AUTO     -1
1186 #define IOAPIC_EDGE     0
1187 #define IOAPIC_LEVEL    1
1188
1189 static inline void ioapic_register_intr(int irq, int vector, unsigned long trigger)
1190 {
1191         if (use_pci_vector() && !platform_legacy_irq(irq)) {
1192                 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1193                                 trigger == IOAPIC_LEVEL)
1194                         irq_desc[vector].handler = &ioapic_level_type;
1195                 else
1196                         irq_desc[vector].handler = &ioapic_edge_type;
1197                 set_intr_gate(vector, interrupt[vector]);
1198         } else  {
1199                 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1200                                 trigger == IOAPIC_LEVEL)
1201                         irq_desc[irq].handler = &ioapic_level_type;
1202                 else
1203                         irq_desc[irq].handler = &ioapic_edge_type;
1204                 set_intr_gate(vector, interrupt[irq]);
1205         }
1206 }
1207
1208 static void __init setup_IO_APIC_irqs(void)
1209 {
1210         struct IO_APIC_route_entry entry;
1211         int apic, pin, idx, irq, first_notcon = 1, vector;
1212         unsigned long flags;
1213
1214         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1215
1216         for (apic = 0; apic < nr_ioapics; apic++) {
1217         for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1218
1219                 /*
1220                  * add it to the IO-APIC irq-routing table:
1221                  */
1222                 memset(&entry,0,sizeof(entry));
1223
1224                 entry.delivery_mode = INT_DELIVERY_MODE;
1225                 entry.dest_mode = INT_DEST_MODE;
1226                 entry.mask = 0;                         /* enable IRQ */
1227                 entry.dest.logical.logical_dest = 
1228                                         cpu_mask_to_apicid(TARGET_CPUS);
1229
1230                 idx = find_irq_entry(apic,pin,mp_INT);
1231                 if (idx == -1) {
1232                         if (first_notcon) {
1233                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1234                                                 " IO-APIC (apicid-pin) %d-%d",
1235                                                 mp_ioapics[apic].mpc_apicid,
1236                                                 pin);
1237                                 first_notcon = 0;
1238                         } else
1239                                 apic_printk(APIC_VERBOSE, ", %d-%d",
1240                                         mp_ioapics[apic].mpc_apicid, pin);
1241                         continue;
1242                 }
1243
1244                 entry.trigger = irq_trigger(idx);
1245                 entry.polarity = irq_polarity(idx);
1246
1247                 if (irq_trigger(idx)) {
1248                         entry.trigger = 1;
1249                         entry.mask = 1;
1250                 }
1251
1252                 irq = pin_2_irq(idx, apic, pin);
1253                 /*
1254                  * skip adding the timer int on secondary nodes, which causes
1255                  * a small but painful rift in the time-space continuum
1256                  */
1257                 if (multi_timer_check(apic, irq))
1258                         continue;
1259                 else
1260                         add_pin_to_irq(irq, apic, pin);
1261
1262                 if (!apic && !IO_APIC_IRQ(irq))
1263                         continue;
1264
1265                 if (IO_APIC_IRQ(irq)) {
1266                         vector = assign_irq_vector(irq);
1267                         entry.vector = vector;
1268                         ioapic_register_intr(irq, vector, IOAPIC_AUTO);
1269                 
1270                         if (!apic && (irq < 16))
1271                                 disable_8259A_irq(irq);
1272                 }
1273                 spin_lock_irqsave(&ioapic_lock, flags);
1274                 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
1275                 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
1276                 set_native_irq_info(irq, TARGET_CPUS);
1277                 spin_unlock_irqrestore(&ioapic_lock, flags);
1278         }
1279         }
1280
1281         if (!first_notcon)
1282                 apic_printk(APIC_VERBOSE, " not connected.\n");
1283 }
1284
1285 /*
1286  * Set up the 8259A-master output pin:
1287  */
1288 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
1289 {
1290         struct IO_APIC_route_entry entry;
1291         unsigned long flags;
1292
1293         memset(&entry,0,sizeof(entry));
1294
1295         disable_8259A_irq(0);
1296
1297         /* mask LVT0 */
1298         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1299
1300         /*
1301          * We use logical delivery to get the timer IRQ
1302          * to the first CPU.
1303          */
1304         entry.dest_mode = INT_DEST_MODE;
1305         entry.mask = 0;                                 /* unmask IRQ now */
1306         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1307         entry.delivery_mode = INT_DELIVERY_MODE;
1308         entry.polarity = 0;
1309         entry.trigger = 0;
1310         entry.vector = vector;
1311
1312         /*
1313          * The timer IRQ doesn't have to know that behind the
1314          * scene we have a 8259A-master in AEOI mode ...
1315          */
1316         irq_desc[0].handler = &ioapic_edge_type;
1317
1318         /*
1319          * Add it to the IO-APIC irq-routing table:
1320          */
1321         spin_lock_irqsave(&ioapic_lock, flags);
1322         io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
1323         io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
1324         spin_unlock_irqrestore(&ioapic_lock, flags);
1325
1326         enable_8259A_irq(0);
1327 }
1328
1329 static inline void UNEXPECTED_IO_APIC(void)
1330 {
1331 }
1332
1333 void __init print_IO_APIC(void)
1334 {
1335         int apic, i;
1336         union IO_APIC_reg_00 reg_00;
1337         union IO_APIC_reg_01 reg_01;
1338         union IO_APIC_reg_02 reg_02;
1339         union IO_APIC_reg_03 reg_03;
1340         unsigned long flags;
1341
1342         if (apic_verbosity == APIC_QUIET)
1343                 return;
1344
1345         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1346         for (i = 0; i < nr_ioapics; i++)
1347                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1348                        mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
1349
1350         /*
1351          * We are a bit conservative about what we expect.  We have to
1352          * know about every hardware change ASAP.
1353          */
1354         printk(KERN_INFO "testing the IO APIC.......................\n");
1355
1356         for (apic = 0; apic < nr_ioapics; apic++) {
1357
1358         spin_lock_irqsave(&ioapic_lock, flags);
1359         reg_00.raw = io_apic_read(apic, 0);
1360         reg_01.raw = io_apic_read(apic, 1);
1361         if (reg_01.bits.version >= 0x10)
1362                 reg_02.raw = io_apic_read(apic, 2);
1363         if (reg_01.bits.version >= 0x20)
1364                 reg_03.raw = io_apic_read(apic, 3);
1365         spin_unlock_irqrestore(&ioapic_lock, flags);
1366
1367         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
1368         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1369         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
1370         printk(KERN_DEBUG ".......    : Delivery Type: %X\n", reg_00.bits.delivery_type);
1371         printk(KERN_DEBUG ".......    : LTS          : %X\n", reg_00.bits.LTS);
1372         if (reg_00.bits.ID >= get_physical_broadcast())
1373                 UNEXPECTED_IO_APIC();
1374         if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
1375                 UNEXPECTED_IO_APIC();
1376
1377         printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
1378         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
1379         if (    (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
1380                 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
1381                 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
1382                 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
1383                 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
1384                 (reg_01.bits.entries != 0x2E) &&
1385                 (reg_01.bits.entries != 0x3F)
1386         )
1387                 UNEXPECTED_IO_APIC();
1388
1389         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
1390         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
1391         if (    (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
1392                 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
1393                 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
1394                 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
1395                 (reg_01.bits.version != 0x20)    /* Intel P64H (82806 AA) */
1396         )
1397                 UNEXPECTED_IO_APIC();
1398         if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
1399                 UNEXPECTED_IO_APIC();
1400
1401         /*
1402          * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1403          * but the value of reg_02 is read as the previous read register
1404          * value, so ignore it if reg_02 == reg_01.
1405          */
1406         if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1407                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1408                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
1409                 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
1410                         UNEXPECTED_IO_APIC();
1411         }
1412
1413         /*
1414          * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1415          * or reg_03, but the value of reg_0[23] is read as the previous read
1416          * register value, so ignore it if reg_03 == reg_0[12].
1417          */
1418         if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1419             reg_03.raw != reg_01.raw) {
1420                 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1421                 printk(KERN_DEBUG ".......     : Boot DT    : %X\n", reg_03.bits.boot_DT);
1422                 if (reg_03.bits.__reserved_1)
1423                         UNEXPECTED_IO_APIC();
1424         }
1425
1426         printk(KERN_DEBUG ".... IRQ redirection table:\n");
1427
1428         printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1429                           " Stat Dest Deli Vect:   \n");
1430
1431         for (i = 0; i <= reg_01.bits.entries; i++) {
1432                 struct IO_APIC_route_entry entry;
1433
1434                 spin_lock_irqsave(&ioapic_lock, flags);
1435                 *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2);
1436                 *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2);
1437                 spin_unlock_irqrestore(&ioapic_lock, flags);
1438
1439                 printk(KERN_DEBUG " %02x %03X %02X  ",
1440                         i,
1441                         entry.dest.logical.logical_dest,
1442                         entry.dest.physical.physical_dest
1443                 );
1444
1445                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
1446                         entry.mask,
1447                         entry.trigger,
1448                         entry.irr,
1449                         entry.polarity,
1450                         entry.delivery_status,
1451                         entry.dest_mode,
1452                         entry.delivery_mode,
1453                         entry.vector
1454                 );
1455         }
1456         }
1457         if (use_pci_vector())
1458                 printk(KERN_INFO "Using vector-based indexing\n");
1459         printk(KERN_DEBUG "IRQ to pin mappings:\n");
1460         for (i = 0; i < NR_IRQS; i++) {
1461                 struct irq_pin_list *entry = irq_2_pin + i;
1462                 if (entry->pin < 0)
1463                         continue;
1464                 if (use_pci_vector() && !platform_legacy_irq(i))
1465                         printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i));
1466                 else
1467                         printk(KERN_DEBUG "IRQ%d ", i);
1468                 for (;;) {
1469                         printk("-> %d:%d", entry->apic, entry->pin);
1470                         if (!entry->next)
1471                                 break;
1472                         entry = irq_2_pin + entry->next;
1473                 }
1474                 printk("\n");
1475         }
1476
1477         printk(KERN_INFO ".................................... done.\n");
1478
1479         return;
1480 }
1481
1482 #if 0
1483
1484 static void print_APIC_bitfield (int base)
1485 {
1486         unsigned int v;
1487         int i, j;
1488
1489         if (apic_verbosity == APIC_QUIET)
1490                 return;
1491
1492         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1493         for (i = 0; i < 8; i++) {
1494                 v = apic_read(base + i*0x10);
1495                 for (j = 0; j < 32; j++) {
1496                         if (v & (1<<j))
1497                                 printk("1");
1498                         else
1499                                 printk("0");
1500                 }
1501                 printk("\n");
1502         }
1503 }
1504
1505 void /*__init*/ print_local_APIC(void * dummy)
1506 {
1507         unsigned int v, ver, maxlvt;
1508
1509         if (apic_verbosity == APIC_QUIET)
1510                 return;
1511
1512         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1513                 smp_processor_id(), hard_smp_processor_id());
1514         v = apic_read(APIC_ID);
1515         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, GET_APIC_ID(v));
1516         v = apic_read(APIC_LVR);
1517         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1518         ver = GET_APIC_VERSION(v);
1519         maxlvt = get_maxlvt();
1520
1521         v = apic_read(APIC_TASKPRI);
1522         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1523
1524         if (APIC_INTEGRATED(ver)) {                     /* !82489DX */
1525                 v = apic_read(APIC_ARBPRI);
1526                 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1527                         v & APIC_ARBPRI_MASK);
1528                 v = apic_read(APIC_PROCPRI);
1529                 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1530         }
1531
1532         v = apic_read(APIC_EOI);
1533         printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1534         v = apic_read(APIC_RRR);
1535         printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1536         v = apic_read(APIC_LDR);
1537         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1538         v = apic_read(APIC_DFR);
1539         printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1540         v = apic_read(APIC_SPIV);
1541         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1542
1543         printk(KERN_DEBUG "... APIC ISR field:\n");
1544         print_APIC_bitfield(APIC_ISR);
1545         printk(KERN_DEBUG "... APIC TMR field:\n");
1546         print_APIC_bitfield(APIC_TMR);
1547         printk(KERN_DEBUG "... APIC IRR field:\n");
1548         print_APIC_bitfield(APIC_IRR);
1549
1550         if (APIC_INTEGRATED(ver)) {             /* !82489DX */
1551                 if (maxlvt > 3)         /* Due to the Pentium erratum 3AP. */
1552                         apic_write(APIC_ESR, 0);
1553                 v = apic_read(APIC_ESR);
1554                 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1555         }
1556
1557         v = apic_read(APIC_ICR);
1558         printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1559         v = apic_read(APIC_ICR2);
1560         printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1561
1562         v = apic_read(APIC_LVTT);
1563         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1564
1565         if (maxlvt > 3) {                       /* PC is LVT#4. */
1566                 v = apic_read(APIC_LVTPC);
1567                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1568         }
1569         v = apic_read(APIC_LVT0);
1570         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1571         v = apic_read(APIC_LVT1);
1572         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1573
1574         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1575                 v = apic_read(APIC_LVTERR);
1576                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1577         }
1578
1579         v = apic_read(APIC_TMICT);
1580         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1581         v = apic_read(APIC_TMCCT);
1582         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1583         v = apic_read(APIC_TDCR);
1584         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1585         printk("\n");
1586 }
1587
1588 void print_all_local_APICs (void)
1589 {
1590         on_each_cpu(print_local_APIC, NULL, 1, 1);
1591 }
1592
1593 void /*__init*/ print_PIC(void)
1594 {
1595         unsigned int v;
1596         unsigned long flags;
1597
1598         if (apic_verbosity == APIC_QUIET)
1599                 return;
1600
1601         printk(KERN_DEBUG "\nprinting PIC contents\n");
1602
1603         spin_lock_irqsave(&i8259A_lock, flags);
1604
1605         v = inb(0xa1) << 8 | inb(0x21);
1606         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1607
1608         v = inb(0xa0) << 8 | inb(0x20);
1609         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1610
1611         outb(0x0b,0xa0);
1612         outb(0x0b,0x20);
1613         v = inb(0xa0) << 8 | inb(0x20);
1614         outb(0x0a,0xa0);
1615         outb(0x0a,0x20);
1616
1617         spin_unlock_irqrestore(&i8259A_lock, flags);
1618
1619         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1620
1621         v = inb(0x4d1) << 8 | inb(0x4d0);
1622         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1623 }
1624
1625 #endif  /*  0  */
1626
1627 static void __init enable_IO_APIC(void)
1628 {
1629         union IO_APIC_reg_01 reg_01;
1630         int i8259_apic, i8259_pin;
1631         int i, apic;
1632         unsigned long flags;
1633
1634         for (i = 0; i < PIN_MAP_SIZE; i++) {
1635                 irq_2_pin[i].pin = -1;
1636                 irq_2_pin[i].next = 0;
1637         }
1638         if (!pirqs_enabled)
1639                 for (i = 0; i < MAX_PIRQS; i++)
1640                         pirq_entries[i] = -1;
1641
1642         /*
1643          * The number of IO-APIC IRQ registers (== #pins):
1644          */
1645         for (apic = 0; apic < nr_ioapics; apic++) {
1646                 spin_lock_irqsave(&ioapic_lock, flags);
1647                 reg_01.raw = io_apic_read(apic, 1);
1648                 spin_unlock_irqrestore(&ioapic_lock, flags);
1649                 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1650         }
1651         for(apic = 0; apic < nr_ioapics; apic++) {
1652                 int pin;
1653                 /* See if any of the pins is in ExtINT mode */
1654                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1655                         struct IO_APIC_route_entry entry;
1656                         spin_lock_irqsave(&ioapic_lock, flags);
1657                         *(((int *)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1658                         *(((int *)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1659                         spin_unlock_irqrestore(&ioapic_lock, flags);
1660
1661
1662                         /* If the interrupt line is enabled and in ExtInt mode
1663                          * I have found the pin where the i8259 is connected.
1664                          */
1665                         if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1666                                 ioapic_i8259.apic = apic;
1667                                 ioapic_i8259.pin  = pin;
1668                                 goto found_i8259;
1669                         }
1670                 }
1671         }
1672  found_i8259:
1673         /* Look to see what if the MP table has reported the ExtINT */
1674         /* If we could not find the appropriate pin by looking at the ioapic
1675          * the i8259 probably is not connected the ioapic but give the
1676          * mptable a chance anyway.
1677          */
1678         i8259_pin  = find_isa_irq_pin(0, mp_ExtINT);
1679         i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1680         /* Trust the MP table if nothing is setup in the hardware */
1681         if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1682                 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1683                 ioapic_i8259.pin  = i8259_pin;
1684                 ioapic_i8259.apic = i8259_apic;
1685         }
1686         /* Complain if the MP table and the hardware disagree */
1687         if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1688                 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1689         {
1690                 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1691         }
1692
1693         /*
1694          * Do not trust the IO-APIC being empty at bootup
1695          */
1696         clear_IO_APIC();
1697 }
1698
1699 /*
1700  * Not an __init, needed by the reboot code
1701  */
1702 void disable_IO_APIC(void)
1703 {
1704         /*
1705          * Clear the IO-APIC before rebooting:
1706          */
1707         clear_IO_APIC();
1708
1709         /*
1710          * If the i8259 is routed through an IOAPIC
1711          * Put that IOAPIC in virtual wire mode
1712          * so legacy interrupts can be delivered.
1713          */
1714         if (ioapic_i8259.pin != -1) {
1715                 struct IO_APIC_route_entry entry;
1716                 unsigned long flags;
1717
1718                 memset(&entry, 0, sizeof(entry));
1719                 entry.mask            = 0; /* Enabled */
1720                 entry.trigger         = 0; /* Edge */
1721                 entry.irr             = 0;
1722                 entry.polarity        = 0; /* High */
1723                 entry.delivery_status = 0;
1724                 entry.dest_mode       = 0; /* Physical */
1725                 entry.delivery_mode   = dest_ExtINT; /* ExtInt */
1726                 entry.vector          = 0;
1727                 entry.dest.physical.physical_dest =
1728                                         GET_APIC_ID(apic_read(APIC_ID));
1729
1730                 /*
1731                  * Add it to the IO-APIC irq-routing table:
1732                  */
1733                 spin_lock_irqsave(&ioapic_lock, flags);
1734                 io_apic_write(ioapic_i8259.apic, 0x11+2*ioapic_i8259.pin,
1735                         *(((int *)&entry)+1));
1736                 io_apic_write(ioapic_i8259.apic, 0x10+2*ioapic_i8259.pin,
1737                         *(((int *)&entry)+0));
1738                 spin_unlock_irqrestore(&ioapic_lock, flags);
1739         }
1740         disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1741 }
1742
1743 /*
1744  * function to set the IO-APIC physical IDs based on the
1745  * values stored in the MPC table.
1746  *
1747  * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
1748  */
1749
1750 #ifndef CONFIG_X86_NUMAQ
1751 static void __init setup_ioapic_ids_from_mpc(void)
1752 {
1753         union IO_APIC_reg_00 reg_00;
1754         physid_mask_t phys_id_present_map;
1755         int apic;
1756         int i;
1757         unsigned char old_id;
1758         unsigned long flags;
1759
1760         /*
1761          * Don't check I/O APIC IDs for xAPIC systems.  They have
1762          * no meaning without the serial APIC bus.
1763          */
1764         if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1765                 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
1766                 return;
1767         /*
1768          * This is broken; anything with a real cpu count has to
1769          * circumvent this idiocy regardless.
1770          */
1771         phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1772
1773         /*
1774          * Set the IOAPIC ID to the value stored in the MPC table.
1775          */
1776         for (apic = 0; apic < nr_ioapics; apic++) {
1777
1778                 /* Read the register 0 value */
1779                 spin_lock_irqsave(&ioapic_lock, flags);
1780                 reg_00.raw = io_apic_read(apic, 0);
1781                 spin_unlock_irqrestore(&ioapic_lock, flags);
1782                 
1783                 old_id = mp_ioapics[apic].mpc_apicid;
1784
1785                 if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) {
1786                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1787                                 apic, mp_ioapics[apic].mpc_apicid);
1788                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1789                                 reg_00.bits.ID);
1790                         mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
1791                 }
1792
1793                 /*
1794                  * Sanity check, is the ID really free? Every APIC in a
1795                  * system must have a unique ID or we get lots of nice
1796                  * 'stuck on smp_invalidate_needed IPI wait' messages.
1797                  */
1798                 if (check_apicid_used(phys_id_present_map,
1799                                         mp_ioapics[apic].mpc_apicid)) {
1800                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1801                                 apic, mp_ioapics[apic].mpc_apicid);
1802                         for (i = 0; i < get_physical_broadcast(); i++)
1803                                 if (!physid_isset(i, phys_id_present_map))
1804                                         break;
1805                         if (i >= get_physical_broadcast())
1806                                 panic("Max APIC ID exceeded!\n");
1807                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1808                                 i);
1809                         physid_set(i, phys_id_present_map);
1810                         mp_ioapics[apic].mpc_apicid = i;
1811                 } else {
1812                         physid_mask_t tmp;
1813                         tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid);
1814                         apic_printk(APIC_VERBOSE, "Setting %d in the "
1815                                         "phys_id_present_map\n",
1816                                         mp_ioapics[apic].mpc_apicid);
1817                         physids_or(phys_id_present_map, phys_id_present_map, tmp);
1818                 }
1819
1820
1821                 /*
1822                  * We need to adjust the IRQ routing table
1823                  * if the ID changed.
1824                  */
1825                 if (old_id != mp_ioapics[apic].mpc_apicid)
1826                         for (i = 0; i < mp_irq_entries; i++)
1827                                 if (mp_irqs[i].mpc_dstapic == old_id)
1828                                         mp_irqs[i].mpc_dstapic
1829                                                 = mp_ioapics[apic].mpc_apicid;
1830
1831                 /*
1832                  * Read the right value from the MPC table and
1833                  * write it into the ID register.
1834                  */
1835                 apic_printk(APIC_VERBOSE, KERN_INFO
1836                         "...changing IO-APIC physical APIC ID to %d ...",
1837                         mp_ioapics[apic].mpc_apicid);
1838
1839                 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1840                 spin_lock_irqsave(&ioapic_lock, flags);
1841                 io_apic_write(apic, 0, reg_00.raw);
1842                 spin_unlock_irqrestore(&ioapic_lock, flags);
1843
1844                 /*
1845                  * Sanity check
1846                  */
1847                 spin_lock_irqsave(&ioapic_lock, flags);
1848                 reg_00.raw = io_apic_read(apic, 0);
1849                 spin_unlock_irqrestore(&ioapic_lock, flags);
1850                 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1851                         printk("could not set ID!\n");
1852                 else
1853                         apic_printk(APIC_VERBOSE, " ok.\n");
1854         }
1855 }
1856 #else
1857 static void __init setup_ioapic_ids_from_mpc(void) { }
1858 #endif
1859
1860 /*
1861  * There is a nasty bug in some older SMP boards, their mptable lies
1862  * about the timer IRQ. We do the following to work around the situation:
1863  *
1864  *      - timer IRQ defaults to IO-APIC IRQ
1865  *      - if this function detects that timer IRQs are defunct, then we fall
1866  *        back to ISA timer IRQs
1867  */
1868 static int __init timer_irq_works(void)
1869 {
1870         unsigned long t1 = jiffies;
1871
1872         local_irq_enable();
1873         /* Let ten ticks pass... */
1874         mdelay((10 * 1000) / HZ);
1875
1876         /*
1877          * Expect a few ticks at least, to be sure some possible
1878          * glue logic does not lock up after one or two first
1879          * ticks in a non-ExtINT mode.  Also the local APIC
1880          * might have cached one ExtINT interrupt.  Finally, at
1881          * least one tick may be lost due to delays.
1882          */
1883         if (jiffies - t1 > 4)
1884                 return 1;
1885
1886         return 0;
1887 }
1888
1889 /*
1890  * In the SMP+IOAPIC case it might happen that there are an unspecified
1891  * number of pending IRQ events unhandled. These cases are very rare,
1892  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1893  * better to do it this way as thus we do not have to be aware of
1894  * 'pending' interrupts in the IRQ path, except at this point.
1895  */
1896 /*
1897  * Edge triggered needs to resend any interrupt
1898  * that was delayed but this is now handled in the device
1899  * independent code.
1900  */
1901
1902 /*
1903  * Starting up a edge-triggered IO-APIC interrupt is
1904  * nasty - we need to make sure that we get the edge.
1905  * If it is already asserted for some reason, we need
1906  * return 1 to indicate that is was pending.
1907  *
1908  * This is not complete - we should be able to fake
1909  * an edge even if it isn't on the 8259A...
1910  */
1911 static unsigned int startup_edge_ioapic_irq(unsigned int irq)
1912 {
1913         int was_pending = 0;
1914         unsigned long flags;
1915
1916         spin_lock_irqsave(&ioapic_lock, flags);
1917         if (irq < 16) {
1918                 disable_8259A_irq(irq);
1919                 if (i8259A_irq_pending(irq))
1920                         was_pending = 1;
1921         }
1922         __unmask_IO_APIC_irq(irq);
1923         spin_unlock_irqrestore(&ioapic_lock, flags);
1924
1925         return was_pending;
1926 }
1927
1928 /*
1929  * Once we have recorded IRQ_PENDING already, we can mask the
1930  * interrupt for real. This prevents IRQ storms from unhandled
1931  * devices.
1932  */
1933 static void ack_edge_ioapic_irq(unsigned int irq)
1934 {
1935         move_irq(irq);
1936         if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
1937                                         == (IRQ_PENDING | IRQ_DISABLED))
1938                 mask_IO_APIC_irq(irq);
1939         ack_APIC_irq();
1940 }
1941
1942 /*
1943  * Level triggered interrupts can just be masked,
1944  * and shutting down and starting up the interrupt
1945  * is the same as enabling and disabling them -- except
1946  * with a startup need to return a "was pending" value.
1947  *
1948  * Level triggered interrupts are special because we
1949  * do not touch any IO-APIC register while handling
1950  * them. We ack the APIC in the end-IRQ handler, not
1951  * in the start-IRQ-handler. Protection against reentrance
1952  * from the same interrupt is still provided, both by the
1953  * generic IRQ layer and by the fact that an unacked local
1954  * APIC does not accept IRQs.
1955  */
1956 static unsigned int startup_level_ioapic_irq (unsigned int irq)
1957 {
1958         unmask_IO_APIC_irq(irq);
1959
1960         return 0; /* don't check for pending */
1961 }
1962
1963 static void end_level_ioapic_irq (unsigned int irq)
1964 {
1965         unsigned long v;
1966         int i;
1967
1968         move_irq(irq);
1969 /*
1970  * It appears there is an erratum which affects at least version 0x11
1971  * of I/O APIC (that's the 82093AA and cores integrated into various
1972  * chipsets).  Under certain conditions a level-triggered interrupt is
1973  * erroneously delivered as edge-triggered one but the respective IRR
1974  * bit gets set nevertheless.  As a result the I/O unit expects an EOI
1975  * message but it will never arrive and further interrupts are blocked
1976  * from the source.  The exact reason is so far unknown, but the
1977  * phenomenon was observed when two consecutive interrupt requests
1978  * from a given source get delivered to the same CPU and the source is
1979  * temporarily disabled in between.
1980  *
1981  * A workaround is to simulate an EOI message manually.  We achieve it
1982  * by setting the trigger mode to edge and then to level when the edge
1983  * trigger mode gets detected in the TMR of a local APIC for a
1984  * level-triggered interrupt.  We mask the source for the time of the
1985  * operation to prevent an edge-triggered interrupt escaping meanwhile.
1986  * The idea is from Manfred Spraul.  --macro
1987  */
1988         i = IO_APIC_VECTOR(irq);
1989
1990         v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1991
1992         ack_APIC_irq();
1993
1994         if (!(v & (1 << (i & 0x1f)))) {
1995                 atomic_inc(&irq_mis_count);
1996                 spin_lock(&ioapic_lock);
1997                 __mask_and_edge_IO_APIC_irq(irq);
1998                 __unmask_and_level_IO_APIC_irq(irq);
1999                 spin_unlock(&ioapic_lock);
2000         }
2001 }
2002
2003 #ifdef CONFIG_PCI_MSI
2004 static unsigned int startup_edge_ioapic_vector(unsigned int vector)
2005 {
2006         int irq = vector_to_irq(vector);
2007
2008         return startup_edge_ioapic_irq(irq);
2009 }
2010
2011 static void ack_edge_ioapic_vector(unsigned int vector)
2012 {
2013         int irq = vector_to_irq(vector);
2014
2015         move_native_irq(vector);
2016         ack_edge_ioapic_irq(irq);
2017 }
2018
2019 static unsigned int startup_level_ioapic_vector (unsigned int vector)
2020 {
2021         int irq = vector_to_irq(vector);
2022
2023         return startup_level_ioapic_irq (irq);
2024 }
2025
2026 static void end_level_ioapic_vector (unsigned int vector)
2027 {
2028         int irq = vector_to_irq(vector);
2029
2030         move_native_irq(vector);
2031         end_level_ioapic_irq(irq);
2032 }
2033
2034 static void mask_IO_APIC_vector (unsigned int vector)
2035 {
2036         int irq = vector_to_irq(vector);
2037
2038         mask_IO_APIC_irq(irq);
2039 }
2040
2041 static void unmask_IO_APIC_vector (unsigned int vector)
2042 {
2043         int irq = vector_to_irq(vector);
2044
2045         unmask_IO_APIC_irq(irq);
2046 }
2047
2048 #ifdef CONFIG_SMP
2049 static void set_ioapic_affinity_vector (unsigned int vector,
2050                                         cpumask_t cpu_mask)
2051 {
2052         int irq = vector_to_irq(vector);
2053
2054         set_native_irq_info(vector, cpu_mask);
2055         set_ioapic_affinity_irq(irq, cpu_mask);
2056 }
2057 #endif
2058 #endif
2059
2060 /*
2061  * Level and edge triggered IO-APIC interrupts need different handling,
2062  * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2063  * handled with the level-triggered descriptor, but that one has slightly
2064  * more overhead. Level-triggered interrupts cannot be handled with the
2065  * edge-triggered handler, without risking IRQ storms and other ugly
2066  * races.
2067  */
2068 static struct hw_interrupt_type ioapic_edge_type __read_mostly = {
2069         .typename       = "IO-APIC-edge",
2070         .startup        = startup_edge_ioapic,
2071         .shutdown       = shutdown_edge_ioapic,
2072         .enable         = enable_edge_ioapic,
2073         .disable        = disable_edge_ioapic,
2074         .ack            = ack_edge_ioapic,
2075         .end            = end_edge_ioapic,
2076 #ifdef CONFIG_SMP
2077         .set_affinity   = set_ioapic_affinity,
2078 #endif
2079 };
2080
2081 static struct hw_interrupt_type ioapic_level_type __read_mostly = {
2082         .typename       = "IO-APIC-level",
2083         .startup        = startup_level_ioapic,
2084         .shutdown       = shutdown_level_ioapic,
2085         .enable         = enable_level_ioapic,
2086         .disable        = disable_level_ioapic,
2087         .ack            = mask_and_ack_level_ioapic,
2088         .end            = end_level_ioapic,
2089 #ifdef CONFIG_SMP
2090         .set_affinity   = set_ioapic_affinity,
2091 #endif
2092 };
2093
2094 static inline void init_IO_APIC_traps(void)
2095 {
2096         int irq;
2097
2098         /*
2099          * NOTE! The local APIC isn't very good at handling
2100          * multiple interrupts at the same interrupt level.
2101          * As the interrupt level is determined by taking the
2102          * vector number and shifting that right by 4, we
2103          * want to spread these out a bit so that they don't
2104          * all fall in the same interrupt level.
2105          *
2106          * Also, we've got to be careful not to trash gate
2107          * 0x80, because int 0x80 is hm, kind of importantish. ;)
2108          */
2109         for (irq = 0; irq < NR_IRQS ; irq++) {
2110                 int tmp = irq;
2111                 if (use_pci_vector()) {
2112                         if (!platform_legacy_irq(tmp))
2113                                 if ((tmp = vector_to_irq(tmp)) == -1)
2114                                         continue;
2115                 }
2116                 if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
2117                         /*
2118                          * Hmm.. We don't have an entry for this,
2119                          * so default to an old-fashioned 8259
2120                          * interrupt if we can..
2121                          */
2122                         if (irq < 16)
2123                                 make_8259A_irq(irq);
2124                         else
2125                                 /* Strange. Oh, well.. */
2126                                 irq_desc[irq].handler = &no_irq_type;
2127                 }
2128         }
2129 }
2130
2131 static void enable_lapic_irq (unsigned int irq)
2132 {
2133         unsigned long v;
2134
2135         v = apic_read(APIC_LVT0);
2136         apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
2137 }
2138
2139 static void disable_lapic_irq (unsigned int irq)
2140 {
2141         unsigned long v;
2142
2143         v = apic_read(APIC_LVT0);
2144         apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
2145 }
2146
2147 static void ack_lapic_irq (unsigned int irq)
2148 {
2149         ack_APIC_irq();
2150 }
2151
2152 static void end_lapic_irq (unsigned int i) { /* nothing */ }
2153
2154 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
2155         .typename       = "local-APIC-edge",
2156         .startup        = NULL, /* startup_irq() not used for IRQ0 */
2157         .shutdown       = NULL, /* shutdown_irq() not used for IRQ0 */
2158         .enable         = enable_lapic_irq,
2159         .disable        = disable_lapic_irq,
2160         .ack            = ack_lapic_irq,
2161         .end            = end_lapic_irq
2162 };
2163
2164 static void setup_nmi (void)
2165 {
2166         /*
2167          * Dirty trick to enable the NMI watchdog ...
2168          * We put the 8259A master into AEOI mode and
2169          * unmask on all local APICs LVT0 as NMI.
2170          *
2171          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2172          * is from Maciej W. Rozycki - so we do not have to EOI from
2173          * the NMI handler or the timer interrupt.
2174          */ 
2175         apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2176
2177         on_each_cpu(enable_NMI_through_LVT0, NULL, 1, 1);
2178
2179         apic_printk(APIC_VERBOSE, " done.\n");
2180 }
2181
2182 /*
2183  * This looks a bit hackish but it's about the only one way of sending
2184  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
2185  * not support the ExtINT mode, unfortunately.  We need to send these
2186  * cycles as some i82489DX-based boards have glue logic that keeps the
2187  * 8259A interrupt line asserted until INTA.  --macro
2188  */
2189 static inline void unlock_ExtINT_logic(void)
2190 {
2191         int apic, pin, i;
2192         struct IO_APIC_route_entry entry0, entry1;
2193         unsigned char save_control, save_freq_select;
2194         unsigned long flags;
2195
2196         pin  = find_isa_irq_pin(8, mp_INT);
2197         apic = find_isa_irq_apic(8, mp_INT);
2198         if (pin == -1)
2199                 return;
2200
2201         spin_lock_irqsave(&ioapic_lock, flags);
2202         *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
2203         *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
2204         spin_unlock_irqrestore(&ioapic_lock, flags);
2205         clear_IO_APIC_pin(apic, pin);
2206
2207         memset(&entry1, 0, sizeof(entry1));
2208
2209         entry1.dest_mode = 0;                   /* physical delivery */
2210         entry1.mask = 0;                        /* unmask IRQ now */
2211         entry1.dest.physical.physical_dest = hard_smp_processor_id();
2212         entry1.delivery_mode = dest_ExtINT;
2213         entry1.polarity = entry0.polarity;
2214         entry1.trigger = 0;
2215         entry1.vector = 0;
2216
2217         spin_lock_irqsave(&ioapic_lock, flags);
2218         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
2219         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
2220         spin_unlock_irqrestore(&ioapic_lock, flags);
2221
2222         save_control = CMOS_READ(RTC_CONTROL);
2223         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2224         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2225                    RTC_FREQ_SELECT);
2226         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2227
2228         i = 100;
2229         while (i-- > 0) {
2230                 mdelay(10);
2231                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2232                         i -= 10;
2233         }
2234
2235         CMOS_WRITE(save_control, RTC_CONTROL);
2236         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2237         clear_IO_APIC_pin(apic, pin);
2238
2239         spin_lock_irqsave(&ioapic_lock, flags);
2240         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
2241         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
2242         spin_unlock_irqrestore(&ioapic_lock, flags);
2243 }
2244
2245 /*
2246  * This code may look a bit paranoid, but it's supposed to cooperate with
2247  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
2248  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
2249  * fanatically on his truly buggy board.
2250  */
2251 static inline void check_timer(void)
2252 {
2253         int apic1, pin1, apic2, pin2;
2254         int vector;
2255
2256         /*
2257          * get/set the timer IRQ vector:
2258          */
2259         disable_8259A_irq(0);
2260         vector = assign_irq_vector(0);
2261         set_intr_gate(vector, interrupt[0]);
2262
2263         /*
2264          * Subtle, code in do_timer_interrupt() expects an AEOI
2265          * mode for the 8259A whenever interrupts are routed
2266          * through I/O APICs.  Also IRQ0 has to be enabled in
2267          * the 8259A which implies the virtual wire has to be
2268          * disabled in the local APIC.
2269          */
2270         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2271         init_8259A(1);
2272         timer_ack = 1;
2273         if (timer_over_8254 > 0)
2274                 enable_8259A_irq(0);
2275
2276         pin1  = find_isa_irq_pin(0, mp_INT);
2277         apic1 = find_isa_irq_apic(0, mp_INT);
2278         pin2  = ioapic_i8259.pin;
2279         apic2 = ioapic_i8259.apic;
2280
2281         printk(KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
2282                 vector, apic1, pin1, apic2, pin2);
2283
2284         if (pin1 != -1) {
2285                 /*
2286                  * Ok, does IRQ0 through the IOAPIC work?
2287                  */
2288                 unmask_IO_APIC_irq(0);
2289                 if (timer_irq_works()) {
2290                         if (nmi_watchdog == NMI_IO_APIC) {
2291                                 disable_8259A_irq(0);
2292                                 setup_nmi();
2293                                 enable_8259A_irq(0);
2294                         }
2295                         if (disable_timer_pin_1 > 0)
2296                                 clear_IO_APIC_pin(0, pin1);
2297                         return;
2298                 }
2299                 clear_IO_APIC_pin(apic1, pin1);
2300                 printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to "
2301                                 "IO-APIC\n");
2302         }
2303
2304         printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
2305         if (pin2 != -1) {
2306                 printk("\n..... (found pin %d) ...", pin2);
2307                 /*
2308                  * legacy devices should be connected to IO APIC #0
2309                  */
2310                 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
2311                 if (timer_irq_works()) {
2312                         printk("works.\n");
2313                         if (pin1 != -1)
2314                                 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
2315                         else
2316                                 add_pin_to_irq(0, apic2, pin2);
2317                         if (nmi_watchdog == NMI_IO_APIC) {
2318                                 setup_nmi();
2319                         }
2320                         return;
2321                 }
2322                 /*
2323                  * Cleanup, just in case ...
2324                  */
2325                 clear_IO_APIC_pin(apic2, pin2);
2326         }
2327         printk(" failed.\n");
2328
2329         if (nmi_watchdog == NMI_IO_APIC) {
2330                 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
2331                 nmi_watchdog = 0;
2332         }
2333
2334         printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
2335
2336         disable_8259A_irq(0);
2337         irq_desc[0].handler = &lapic_irq_type;
2338         apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector);   /* Fixed mode */
2339         enable_8259A_irq(0);
2340
2341         if (timer_irq_works()) {
2342                 printk(" works.\n");
2343                 return;
2344         }
2345         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
2346         printk(" failed.\n");
2347
2348         printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
2349
2350         timer_ack = 0;
2351         init_8259A(0);
2352         make_8259A_irq(0);
2353         apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
2354
2355         unlock_ExtINT_logic();
2356
2357         if (timer_irq_works()) {
2358                 printk(" works.\n");
2359                 return;
2360         }
2361         printk(" failed :(.\n");
2362         panic("IO-APIC + timer doesn't work!  Boot with apic=debug and send a "
2363                 "report.  Then try booting with the 'noapic' option");
2364 }
2365
2366 /*
2367  *
2368  * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2369  * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2370  *   Linux doesn't really care, as it's not actually used
2371  *   for any interrupt handling anyway.
2372  */
2373 #define PIC_IRQS        (1 << PIC_CASCADE_IR)
2374
2375 void __init setup_IO_APIC(void)
2376 {
2377         enable_IO_APIC();
2378
2379         if (acpi_ioapic)
2380                 io_apic_irqs = ~0;      /* all IRQs go through IOAPIC */
2381         else
2382                 io_apic_irqs = ~PIC_IRQS;
2383
2384         printk("ENABLING IO-APIC IRQs\n");
2385
2386         /*
2387          * Set up IO-APIC IRQ routing.
2388          */
2389         if (!acpi_ioapic)
2390                 setup_ioapic_ids_from_mpc();
2391         sync_Arb_IDs();
2392         setup_IO_APIC_irqs();
2393         init_IO_APIC_traps();
2394         check_timer();
2395         if (!acpi_ioapic)
2396                 print_IO_APIC();
2397 }
2398
2399 static int __init setup_disable_8254_timer(char *s)
2400 {
2401         timer_over_8254 = -1;
2402         return 1;
2403 }
2404 static int __init setup_enable_8254_timer(char *s)
2405 {
2406         timer_over_8254 = 2;
2407         return 1;
2408 }
2409
2410 __setup("disable_8254_timer", setup_disable_8254_timer);
2411 __setup("enable_8254_timer", setup_enable_8254_timer);
2412
2413 /*
2414  *      Called after all the initialization is done. If we didnt find any
2415  *      APIC bugs then we can allow the modify fast path
2416  */
2417  
2418 static int __init io_apic_bug_finalize(void)
2419 {
2420         if(sis_apic_bug == -1)
2421                 sis_apic_bug = 0;
2422         return 0;
2423 }
2424
2425 late_initcall(io_apic_bug_finalize);
2426
2427 struct sysfs_ioapic_data {
2428         struct sys_device dev;
2429         struct IO_APIC_route_entry entry[0];
2430 };
2431 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2432
2433 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2434 {
2435         struct IO_APIC_route_entry *entry;
2436         struct sysfs_ioapic_data *data;
2437         unsigned long flags;
2438         int i;
2439         
2440         data = container_of(dev, struct sysfs_ioapic_data, dev);
2441         entry = data->entry;
2442         spin_lock_irqsave(&ioapic_lock, flags);
2443         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
2444                 *(((int *)entry) + 1) = io_apic_read(dev->id, 0x11 + 2 * i);
2445                 *(((int *)entry) + 0) = io_apic_read(dev->id, 0x10 + 2 * i);
2446         }
2447         spin_unlock_irqrestore(&ioapic_lock, flags);
2448
2449         return 0;
2450 }
2451
2452 static int ioapic_resume(struct sys_device *dev)
2453 {
2454         struct IO_APIC_route_entry *entry;
2455         struct sysfs_ioapic_data *data;
2456         unsigned long flags;
2457         union IO_APIC_reg_00 reg_00;
2458         int i;
2459         
2460         data = container_of(dev, struct sysfs_ioapic_data, dev);
2461         entry = data->entry;
2462
2463         spin_lock_irqsave(&ioapic_lock, flags);
2464         reg_00.raw = io_apic_read(dev->id, 0);
2465         if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
2466                 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
2467                 io_apic_write(dev->id, 0, reg_00.raw);
2468         }
2469         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
2470                 io_apic_write(dev->id, 0x11+2*i, *(((int *)entry)+1));
2471                 io_apic_write(dev->id, 0x10+2*i, *(((int *)entry)+0));
2472         }
2473         spin_unlock_irqrestore(&ioapic_lock, flags);
2474
2475         return 0;
2476 }
2477
2478 static struct sysdev_class ioapic_sysdev_class = {
2479         set_kset_name("ioapic"),
2480         .suspend = ioapic_suspend,
2481         .resume = ioapic_resume,
2482 };
2483
2484 static int __init ioapic_init_sysfs(void)
2485 {
2486         struct sys_device * dev;
2487         int i, size, error = 0;
2488
2489         error = sysdev_class_register(&ioapic_sysdev_class);
2490         if (error)
2491                 return error;
2492
2493         for (i = 0; i < nr_ioapics; i++ ) {
2494                 size = sizeof(struct sys_device) + nr_ioapic_registers[i] 
2495                         * sizeof(struct IO_APIC_route_entry);
2496                 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
2497                 if (!mp_ioapic_data[i]) {
2498                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2499                         continue;
2500                 }
2501                 memset(mp_ioapic_data[i], 0, size);
2502                 dev = &mp_ioapic_data[i]->dev;
2503                 dev->id = i; 
2504                 dev->cls = &ioapic_sysdev_class;
2505                 error = sysdev_register(dev);
2506                 if (error) {
2507                         kfree(mp_ioapic_data[i]);
2508                         mp_ioapic_data[i] = NULL;
2509                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2510                         continue;
2511                 }
2512         }
2513
2514         return 0;
2515 }
2516
2517 device_initcall(ioapic_init_sysfs);
2518
2519 /* --------------------------------------------------------------------------
2520                           ACPI-based IOAPIC Configuration
2521    -------------------------------------------------------------------------- */
2522
2523 #ifdef CONFIG_ACPI
2524
2525 int __init io_apic_get_unique_id (int ioapic, int apic_id)
2526 {
2527         union IO_APIC_reg_00 reg_00;
2528         static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2529         physid_mask_t tmp;
2530         unsigned long flags;
2531         int i = 0;
2532
2533         /*
2534          * The P4 platform supports up to 256 APIC IDs on two separate APIC 
2535          * buses (one for LAPICs, one for IOAPICs), where predecessors only 
2536          * supports up to 16 on one shared APIC bus.
2537          * 
2538          * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2539          *      advantage of new APIC bus architecture.
2540          */
2541
2542         if (physids_empty(apic_id_map))
2543                 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
2544
2545         spin_lock_irqsave(&ioapic_lock, flags);
2546         reg_00.raw = io_apic_read(ioapic, 0);
2547         spin_unlock_irqrestore(&ioapic_lock, flags);
2548
2549         if (apic_id >= get_physical_broadcast()) {
2550                 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2551                         "%d\n", ioapic, apic_id, reg_00.bits.ID);
2552                 apic_id = reg_00.bits.ID;
2553         }
2554
2555         /*
2556          * Every APIC in a system must have a unique ID or we get lots of nice 
2557          * 'stuck on smp_invalidate_needed IPI wait' messages.
2558          */
2559         if (check_apicid_used(apic_id_map, apic_id)) {
2560
2561                 for (i = 0; i < get_physical_broadcast(); i++) {
2562                         if (!check_apicid_used(apic_id_map, i))
2563                                 break;
2564                 }
2565
2566                 if (i == get_physical_broadcast())
2567                         panic("Max apic_id exceeded!\n");
2568
2569                 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2570                         "trying %d\n", ioapic, apic_id, i);
2571
2572                 apic_id = i;
2573         } 
2574
2575         tmp = apicid_to_cpu_present(apic_id);
2576         physids_or(apic_id_map, apic_id_map, tmp);
2577
2578         if (reg_00.bits.ID != apic_id) {
2579                 reg_00.bits.ID = apic_id;
2580
2581                 spin_lock_irqsave(&ioapic_lock, flags);
2582                 io_apic_write(ioapic, 0, reg_00.raw);
2583                 reg_00.raw = io_apic_read(ioapic, 0);
2584                 spin_unlock_irqrestore(&ioapic_lock, flags);
2585
2586                 /* Sanity check */
2587                 if (reg_00.bits.ID != apic_id) {
2588                         printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
2589                         return -1;
2590                 }
2591         }
2592
2593         apic_printk(APIC_VERBOSE, KERN_INFO
2594                         "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2595
2596         return apic_id;
2597 }
2598
2599
2600 int __init io_apic_get_version (int ioapic)
2601 {
2602         union IO_APIC_reg_01    reg_01;
2603         unsigned long flags;
2604
2605         spin_lock_irqsave(&ioapic_lock, flags);
2606         reg_01.raw = io_apic_read(ioapic, 1);
2607         spin_unlock_irqrestore(&ioapic_lock, flags);
2608
2609         return reg_01.bits.version;
2610 }
2611
2612
2613 int __init io_apic_get_redir_entries (int ioapic)
2614 {
2615         union IO_APIC_reg_01    reg_01;
2616         unsigned long flags;
2617
2618         spin_lock_irqsave(&ioapic_lock, flags);
2619         reg_01.raw = io_apic_read(ioapic, 1);
2620         spin_unlock_irqrestore(&ioapic_lock, flags);
2621
2622         return reg_01.bits.entries;
2623 }
2624
2625
2626 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
2627 {
2628         struct IO_APIC_route_entry entry;
2629         unsigned long flags;
2630
2631         if (!IO_APIC_IRQ(irq)) {
2632                 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2633                         ioapic);
2634                 return -EINVAL;
2635         }
2636
2637         /*
2638          * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2639          * Note that we mask (disable) IRQs now -- these get enabled when the
2640          * corresponding device driver registers for this IRQ.
2641          */
2642
2643         memset(&entry,0,sizeof(entry));
2644
2645         entry.delivery_mode = INT_DELIVERY_MODE;
2646         entry.dest_mode = INT_DEST_MODE;
2647         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2648         entry.trigger = edge_level;
2649         entry.polarity = active_high_low;
2650         entry.mask  = 1;
2651
2652         /*
2653          * IRQs < 16 are already in the irq_2_pin[] map
2654          */
2655         if (irq >= 16)
2656                 add_pin_to_irq(irq, ioapic, pin);
2657
2658         entry.vector = assign_irq_vector(irq);
2659
2660         apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry "
2661                 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic,
2662                 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2663                 edge_level, active_high_low);
2664
2665         ioapic_register_intr(irq, entry.vector, edge_level);
2666
2667         if (!ioapic && (irq < 16))
2668                 disable_8259A_irq(irq);
2669
2670         spin_lock_irqsave(&ioapic_lock, flags);
2671         io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1));
2672         io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0));
2673         set_native_irq_info(use_pci_vector() ? entry.vector : irq, TARGET_CPUS);
2674         spin_unlock_irqrestore(&ioapic_lock, flags);
2675
2676         return 0;
2677 }
2678
2679 #endif /* CONFIG_ACPI */