Merge git://git.kernel.org/pub/scm/linux/kernel/git/steve/gfs2-2.6-fixes
[linux-2.6.git] / arch / i386 / kernel / io_apic.c
1 /*
2  *      Intel IO-APIC support for multi-Pentium hosts.
3  *
4  *      Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5  *
6  *      Many thanks to Stig Venaas for trying out countless experimental
7  *      patches and reporting/debugging problems patiently!
8  *
9  *      (c) 1999, Multiple IO-APIC support, developed by
10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
13  *      and Ingo Molnar <mingo@redhat.com>
14  *
15  *      Fixes
16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
17  *                                      thanks to Eric Gilmore
18  *                                      and Rolf G. Tews
19  *                                      for testing these extensively
20  *      Paul Diefenbaugh        :       Added full ACPI support
21  */
22
23 #include <linux/mm.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/mc146818rtc.h>
29 #include <linux/compiler.h>
30 #include <linux/acpi.h>
31 #include <linux/module.h>
32 #include <linux/sysdev.h>
33 #include <linux/pci.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38
39 #include <asm/io.h>
40 #include <asm/smp.h>
41 #include <asm/desc.h>
42 #include <asm/timer.h>
43 #include <asm/i8259.h>
44 #include <asm/nmi.h>
45 #include <asm/msidef.h>
46 #include <asm/hypertransport.h>
47
48 #include <mach_apic.h>
49 #include <mach_apicdef.h>
50
51 #include "io_ports.h"
52
53 int (*ioapic_renumber_irq)(int ioapic, int irq);
54 atomic_t irq_mis_count;
55
56 /* Where if anywhere is the i8259 connect in external int mode */
57 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
58
59 static DEFINE_SPINLOCK(ioapic_lock);
60 static DEFINE_SPINLOCK(vector_lock);
61
62 int timer_over_8254 __initdata = 1;
63
64 /*
65  *      Is the SiS APIC rmw bug present ?
66  *      -1 = don't know, 0 = no, 1 = yes
67  */
68 int sis_apic_bug = -1;
69
70 /*
71  * # of IRQ routing registers
72  */
73 int nr_ioapic_registers[MAX_IO_APICS];
74
75 static int disable_timer_pin_1 __initdata;
76
77 /*
78  * Rough estimation of how many shared IRQs there are, can
79  * be changed anytime.
80  */
81 #define MAX_PLUS_SHARED_IRQS NR_IRQS
82 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
83
84 /*
85  * This is performance-critical, we want to do it O(1)
86  *
87  * the indexing order of this array favors 1:1 mappings
88  * between pins and IRQs.
89  */
90
91 static struct irq_pin_list {
92         int apic, pin, next;
93 } irq_2_pin[PIN_MAP_SIZE];
94
95 struct io_apic {
96         unsigned int index;
97         unsigned int unused[3];
98         unsigned int data;
99 };
100
101 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
102 {
103         return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
104                 + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK);
105 }
106
107 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
108 {
109         struct io_apic __iomem *io_apic = io_apic_base(apic);
110         writel(reg, &io_apic->index);
111         return readl(&io_apic->data);
112 }
113
114 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
115 {
116         struct io_apic __iomem *io_apic = io_apic_base(apic);
117         writel(reg, &io_apic->index);
118         writel(value, &io_apic->data);
119 }
120
121 /*
122  * Re-write a value: to be used for read-modify-write
123  * cycles where the read already set up the index register.
124  *
125  * Older SiS APIC requires we rewrite the index register
126  */
127 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
128 {
129         volatile struct io_apic __iomem *io_apic = io_apic_base(apic);
130         if (sis_apic_bug)
131                 writel(reg, &io_apic->index);
132         writel(value, &io_apic->data);
133 }
134
135 union entry_union {
136         struct { u32 w1, w2; };
137         struct IO_APIC_route_entry entry;
138 };
139
140 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
141 {
142         union entry_union eu;
143         unsigned long flags;
144         spin_lock_irqsave(&ioapic_lock, flags);
145         eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
146         eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
147         spin_unlock_irqrestore(&ioapic_lock, flags);
148         return eu.entry;
149 }
150
151 /*
152  * When we write a new IO APIC routing entry, we need to write the high
153  * word first! If the mask bit in the low word is clear, we will enable
154  * the interrupt, and we need to make sure the entry is fully populated
155  * before that happens.
156  */
157 static void
158 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
159 {
160         union entry_union eu;
161         eu.entry = e;
162         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
163         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
164 }
165
166 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
167 {
168         unsigned long flags;
169         spin_lock_irqsave(&ioapic_lock, flags);
170         __ioapic_write_entry(apic, pin, e);
171         spin_unlock_irqrestore(&ioapic_lock, flags);
172 }
173
174 /*
175  * When we mask an IO APIC routing entry, we need to write the low
176  * word first, in order to set the mask bit before we change the
177  * high bits!
178  */
179 static void ioapic_mask_entry(int apic, int pin)
180 {
181         unsigned long flags;
182         union entry_union eu = { .entry.mask = 1 };
183
184         spin_lock_irqsave(&ioapic_lock, flags);
185         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
186         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
187         spin_unlock_irqrestore(&ioapic_lock, flags);
188 }
189
190 /*
191  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
192  * shared ISA-space IRQs, so we have to support them. We are super
193  * fast in the common case, and fast for shared ISA-space IRQs.
194  */
195 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
196 {
197         static int first_free_entry = NR_IRQS;
198         struct irq_pin_list *entry = irq_2_pin + irq;
199
200         while (entry->next)
201                 entry = irq_2_pin + entry->next;
202
203         if (entry->pin != -1) {
204                 entry->next = first_free_entry;
205                 entry = irq_2_pin + entry->next;
206                 if (++first_free_entry >= PIN_MAP_SIZE)
207                         panic("io_apic.c: whoops");
208         }
209         entry->apic = apic;
210         entry->pin = pin;
211 }
212
213 /*
214  * Reroute an IRQ to a different pin.
215  */
216 static void __init replace_pin_at_irq(unsigned int irq,
217                                       int oldapic, int oldpin,
218                                       int newapic, int newpin)
219 {
220         struct irq_pin_list *entry = irq_2_pin + irq;
221
222         while (1) {
223                 if (entry->apic == oldapic && entry->pin == oldpin) {
224                         entry->apic = newapic;
225                         entry->pin = newpin;
226                 }
227                 if (!entry->next)
228                         break;
229                 entry = irq_2_pin + entry->next;
230         }
231 }
232
233 static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable)
234 {
235         struct irq_pin_list *entry = irq_2_pin + irq;
236         unsigned int pin, reg;
237
238         for (;;) {
239                 pin = entry->pin;
240                 if (pin == -1)
241                         break;
242                 reg = io_apic_read(entry->apic, 0x10 + pin*2);
243                 reg &= ~disable;
244                 reg |= enable;
245                 io_apic_modify(entry->apic, 0x10 + pin*2, reg);
246                 if (!entry->next)
247                         break;
248                 entry = irq_2_pin + entry->next;
249         }
250 }
251
252 /* mask = 1 */
253 static void __mask_IO_APIC_irq (unsigned int irq)
254 {
255         __modify_IO_APIC_irq(irq, 0x00010000, 0);
256 }
257
258 /* mask = 0 */
259 static void __unmask_IO_APIC_irq (unsigned int irq)
260 {
261         __modify_IO_APIC_irq(irq, 0, 0x00010000);
262 }
263
264 /* mask = 1, trigger = 0 */
265 static void __mask_and_edge_IO_APIC_irq (unsigned int irq)
266 {
267         __modify_IO_APIC_irq(irq, 0x00010000, 0x00008000);
268 }
269
270 /* mask = 0, trigger = 1 */
271 static void __unmask_and_level_IO_APIC_irq (unsigned int irq)
272 {
273         __modify_IO_APIC_irq(irq, 0x00008000, 0x00010000);
274 }
275
276 static void mask_IO_APIC_irq (unsigned int irq)
277 {
278         unsigned long flags;
279
280         spin_lock_irqsave(&ioapic_lock, flags);
281         __mask_IO_APIC_irq(irq);
282         spin_unlock_irqrestore(&ioapic_lock, flags);
283 }
284
285 static void unmask_IO_APIC_irq (unsigned int irq)
286 {
287         unsigned long flags;
288
289         spin_lock_irqsave(&ioapic_lock, flags);
290         __unmask_IO_APIC_irq(irq);
291         spin_unlock_irqrestore(&ioapic_lock, flags);
292 }
293
294 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
295 {
296         struct IO_APIC_route_entry entry;
297         
298         /* Check delivery_mode to be sure we're not clearing an SMI pin */
299         entry = ioapic_read_entry(apic, pin);
300         if (entry.delivery_mode == dest_SMI)
301                 return;
302
303         /*
304          * Disable it in the IO-APIC irq-routing table:
305          */
306         ioapic_mask_entry(apic, pin);
307 }
308
309 static void clear_IO_APIC (void)
310 {
311         int apic, pin;
312
313         for (apic = 0; apic < nr_ioapics; apic++)
314                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
315                         clear_IO_APIC_pin(apic, pin);
316 }
317
318 #ifdef CONFIG_SMP
319 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
320 {
321         unsigned long flags;
322         int pin;
323         struct irq_pin_list *entry = irq_2_pin + irq;
324         unsigned int apicid_value;
325         cpumask_t tmp;
326         
327         cpus_and(tmp, cpumask, cpu_online_map);
328         if (cpus_empty(tmp))
329                 tmp = TARGET_CPUS;
330
331         cpus_and(cpumask, tmp, CPU_MASK_ALL);
332
333         apicid_value = cpu_mask_to_apicid(cpumask);
334         /* Prepare to do the io_apic_write */
335         apicid_value = apicid_value << 24;
336         spin_lock_irqsave(&ioapic_lock, flags);
337         for (;;) {
338                 pin = entry->pin;
339                 if (pin == -1)
340                         break;
341                 io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
342                 if (!entry->next)
343                         break;
344                 entry = irq_2_pin + entry->next;
345         }
346         irq_desc[irq].affinity = cpumask;
347         spin_unlock_irqrestore(&ioapic_lock, flags);
348 }
349
350 #if defined(CONFIG_IRQBALANCE)
351 # include <asm/processor.h>     /* kernel_thread() */
352 # include <linux/kernel_stat.h> /* kstat */
353 # include <linux/slab.h>                /* kmalloc() */
354 # include <linux/timer.h>       /* time_after() */
355  
356 #define IRQBALANCE_CHECK_ARCH -999
357 #define MAX_BALANCED_IRQ_INTERVAL       (5*HZ)
358 #define MIN_BALANCED_IRQ_INTERVAL       (HZ/2)
359 #define BALANCED_IRQ_MORE_DELTA         (HZ/10)
360 #define BALANCED_IRQ_LESS_DELTA         (HZ)
361
362 static int irqbalance_disabled __read_mostly = IRQBALANCE_CHECK_ARCH;
363 static int physical_balance __read_mostly;
364 static long balanced_irq_interval __read_mostly = MAX_BALANCED_IRQ_INTERVAL;
365
366 static struct irq_cpu_info {
367         unsigned long * last_irq;
368         unsigned long * irq_delta;
369         unsigned long irq;
370 } irq_cpu_data[NR_CPUS];
371
372 #define CPU_IRQ(cpu)            (irq_cpu_data[cpu].irq)
373 #define LAST_CPU_IRQ(cpu,irq)   (irq_cpu_data[cpu].last_irq[irq])
374 #define IRQ_DELTA(cpu,irq)      (irq_cpu_data[cpu].irq_delta[irq])
375
376 #define IDLE_ENOUGH(cpu,now) \
377         (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
378
379 #define IRQ_ALLOWED(cpu, allowed_mask)  cpu_isset(cpu, allowed_mask)
380
381 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(cpu_sibling_map[i]))
382
383 static cpumask_t balance_irq_affinity[NR_IRQS] = {
384         [0 ... NR_IRQS-1] = CPU_MASK_ALL
385 };
386
387 void set_balance_irq_affinity(unsigned int irq, cpumask_t mask)
388 {
389         balance_irq_affinity[irq] = mask;
390 }
391
392 static unsigned long move(int curr_cpu, cpumask_t allowed_mask,
393                         unsigned long now, int direction)
394 {
395         int search_idle = 1;
396         int cpu = curr_cpu;
397
398         goto inside;
399
400         do {
401                 if (unlikely(cpu == curr_cpu))
402                         search_idle = 0;
403 inside:
404                 if (direction == 1) {
405                         cpu++;
406                         if (cpu >= NR_CPUS)
407                                 cpu = 0;
408                 } else {
409                         cpu--;
410                         if (cpu == -1)
411                                 cpu = NR_CPUS-1;
412                 }
413         } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu,allowed_mask) ||
414                         (search_idle && !IDLE_ENOUGH(cpu,now)));
415
416         return cpu;
417 }
418
419 static inline void balance_irq(int cpu, int irq)
420 {
421         unsigned long now = jiffies;
422         cpumask_t allowed_mask;
423         unsigned int new_cpu;
424                 
425         if (irqbalance_disabled)
426                 return; 
427
428         cpus_and(allowed_mask, cpu_online_map, balance_irq_affinity[irq]);
429         new_cpu = move(cpu, allowed_mask, now, 1);
430         if (cpu != new_cpu) {
431                 set_pending_irq(irq, cpumask_of_cpu(new_cpu));
432         }
433 }
434
435 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold)
436 {
437         int i, j;
438
439         for_each_online_cpu(i) {
440                 for (j = 0; j < NR_IRQS; j++) {
441                         if (!irq_desc[j].action)
442                                 continue;
443                         /* Is it a significant load ?  */
444                         if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i),j) <
445                                                 useful_load_threshold)
446                                 continue;
447                         balance_irq(i, j);
448                 }
449         }
450         balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
451                 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);       
452         return;
453 }
454
455 static void do_irq_balance(void)
456 {
457         int i, j;
458         unsigned long max_cpu_irq = 0, min_cpu_irq = (~0);
459         unsigned long move_this_load = 0;
460         int max_loaded = 0, min_loaded = 0;
461         int load;
462         unsigned long useful_load_threshold = balanced_irq_interval + 10;
463         int selected_irq;
464         int tmp_loaded, first_attempt = 1;
465         unsigned long tmp_cpu_irq;
466         unsigned long imbalance = 0;
467         cpumask_t allowed_mask, target_cpu_mask, tmp;
468
469         for_each_possible_cpu(i) {
470                 int package_index;
471                 CPU_IRQ(i) = 0;
472                 if (!cpu_online(i))
473                         continue;
474                 package_index = CPU_TO_PACKAGEINDEX(i);
475                 for (j = 0; j < NR_IRQS; j++) {
476                         unsigned long value_now, delta;
477                         /* Is this an active IRQ or balancing disabled ? */
478                         if (!irq_desc[j].action || irq_balancing_disabled(j))
479                                 continue;
480                         if ( package_index == i )
481                                 IRQ_DELTA(package_index,j) = 0;
482                         /* Determine the total count per processor per IRQ */
483                         value_now = (unsigned long) kstat_cpu(i).irqs[j];
484
485                         /* Determine the activity per processor per IRQ */
486                         delta = value_now - LAST_CPU_IRQ(i,j);
487
488                         /* Update last_cpu_irq[][] for the next time */
489                         LAST_CPU_IRQ(i,j) = value_now;
490
491                         /* Ignore IRQs whose rate is less than the clock */
492                         if (delta < useful_load_threshold)
493                                 continue;
494                         /* update the load for the processor or package total */
495                         IRQ_DELTA(package_index,j) += delta;
496
497                         /* Keep track of the higher numbered sibling as well */
498                         if (i != package_index)
499                                 CPU_IRQ(i) += delta;
500                         /*
501                          * We have sibling A and sibling B in the package
502                          *
503                          * cpu_irq[A] = load for cpu A + load for cpu B
504                          * cpu_irq[B] = load for cpu B
505                          */
506                         CPU_IRQ(package_index) += delta;
507                 }
508         }
509         /* Find the least loaded processor package */
510         for_each_online_cpu(i) {
511                 if (i != CPU_TO_PACKAGEINDEX(i))
512                         continue;
513                 if (min_cpu_irq > CPU_IRQ(i)) {
514                         min_cpu_irq = CPU_IRQ(i);
515                         min_loaded = i;
516                 }
517         }
518         max_cpu_irq = ULONG_MAX;
519
520 tryanothercpu:
521         /* Look for heaviest loaded processor.
522          * We may come back to get the next heaviest loaded processor.
523          * Skip processors with trivial loads.
524          */
525         tmp_cpu_irq = 0;
526         tmp_loaded = -1;
527         for_each_online_cpu(i) {
528                 if (i != CPU_TO_PACKAGEINDEX(i))
529                         continue;
530                 if (max_cpu_irq <= CPU_IRQ(i)) 
531                         continue;
532                 if (tmp_cpu_irq < CPU_IRQ(i)) {
533                         tmp_cpu_irq = CPU_IRQ(i);
534                         tmp_loaded = i;
535                 }
536         }
537
538         if (tmp_loaded == -1) {
539          /* In the case of small number of heavy interrupt sources, 
540           * loading some of the cpus too much. We use Ingo's original 
541           * approach to rotate them around.
542           */
543                 if (!first_attempt && imbalance >= useful_load_threshold) {
544                         rotate_irqs_among_cpus(useful_load_threshold);
545                         return;
546                 }
547                 goto not_worth_the_effort;
548         }
549         
550         first_attempt = 0;              /* heaviest search */
551         max_cpu_irq = tmp_cpu_irq;      /* load */
552         max_loaded = tmp_loaded;        /* processor */
553         imbalance = (max_cpu_irq - min_cpu_irq) / 2;
554         
555         /* if imbalance is less than approx 10% of max load, then
556          * observe diminishing returns action. - quit
557          */
558         if (imbalance < (max_cpu_irq >> 3))
559                 goto not_worth_the_effort;
560
561 tryanotherirq:
562         /* if we select an IRQ to move that can't go where we want, then
563          * see if there is another one to try.
564          */
565         move_this_load = 0;
566         selected_irq = -1;
567         for (j = 0; j < NR_IRQS; j++) {
568                 /* Is this an active IRQ? */
569                 if (!irq_desc[j].action)
570                         continue;
571                 if (imbalance <= IRQ_DELTA(max_loaded,j))
572                         continue;
573                 /* Try to find the IRQ that is closest to the imbalance
574                  * without going over.
575                  */
576                 if (move_this_load < IRQ_DELTA(max_loaded,j)) {
577                         move_this_load = IRQ_DELTA(max_loaded,j);
578                         selected_irq = j;
579                 }
580         }
581         if (selected_irq == -1) {
582                 goto tryanothercpu;
583         }
584
585         imbalance = move_this_load;
586         
587         /* For physical_balance case, we accumlated both load
588          * values in the one of the siblings cpu_irq[],
589          * to use the same code for physical and logical processors
590          * as much as possible. 
591          *
592          * NOTE: the cpu_irq[] array holds the sum of the load for
593          * sibling A and sibling B in the slot for the lowest numbered
594          * sibling (A), _AND_ the load for sibling B in the slot for
595          * the higher numbered sibling.
596          *
597          * We seek the least loaded sibling by making the comparison
598          * (A+B)/2 vs B
599          */
600         load = CPU_IRQ(min_loaded) >> 1;
601         for_each_cpu_mask(j, cpu_sibling_map[min_loaded]) {
602                 if (load > CPU_IRQ(j)) {
603                         /* This won't change cpu_sibling_map[min_loaded] */
604                         load = CPU_IRQ(j);
605                         min_loaded = j;
606                 }
607         }
608
609         cpus_and(allowed_mask,
610                 cpu_online_map,
611                 balance_irq_affinity[selected_irq]);
612         target_cpu_mask = cpumask_of_cpu(min_loaded);
613         cpus_and(tmp, target_cpu_mask, allowed_mask);
614
615         if (!cpus_empty(tmp)) {
616                 /* mark for change destination */
617                 set_pending_irq(selected_irq, cpumask_of_cpu(min_loaded));
618
619                 /* Since we made a change, come back sooner to 
620                  * check for more variation.
621                  */
622                 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
623                         balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);       
624                 return;
625         }
626         goto tryanotherirq;
627
628 not_worth_the_effort:
629         /*
630          * if we did not find an IRQ to move, then adjust the time interval
631          * upward
632          */
633         balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL,
634                 balanced_irq_interval + BALANCED_IRQ_MORE_DELTA);       
635         return;
636 }
637
638 static int balanced_irq(void *unused)
639 {
640         int i;
641         unsigned long prev_balance_time = jiffies;
642         long time_remaining = balanced_irq_interval;
643
644         /* push everything to CPU 0 to give us a starting point.  */
645         for (i = 0 ; i < NR_IRQS ; i++) {
646                 irq_desc[i].pending_mask = cpumask_of_cpu(0);
647                 set_pending_irq(i, cpumask_of_cpu(0));
648         }
649
650         set_freezable();
651         for ( ; ; ) {
652                 time_remaining = schedule_timeout_interruptible(time_remaining);
653                 try_to_freeze();
654                 if (time_after(jiffies,
655                                 prev_balance_time+balanced_irq_interval)) {
656                         preempt_disable();
657                         do_irq_balance();
658                         prev_balance_time = jiffies;
659                         time_remaining = balanced_irq_interval;
660                         preempt_enable();
661                 }
662         }
663         return 0;
664 }
665
666 static int __init balanced_irq_init(void)
667 {
668         int i;
669         struct cpuinfo_x86 *c;
670         cpumask_t tmp;
671
672         cpus_shift_right(tmp, cpu_online_map, 2);
673         c = &boot_cpu_data;
674         /* When not overwritten by the command line ask subarchitecture. */
675         if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH)
676                 irqbalance_disabled = NO_BALANCE_IRQ;
677         if (irqbalance_disabled)
678                 return 0;
679         
680          /* disable irqbalance completely if there is only one processor online */
681         if (num_online_cpus() < 2) {
682                 irqbalance_disabled = 1;
683                 return 0;
684         }
685         /*
686          * Enable physical balance only if more than 1 physical processor
687          * is present
688          */
689         if (smp_num_siblings > 1 && !cpus_empty(tmp))
690                 physical_balance = 1;
691
692         for_each_online_cpu(i) {
693                 irq_cpu_data[i].irq_delta = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
694                 irq_cpu_data[i].last_irq = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
695                 if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) {
696                         printk(KERN_ERR "balanced_irq_init: out of memory");
697                         goto failed;
698                 }
699                 memset(irq_cpu_data[i].irq_delta,0,sizeof(unsigned long) * NR_IRQS);
700                 memset(irq_cpu_data[i].last_irq,0,sizeof(unsigned long) * NR_IRQS);
701         }
702         
703         printk(KERN_INFO "Starting balanced_irq\n");
704         if (!IS_ERR(kthread_run(balanced_irq, NULL, "kirqd")))
705                 return 0;
706         printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq");
707 failed:
708         for_each_possible_cpu(i) {
709                 kfree(irq_cpu_data[i].irq_delta);
710                 irq_cpu_data[i].irq_delta = NULL;
711                 kfree(irq_cpu_data[i].last_irq);
712                 irq_cpu_data[i].last_irq = NULL;
713         }
714         return 0;
715 }
716
717 int __devinit irqbalance_disable(char *str)
718 {
719         irqbalance_disabled = 1;
720         return 1;
721 }
722
723 __setup("noirqbalance", irqbalance_disable);
724
725 late_initcall(balanced_irq_init);
726 #endif /* CONFIG_IRQBALANCE */
727 #endif /* CONFIG_SMP */
728
729 #ifndef CONFIG_SMP
730 void fastcall send_IPI_self(int vector)
731 {
732         unsigned int cfg;
733
734         /*
735          * Wait for idle.
736          */
737         apic_wait_icr_idle();
738         cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
739         /*
740          * Send the IPI. The write to APIC_ICR fires this off.
741          */
742         apic_write_around(APIC_ICR, cfg);
743 }
744 #endif /* !CONFIG_SMP */
745
746
747 /*
748  * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
749  * specific CPU-side IRQs.
750  */
751
752 #define MAX_PIRQS 8
753 static int pirq_entries [MAX_PIRQS];
754 static int pirqs_enabled;
755 int skip_ioapic_setup;
756
757 static int __init ioapic_setup(char *str)
758 {
759         skip_ioapic_setup = 1;
760         return 1;
761 }
762
763 __setup("noapic", ioapic_setup);
764
765 static int __init ioapic_pirq_setup(char *str)
766 {
767         int i, max;
768         int ints[MAX_PIRQS+1];
769
770         get_options(str, ARRAY_SIZE(ints), ints);
771
772         for (i = 0; i < MAX_PIRQS; i++)
773                 pirq_entries[i] = -1;
774
775         pirqs_enabled = 1;
776         apic_printk(APIC_VERBOSE, KERN_INFO
777                         "PIRQ redirection, working around broken MP-BIOS.\n");
778         max = MAX_PIRQS;
779         if (ints[0] < MAX_PIRQS)
780                 max = ints[0];
781
782         for (i = 0; i < max; i++) {
783                 apic_printk(APIC_VERBOSE, KERN_DEBUG
784                                 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
785                 /*
786                  * PIRQs are mapped upside down, usually.
787                  */
788                 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
789         }
790         return 1;
791 }
792
793 __setup("pirq=", ioapic_pirq_setup);
794
795 /*
796  * Find the IRQ entry number of a certain pin.
797  */
798 static int find_irq_entry(int apic, int pin, int type)
799 {
800         int i;
801
802         for (i = 0; i < mp_irq_entries; i++)
803                 if (mp_irqs[i].mpc_irqtype == type &&
804                     (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
805                      mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
806                     mp_irqs[i].mpc_dstirq == pin)
807                         return i;
808
809         return -1;
810 }
811
812 /*
813  * Find the pin to which IRQ[irq] (ISA) is connected
814  */
815 static int __init find_isa_irq_pin(int irq, int type)
816 {
817         int i;
818
819         for (i = 0; i < mp_irq_entries; i++) {
820                 int lbus = mp_irqs[i].mpc_srcbus;
821
822                 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
823                      mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
824                      mp_bus_id_to_type[lbus] == MP_BUS_MCA
825                     ) &&
826                     (mp_irqs[i].mpc_irqtype == type) &&
827                     (mp_irqs[i].mpc_srcbusirq == irq))
828
829                         return mp_irqs[i].mpc_dstirq;
830         }
831         return -1;
832 }
833
834 static int __init find_isa_irq_apic(int irq, int type)
835 {
836         int i;
837
838         for (i = 0; i < mp_irq_entries; i++) {
839                 int lbus = mp_irqs[i].mpc_srcbus;
840
841                 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
842                      mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
843                      mp_bus_id_to_type[lbus] == MP_BUS_MCA
844                     ) &&
845                     (mp_irqs[i].mpc_irqtype == type) &&
846                     (mp_irqs[i].mpc_srcbusirq == irq))
847                         break;
848         }
849         if (i < mp_irq_entries) {
850                 int apic;
851                 for(apic = 0; apic < nr_ioapics; apic++) {
852                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
853                                 return apic;
854                 }
855         }
856
857         return -1;
858 }
859
860 /*
861  * Find a specific PCI IRQ entry.
862  * Not an __init, possibly needed by modules
863  */
864 static int pin_2_irq(int idx, int apic, int pin);
865
866 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
867 {
868         int apic, i, best_guess = -1;
869
870         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, "
871                 "slot:%d, pin:%d.\n", bus, slot, pin);
872         if (mp_bus_id_to_pci_bus[bus] == -1) {
873                 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
874                 return -1;
875         }
876         for (i = 0; i < mp_irq_entries; i++) {
877                 int lbus = mp_irqs[i].mpc_srcbus;
878
879                 for (apic = 0; apic < nr_ioapics; apic++)
880                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
881                             mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
882                                 break;
883
884                 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
885                     !mp_irqs[i].mpc_irqtype &&
886                     (bus == lbus) &&
887                     (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
888                         int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
889
890                         if (!(apic || IO_APIC_IRQ(irq)))
891                                 continue;
892
893                         if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
894                                 return irq;
895                         /*
896                          * Use the first all-but-pin matching entry as a
897                          * best-guess fuzzy result for broken mptables.
898                          */
899                         if (best_guess < 0)
900                                 best_guess = irq;
901                 }
902         }
903         return best_guess;
904 }
905 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
906
907 /*
908  * This function currently is only a helper for the i386 smp boot process where 
909  * we need to reprogram the ioredtbls to cater for the cpus which have come online
910  * so mask in all cases should simply be TARGET_CPUS
911  */
912 #ifdef CONFIG_SMP
913 void __init setup_ioapic_dest(void)
914 {
915         int pin, ioapic, irq, irq_entry;
916
917         if (skip_ioapic_setup == 1)
918                 return;
919
920         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
921                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
922                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
923                         if (irq_entry == -1)
924                                 continue;
925                         irq = pin_2_irq(irq_entry, ioapic, pin);
926                         set_ioapic_affinity_irq(irq, TARGET_CPUS);
927                 }
928
929         }
930 }
931 #endif
932
933 /*
934  * EISA Edge/Level control register, ELCR
935  */
936 static int EISA_ELCR(unsigned int irq)
937 {
938         if (irq < 16) {
939                 unsigned int port = 0x4d0 + (irq >> 3);
940                 return (inb(port) >> (irq & 7)) & 1;
941         }
942         apic_printk(APIC_VERBOSE, KERN_INFO
943                         "Broken MPtable reports ISA irq %d\n", irq);
944         return 0;
945 }
946
947 /* EISA interrupts are always polarity zero and can be edge or level
948  * trigger depending on the ELCR value.  If an interrupt is listed as
949  * EISA conforming in the MP table, that means its trigger type must
950  * be read in from the ELCR */
951
952 #define default_EISA_trigger(idx)       (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
953 #define default_EISA_polarity(idx)      (0)
954
955 /* ISA interrupts are always polarity zero edge triggered,
956  * when listed as conforming in the MP table. */
957
958 #define default_ISA_trigger(idx)        (0)
959 #define default_ISA_polarity(idx)       (0)
960
961 /* PCI interrupts are always polarity one level triggered,
962  * when listed as conforming in the MP table. */
963
964 #define default_PCI_trigger(idx)        (1)
965 #define default_PCI_polarity(idx)       (1)
966
967 /* MCA interrupts are always polarity zero level triggered,
968  * when listed as conforming in the MP table. */
969
970 #define default_MCA_trigger(idx)        (1)
971 #define default_MCA_polarity(idx)       (0)
972
973 static int __init MPBIOS_polarity(int idx)
974 {
975         int bus = mp_irqs[idx].mpc_srcbus;
976         int polarity;
977
978         /*
979          * Determine IRQ line polarity (high active or low active):
980          */
981         switch (mp_irqs[idx].mpc_irqflag & 3)
982         {
983                 case 0: /* conforms, ie. bus-type dependent polarity */
984                 {
985                         switch (mp_bus_id_to_type[bus])
986                         {
987                                 case MP_BUS_ISA: /* ISA pin */
988                                 {
989                                         polarity = default_ISA_polarity(idx);
990                                         break;
991                                 }
992                                 case MP_BUS_EISA: /* EISA pin */
993                                 {
994                                         polarity = default_EISA_polarity(idx);
995                                         break;
996                                 }
997                                 case MP_BUS_PCI: /* PCI pin */
998                                 {
999                                         polarity = default_PCI_polarity(idx);
1000                                         break;
1001                                 }
1002                                 case MP_BUS_MCA: /* MCA pin */
1003                                 {
1004                                         polarity = default_MCA_polarity(idx);
1005                                         break;
1006                                 }
1007                                 default:
1008                                 {
1009                                         printk(KERN_WARNING "broken BIOS!!\n");
1010                                         polarity = 1;
1011                                         break;
1012                                 }
1013                         }
1014                         break;
1015                 }
1016                 case 1: /* high active */
1017                 {
1018                         polarity = 0;
1019                         break;
1020                 }
1021                 case 2: /* reserved */
1022                 {
1023                         printk(KERN_WARNING "broken BIOS!!\n");
1024                         polarity = 1;
1025                         break;
1026                 }
1027                 case 3: /* low active */
1028                 {
1029                         polarity = 1;
1030                         break;
1031                 }
1032                 default: /* invalid */
1033                 {
1034                         printk(KERN_WARNING "broken BIOS!!\n");
1035                         polarity = 1;
1036                         break;
1037                 }
1038         }
1039         return polarity;
1040 }
1041
1042 static int MPBIOS_trigger(int idx)
1043 {
1044         int bus = mp_irqs[idx].mpc_srcbus;
1045         int trigger;
1046
1047         /*
1048          * Determine IRQ trigger mode (edge or level sensitive):
1049          */
1050         switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
1051         {
1052                 case 0: /* conforms, ie. bus-type dependent */
1053                 {
1054                         switch (mp_bus_id_to_type[bus])
1055                         {
1056                                 case MP_BUS_ISA: /* ISA pin */
1057                                 {
1058                                         trigger = default_ISA_trigger(idx);
1059                                         break;
1060                                 }
1061                                 case MP_BUS_EISA: /* EISA pin */
1062                                 {
1063                                         trigger = default_EISA_trigger(idx);
1064                                         break;
1065                                 }
1066                                 case MP_BUS_PCI: /* PCI pin */
1067                                 {
1068                                         trigger = default_PCI_trigger(idx);
1069                                         break;
1070                                 }
1071                                 case MP_BUS_MCA: /* MCA pin */
1072                                 {
1073                                         trigger = default_MCA_trigger(idx);
1074                                         break;
1075                                 }
1076                                 default:
1077                                 {
1078                                         printk(KERN_WARNING "broken BIOS!!\n");
1079                                         trigger = 1;
1080                                         break;
1081                                 }
1082                         }
1083                         break;
1084                 }
1085                 case 1: /* edge */
1086                 {
1087                         trigger = 0;
1088                         break;
1089                 }
1090                 case 2: /* reserved */
1091                 {
1092                         printk(KERN_WARNING "broken BIOS!!\n");
1093                         trigger = 1;
1094                         break;
1095                 }
1096                 case 3: /* level */
1097                 {
1098                         trigger = 1;
1099                         break;
1100                 }
1101                 default: /* invalid */
1102                 {
1103                         printk(KERN_WARNING "broken BIOS!!\n");
1104                         trigger = 0;
1105                         break;
1106                 }
1107         }
1108         return trigger;
1109 }
1110
1111 static inline int irq_polarity(int idx)
1112 {
1113         return MPBIOS_polarity(idx);
1114 }
1115
1116 static inline int irq_trigger(int idx)
1117 {
1118         return MPBIOS_trigger(idx);
1119 }
1120
1121 static int pin_2_irq(int idx, int apic, int pin)
1122 {
1123         int irq, i;
1124         int bus = mp_irqs[idx].mpc_srcbus;
1125
1126         /*
1127          * Debugging check, we are in big trouble if this message pops up!
1128          */
1129         if (mp_irqs[idx].mpc_dstirq != pin)
1130                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1131
1132         switch (mp_bus_id_to_type[bus])
1133         {
1134                 case MP_BUS_ISA: /* ISA pin */
1135                 case MP_BUS_EISA:
1136                 case MP_BUS_MCA:
1137                 {
1138                         irq = mp_irqs[idx].mpc_srcbusirq;
1139                         break;
1140                 }
1141                 case MP_BUS_PCI: /* PCI pin */
1142                 {
1143                         /*
1144                          * PCI IRQs are mapped in order
1145                          */
1146                         i = irq = 0;
1147                         while (i < apic)
1148                                 irq += nr_ioapic_registers[i++];
1149                         irq += pin;
1150
1151                         /*
1152                          * For MPS mode, so far only needed by ES7000 platform
1153                          */
1154                         if (ioapic_renumber_irq)
1155                                 irq = ioapic_renumber_irq(apic, irq);
1156
1157                         break;
1158                 }
1159                 default:
1160                 {
1161                         printk(KERN_ERR "unknown bus type %d.\n",bus); 
1162                         irq = 0;
1163                         break;
1164                 }
1165         }
1166
1167         /*
1168          * PCI IRQ command line redirection. Yes, limits are hardcoded.
1169          */
1170         if ((pin >= 16) && (pin <= 23)) {
1171                 if (pirq_entries[pin-16] != -1) {
1172                         if (!pirq_entries[pin-16]) {
1173                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1174                                                 "disabling PIRQ%d\n", pin-16);
1175                         } else {
1176                                 irq = pirq_entries[pin-16];
1177                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1178                                                 "using PIRQ%d -> IRQ %d\n",
1179                                                 pin-16, irq);
1180                         }
1181                 }
1182         }
1183         return irq;
1184 }
1185
1186 static inline int IO_APIC_irq_trigger(int irq)
1187 {
1188         int apic, idx, pin;
1189
1190         for (apic = 0; apic < nr_ioapics; apic++) {
1191                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1192                         idx = find_irq_entry(apic,pin,mp_INT);
1193                         if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
1194                                 return irq_trigger(idx);
1195                 }
1196         }
1197         /*
1198          * nonexistent IRQs are edge default
1199          */
1200         return 0;
1201 }
1202
1203 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1204 static u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 };
1205
1206 static int __assign_irq_vector(int irq)
1207 {
1208         static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1209         int vector, offset, i;
1210
1211         BUG_ON((unsigned)irq >= NR_IRQ_VECTORS);
1212
1213         if (irq_vector[irq] > 0)
1214                 return irq_vector[irq];
1215
1216         vector = current_vector;
1217         offset = current_offset;
1218 next:
1219         vector += 8;
1220         if (vector >= FIRST_SYSTEM_VECTOR) {
1221                 offset = (offset + 1) % 8;
1222                 vector = FIRST_DEVICE_VECTOR + offset;
1223         }
1224         if (vector == current_vector)
1225                 return -ENOSPC;
1226         if (vector == SYSCALL_VECTOR)
1227                 goto next;
1228         for (i = 0; i < NR_IRQ_VECTORS; i++)
1229                 if (irq_vector[i] == vector)
1230                         goto next;
1231
1232         current_vector = vector;
1233         current_offset = offset;
1234         irq_vector[irq] = vector;
1235
1236         return vector;
1237 }
1238
1239 static int assign_irq_vector(int irq)
1240 {
1241         unsigned long flags;
1242         int vector;
1243
1244         spin_lock_irqsave(&vector_lock, flags);
1245         vector = __assign_irq_vector(irq);
1246         spin_unlock_irqrestore(&vector_lock, flags);
1247
1248         return vector;
1249 }
1250 static struct irq_chip ioapic_chip;
1251
1252 #define IOAPIC_AUTO     -1
1253 #define IOAPIC_EDGE     0
1254 #define IOAPIC_LEVEL    1
1255
1256 static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
1257 {
1258         if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1259             trigger == IOAPIC_LEVEL) {
1260                 irq_desc[irq].status |= IRQ_LEVEL;
1261                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1262                                          handle_fasteoi_irq, "fasteoi");
1263         } else {
1264                 irq_desc[irq].status &= ~IRQ_LEVEL;
1265                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1266                                          handle_edge_irq, "edge");
1267         }
1268         set_intr_gate(vector, interrupt[irq]);
1269 }
1270
1271 static void __init setup_IO_APIC_irqs(void)
1272 {
1273         struct IO_APIC_route_entry entry;
1274         int apic, pin, idx, irq, first_notcon = 1, vector;
1275         unsigned long flags;
1276
1277         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1278
1279         for (apic = 0; apic < nr_ioapics; apic++) {
1280         for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1281
1282                 /*
1283                  * add it to the IO-APIC irq-routing table:
1284                  */
1285                 memset(&entry,0,sizeof(entry));
1286
1287                 entry.delivery_mode = INT_DELIVERY_MODE;
1288                 entry.dest_mode = INT_DEST_MODE;
1289                 entry.mask = 0;                         /* enable IRQ */
1290                 entry.dest.logical.logical_dest = 
1291                                         cpu_mask_to_apicid(TARGET_CPUS);
1292
1293                 idx = find_irq_entry(apic,pin,mp_INT);
1294                 if (idx == -1) {
1295                         if (first_notcon) {
1296                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1297                                                 " IO-APIC (apicid-pin) %d-%d",
1298                                                 mp_ioapics[apic].mpc_apicid,
1299                                                 pin);
1300                                 first_notcon = 0;
1301                         } else
1302                                 apic_printk(APIC_VERBOSE, ", %d-%d",
1303                                         mp_ioapics[apic].mpc_apicid, pin);
1304                         continue;
1305                 }
1306
1307                 entry.trigger = irq_trigger(idx);
1308                 entry.polarity = irq_polarity(idx);
1309
1310                 if (irq_trigger(idx)) {
1311                         entry.trigger = 1;
1312                         entry.mask = 1;
1313                 }
1314
1315                 irq = pin_2_irq(idx, apic, pin);
1316                 /*
1317                  * skip adding the timer int on secondary nodes, which causes
1318                  * a small but painful rift in the time-space continuum
1319                  */
1320                 if (multi_timer_check(apic, irq))
1321                         continue;
1322                 else
1323                         add_pin_to_irq(irq, apic, pin);
1324
1325                 if (!apic && !IO_APIC_IRQ(irq))
1326                         continue;
1327
1328                 if (IO_APIC_IRQ(irq)) {
1329                         vector = assign_irq_vector(irq);
1330                         entry.vector = vector;
1331                         ioapic_register_intr(irq, vector, IOAPIC_AUTO);
1332                 
1333                         if (!apic && (irq < 16))
1334                                 disable_8259A_irq(irq);
1335                 }
1336                 spin_lock_irqsave(&ioapic_lock, flags);
1337                 __ioapic_write_entry(apic, pin, entry);
1338                 spin_unlock_irqrestore(&ioapic_lock, flags);
1339         }
1340         }
1341
1342         if (!first_notcon)
1343                 apic_printk(APIC_VERBOSE, " not connected.\n");
1344 }
1345
1346 /*
1347  * Set up the 8259A-master output pin:
1348  */
1349 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
1350 {
1351         struct IO_APIC_route_entry entry;
1352
1353         memset(&entry,0,sizeof(entry));
1354
1355         disable_8259A_irq(0);
1356
1357         /* mask LVT0 */
1358         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1359
1360         /*
1361          * We use logical delivery to get the timer IRQ
1362          * to the first CPU.
1363          */
1364         entry.dest_mode = INT_DEST_MODE;
1365         entry.mask = 0;                                 /* unmask IRQ now */
1366         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1367         entry.delivery_mode = INT_DELIVERY_MODE;
1368         entry.polarity = 0;
1369         entry.trigger = 0;
1370         entry.vector = vector;
1371
1372         /*
1373          * The timer IRQ doesn't have to know that behind the
1374          * scene we have a 8259A-master in AEOI mode ...
1375          */
1376         irq_desc[0].chip = &ioapic_chip;
1377         set_irq_handler(0, handle_edge_irq);
1378
1379         /*
1380          * Add it to the IO-APIC irq-routing table:
1381          */
1382         ioapic_write_entry(apic, pin, entry);
1383
1384         enable_8259A_irq(0);
1385 }
1386
1387 void __init print_IO_APIC(void)
1388 {
1389         int apic, i;
1390         union IO_APIC_reg_00 reg_00;
1391         union IO_APIC_reg_01 reg_01;
1392         union IO_APIC_reg_02 reg_02;
1393         union IO_APIC_reg_03 reg_03;
1394         unsigned long flags;
1395
1396         if (apic_verbosity == APIC_QUIET)
1397                 return;
1398
1399         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1400         for (i = 0; i < nr_ioapics; i++)
1401                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1402                        mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
1403
1404         /*
1405          * We are a bit conservative about what we expect.  We have to
1406          * know about every hardware change ASAP.
1407          */
1408         printk(KERN_INFO "testing the IO APIC.......................\n");
1409
1410         for (apic = 0; apic < nr_ioapics; apic++) {
1411
1412         spin_lock_irqsave(&ioapic_lock, flags);
1413         reg_00.raw = io_apic_read(apic, 0);
1414         reg_01.raw = io_apic_read(apic, 1);
1415         if (reg_01.bits.version >= 0x10)
1416                 reg_02.raw = io_apic_read(apic, 2);
1417         if (reg_01.bits.version >= 0x20)
1418                 reg_03.raw = io_apic_read(apic, 3);
1419         spin_unlock_irqrestore(&ioapic_lock, flags);
1420
1421         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
1422         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1423         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
1424         printk(KERN_DEBUG ".......    : Delivery Type: %X\n", reg_00.bits.delivery_type);
1425         printk(KERN_DEBUG ".......    : LTS          : %X\n", reg_00.bits.LTS);
1426
1427         printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
1428         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
1429
1430         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
1431         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
1432
1433         /*
1434          * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1435          * but the value of reg_02 is read as the previous read register
1436          * value, so ignore it if reg_02 == reg_01.
1437          */
1438         if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1439                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1440                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
1441         }
1442
1443         /*
1444          * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1445          * or reg_03, but the value of reg_0[23] is read as the previous read
1446          * register value, so ignore it if reg_03 == reg_0[12].
1447          */
1448         if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1449             reg_03.raw != reg_01.raw) {
1450                 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1451                 printk(KERN_DEBUG ".......     : Boot DT    : %X\n", reg_03.bits.boot_DT);
1452         }
1453
1454         printk(KERN_DEBUG ".... IRQ redirection table:\n");
1455
1456         printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1457                           " Stat Dest Deli Vect:   \n");
1458
1459         for (i = 0; i <= reg_01.bits.entries; i++) {
1460                 struct IO_APIC_route_entry entry;
1461
1462                 entry = ioapic_read_entry(apic, i);
1463
1464                 printk(KERN_DEBUG " %02x %03X %02X  ",
1465                         i,
1466                         entry.dest.logical.logical_dest,
1467                         entry.dest.physical.physical_dest
1468                 );
1469
1470                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
1471                         entry.mask,
1472                         entry.trigger,
1473                         entry.irr,
1474                         entry.polarity,
1475                         entry.delivery_status,
1476                         entry.dest_mode,
1477                         entry.delivery_mode,
1478                         entry.vector
1479                 );
1480         }
1481         }
1482         printk(KERN_DEBUG "IRQ to pin mappings:\n");
1483         for (i = 0; i < NR_IRQS; i++) {
1484                 struct irq_pin_list *entry = irq_2_pin + i;
1485                 if (entry->pin < 0)
1486                         continue;
1487                 printk(KERN_DEBUG "IRQ%d ", i);
1488                 for (;;) {
1489                         printk("-> %d:%d", entry->apic, entry->pin);
1490                         if (!entry->next)
1491                                 break;
1492                         entry = irq_2_pin + entry->next;
1493                 }
1494                 printk("\n");
1495         }
1496
1497         printk(KERN_INFO ".................................... done.\n");
1498
1499         return;
1500 }
1501
1502 #if 0
1503
1504 static void print_APIC_bitfield (int base)
1505 {
1506         unsigned int v;
1507         int i, j;
1508
1509         if (apic_verbosity == APIC_QUIET)
1510                 return;
1511
1512         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1513         for (i = 0; i < 8; i++) {
1514                 v = apic_read(base + i*0x10);
1515                 for (j = 0; j < 32; j++) {
1516                         if (v & (1<<j))
1517                                 printk("1");
1518                         else
1519                                 printk("0");
1520                 }
1521                 printk("\n");
1522         }
1523 }
1524
1525 void /*__init*/ print_local_APIC(void * dummy)
1526 {
1527         unsigned int v, ver, maxlvt;
1528
1529         if (apic_verbosity == APIC_QUIET)
1530                 return;
1531
1532         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1533                 smp_processor_id(), hard_smp_processor_id());
1534         v = apic_read(APIC_ID);
1535         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, GET_APIC_ID(v));
1536         v = apic_read(APIC_LVR);
1537         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1538         ver = GET_APIC_VERSION(v);
1539         maxlvt = lapic_get_maxlvt();
1540
1541         v = apic_read(APIC_TASKPRI);
1542         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1543
1544         if (APIC_INTEGRATED(ver)) {                     /* !82489DX */
1545                 v = apic_read(APIC_ARBPRI);
1546                 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1547                         v & APIC_ARBPRI_MASK);
1548                 v = apic_read(APIC_PROCPRI);
1549                 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1550         }
1551
1552         v = apic_read(APIC_EOI);
1553         printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1554         v = apic_read(APIC_RRR);
1555         printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1556         v = apic_read(APIC_LDR);
1557         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1558         v = apic_read(APIC_DFR);
1559         printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1560         v = apic_read(APIC_SPIV);
1561         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1562
1563         printk(KERN_DEBUG "... APIC ISR field:\n");
1564         print_APIC_bitfield(APIC_ISR);
1565         printk(KERN_DEBUG "... APIC TMR field:\n");
1566         print_APIC_bitfield(APIC_TMR);
1567         printk(KERN_DEBUG "... APIC IRR field:\n");
1568         print_APIC_bitfield(APIC_IRR);
1569
1570         if (APIC_INTEGRATED(ver)) {             /* !82489DX */
1571                 if (maxlvt > 3)         /* Due to the Pentium erratum 3AP. */
1572                         apic_write(APIC_ESR, 0);
1573                 v = apic_read(APIC_ESR);
1574                 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1575         }
1576
1577         v = apic_read(APIC_ICR);
1578         printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1579         v = apic_read(APIC_ICR2);
1580         printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1581
1582         v = apic_read(APIC_LVTT);
1583         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1584
1585         if (maxlvt > 3) {                       /* PC is LVT#4. */
1586                 v = apic_read(APIC_LVTPC);
1587                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1588         }
1589         v = apic_read(APIC_LVT0);
1590         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1591         v = apic_read(APIC_LVT1);
1592         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1593
1594         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1595                 v = apic_read(APIC_LVTERR);
1596                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1597         }
1598
1599         v = apic_read(APIC_TMICT);
1600         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1601         v = apic_read(APIC_TMCCT);
1602         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1603         v = apic_read(APIC_TDCR);
1604         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1605         printk("\n");
1606 }
1607
1608 void print_all_local_APICs (void)
1609 {
1610         on_each_cpu(print_local_APIC, NULL, 1, 1);
1611 }
1612
1613 void /*__init*/ print_PIC(void)
1614 {
1615         unsigned int v;
1616         unsigned long flags;
1617
1618         if (apic_verbosity == APIC_QUIET)
1619                 return;
1620
1621         printk(KERN_DEBUG "\nprinting PIC contents\n");
1622
1623         spin_lock_irqsave(&i8259A_lock, flags);
1624
1625         v = inb(0xa1) << 8 | inb(0x21);
1626         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1627
1628         v = inb(0xa0) << 8 | inb(0x20);
1629         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1630
1631         outb(0x0b,0xa0);
1632         outb(0x0b,0x20);
1633         v = inb(0xa0) << 8 | inb(0x20);
1634         outb(0x0a,0xa0);
1635         outb(0x0a,0x20);
1636
1637         spin_unlock_irqrestore(&i8259A_lock, flags);
1638
1639         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1640
1641         v = inb(0x4d1) << 8 | inb(0x4d0);
1642         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1643 }
1644
1645 #endif  /*  0  */
1646
1647 static void __init enable_IO_APIC(void)
1648 {
1649         union IO_APIC_reg_01 reg_01;
1650         int i8259_apic, i8259_pin;
1651         int i, apic;
1652         unsigned long flags;
1653
1654         for (i = 0; i < PIN_MAP_SIZE; i++) {
1655                 irq_2_pin[i].pin = -1;
1656                 irq_2_pin[i].next = 0;
1657         }
1658         if (!pirqs_enabled)
1659                 for (i = 0; i < MAX_PIRQS; i++)
1660                         pirq_entries[i] = -1;
1661
1662         /*
1663          * The number of IO-APIC IRQ registers (== #pins):
1664          */
1665         for (apic = 0; apic < nr_ioapics; apic++) {
1666                 spin_lock_irqsave(&ioapic_lock, flags);
1667                 reg_01.raw = io_apic_read(apic, 1);
1668                 spin_unlock_irqrestore(&ioapic_lock, flags);
1669                 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1670         }
1671         for(apic = 0; apic < nr_ioapics; apic++) {
1672                 int pin;
1673                 /* See if any of the pins is in ExtINT mode */
1674                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1675                         struct IO_APIC_route_entry entry;
1676                         entry = ioapic_read_entry(apic, pin);
1677
1678
1679                         /* If the interrupt line is enabled and in ExtInt mode
1680                          * I have found the pin where the i8259 is connected.
1681                          */
1682                         if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1683                                 ioapic_i8259.apic = apic;
1684                                 ioapic_i8259.pin  = pin;
1685                                 goto found_i8259;
1686                         }
1687                 }
1688         }
1689  found_i8259:
1690         /* Look to see what if the MP table has reported the ExtINT */
1691         /* If we could not find the appropriate pin by looking at the ioapic
1692          * the i8259 probably is not connected the ioapic but give the
1693          * mptable a chance anyway.
1694          */
1695         i8259_pin  = find_isa_irq_pin(0, mp_ExtINT);
1696         i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1697         /* Trust the MP table if nothing is setup in the hardware */
1698         if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1699                 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1700                 ioapic_i8259.pin  = i8259_pin;
1701                 ioapic_i8259.apic = i8259_apic;
1702         }
1703         /* Complain if the MP table and the hardware disagree */
1704         if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1705                 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1706         {
1707                 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1708         }
1709
1710         /*
1711          * Do not trust the IO-APIC being empty at bootup
1712          */
1713         clear_IO_APIC();
1714 }
1715
1716 /*
1717  * Not an __init, needed by the reboot code
1718  */
1719 void disable_IO_APIC(void)
1720 {
1721         /*
1722          * Clear the IO-APIC before rebooting:
1723          */
1724         clear_IO_APIC();
1725
1726         /*
1727          * If the i8259 is routed through an IOAPIC
1728          * Put that IOAPIC in virtual wire mode
1729          * so legacy interrupts can be delivered.
1730          */
1731         if (ioapic_i8259.pin != -1) {
1732                 struct IO_APIC_route_entry entry;
1733
1734                 memset(&entry, 0, sizeof(entry));
1735                 entry.mask            = 0; /* Enabled */
1736                 entry.trigger         = 0; /* Edge */
1737                 entry.irr             = 0;
1738                 entry.polarity        = 0; /* High */
1739                 entry.delivery_status = 0;
1740                 entry.dest_mode       = 0; /* Physical */
1741                 entry.delivery_mode   = dest_ExtINT; /* ExtInt */
1742                 entry.vector          = 0;
1743                 entry.dest.physical.physical_dest =
1744                                         GET_APIC_ID(apic_read(APIC_ID));
1745
1746                 /*
1747                  * Add it to the IO-APIC irq-routing table:
1748                  */
1749                 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1750         }
1751         disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1752 }
1753
1754 /*
1755  * function to set the IO-APIC physical IDs based on the
1756  * values stored in the MPC table.
1757  *
1758  * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
1759  */
1760
1761 #ifndef CONFIG_X86_NUMAQ
1762 static void __init setup_ioapic_ids_from_mpc(void)
1763 {
1764         union IO_APIC_reg_00 reg_00;
1765         physid_mask_t phys_id_present_map;
1766         int apic;
1767         int i;
1768         unsigned char old_id;
1769         unsigned long flags;
1770
1771         /*
1772          * Don't check I/O APIC IDs for xAPIC systems.  They have
1773          * no meaning without the serial APIC bus.
1774          */
1775         if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1776                 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
1777                 return;
1778         /*
1779          * This is broken; anything with a real cpu count has to
1780          * circumvent this idiocy regardless.
1781          */
1782         phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1783
1784         /*
1785          * Set the IOAPIC ID to the value stored in the MPC table.
1786          */
1787         for (apic = 0; apic < nr_ioapics; apic++) {
1788
1789                 /* Read the register 0 value */
1790                 spin_lock_irqsave(&ioapic_lock, flags);
1791                 reg_00.raw = io_apic_read(apic, 0);
1792                 spin_unlock_irqrestore(&ioapic_lock, flags);
1793                 
1794                 old_id = mp_ioapics[apic].mpc_apicid;
1795
1796                 if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) {
1797                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1798                                 apic, mp_ioapics[apic].mpc_apicid);
1799                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1800                                 reg_00.bits.ID);
1801                         mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
1802                 }
1803
1804                 /*
1805                  * Sanity check, is the ID really free? Every APIC in a
1806                  * system must have a unique ID or we get lots of nice
1807                  * 'stuck on smp_invalidate_needed IPI wait' messages.
1808                  */
1809                 if (check_apicid_used(phys_id_present_map,
1810                                         mp_ioapics[apic].mpc_apicid)) {
1811                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1812                                 apic, mp_ioapics[apic].mpc_apicid);
1813                         for (i = 0; i < get_physical_broadcast(); i++)
1814                                 if (!physid_isset(i, phys_id_present_map))
1815                                         break;
1816                         if (i >= get_physical_broadcast())
1817                                 panic("Max APIC ID exceeded!\n");
1818                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1819                                 i);
1820                         physid_set(i, phys_id_present_map);
1821                         mp_ioapics[apic].mpc_apicid = i;
1822                 } else {
1823                         physid_mask_t tmp;
1824                         tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid);
1825                         apic_printk(APIC_VERBOSE, "Setting %d in the "
1826                                         "phys_id_present_map\n",
1827                                         mp_ioapics[apic].mpc_apicid);
1828                         physids_or(phys_id_present_map, phys_id_present_map, tmp);
1829                 }
1830
1831
1832                 /*
1833                  * We need to adjust the IRQ routing table
1834                  * if the ID changed.
1835                  */
1836                 if (old_id != mp_ioapics[apic].mpc_apicid)
1837                         for (i = 0; i < mp_irq_entries; i++)
1838                                 if (mp_irqs[i].mpc_dstapic == old_id)
1839                                         mp_irqs[i].mpc_dstapic
1840                                                 = mp_ioapics[apic].mpc_apicid;
1841
1842                 /*
1843                  * Read the right value from the MPC table and
1844                  * write it into the ID register.
1845                  */
1846                 apic_printk(APIC_VERBOSE, KERN_INFO
1847                         "...changing IO-APIC physical APIC ID to %d ...",
1848                         mp_ioapics[apic].mpc_apicid);
1849
1850                 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1851                 spin_lock_irqsave(&ioapic_lock, flags);
1852                 io_apic_write(apic, 0, reg_00.raw);
1853                 spin_unlock_irqrestore(&ioapic_lock, flags);
1854
1855                 /*
1856                  * Sanity check
1857                  */
1858                 spin_lock_irqsave(&ioapic_lock, flags);
1859                 reg_00.raw = io_apic_read(apic, 0);
1860                 spin_unlock_irqrestore(&ioapic_lock, flags);
1861                 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1862                         printk("could not set ID!\n");
1863                 else
1864                         apic_printk(APIC_VERBOSE, " ok.\n");
1865         }
1866 }
1867 #else
1868 static void __init setup_ioapic_ids_from_mpc(void) { }
1869 #endif
1870
1871 int no_timer_check __initdata;
1872
1873 static int __init notimercheck(char *s)
1874 {
1875         no_timer_check = 1;
1876         return 1;
1877 }
1878 __setup("no_timer_check", notimercheck);
1879
1880 /*
1881  * There is a nasty bug in some older SMP boards, their mptable lies
1882  * about the timer IRQ. We do the following to work around the situation:
1883  *
1884  *      - timer IRQ defaults to IO-APIC IRQ
1885  *      - if this function detects that timer IRQs are defunct, then we fall
1886  *        back to ISA timer IRQs
1887  */
1888 static int __init timer_irq_works(void)
1889 {
1890         unsigned long t1 = jiffies;
1891
1892         if (no_timer_check)
1893                 return 1;
1894
1895         local_irq_enable();
1896         /* Let ten ticks pass... */
1897         mdelay((10 * 1000) / HZ);
1898
1899         /*
1900          * Expect a few ticks at least, to be sure some possible
1901          * glue logic does not lock up after one or two first
1902          * ticks in a non-ExtINT mode.  Also the local APIC
1903          * might have cached one ExtINT interrupt.  Finally, at
1904          * least one tick may be lost due to delays.
1905          */
1906         if (jiffies - t1 > 4)
1907                 return 1;
1908
1909         return 0;
1910 }
1911
1912 /*
1913  * In the SMP+IOAPIC case it might happen that there are an unspecified
1914  * number of pending IRQ events unhandled. These cases are very rare,
1915  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1916  * better to do it this way as thus we do not have to be aware of
1917  * 'pending' interrupts in the IRQ path, except at this point.
1918  */
1919 /*
1920  * Edge triggered needs to resend any interrupt
1921  * that was delayed but this is now handled in the device
1922  * independent code.
1923  */
1924
1925 /*
1926  * Startup quirk:
1927  *
1928  * Starting up a edge-triggered IO-APIC interrupt is
1929  * nasty - we need to make sure that we get the edge.
1930  * If it is already asserted for some reason, we need
1931  * return 1 to indicate that is was pending.
1932  *
1933  * This is not complete - we should be able to fake
1934  * an edge even if it isn't on the 8259A...
1935  *
1936  * (We do this for level-triggered IRQs too - it cannot hurt.)
1937  */
1938 static unsigned int startup_ioapic_irq(unsigned int irq)
1939 {
1940         int was_pending = 0;
1941         unsigned long flags;
1942
1943         spin_lock_irqsave(&ioapic_lock, flags);
1944         if (irq < 16) {
1945                 disable_8259A_irq(irq);
1946                 if (i8259A_irq_pending(irq))
1947                         was_pending = 1;
1948         }
1949         __unmask_IO_APIC_irq(irq);
1950         spin_unlock_irqrestore(&ioapic_lock, flags);
1951
1952         return was_pending;
1953 }
1954
1955 static void ack_ioapic_irq(unsigned int irq)
1956 {
1957         move_native_irq(irq);
1958         ack_APIC_irq();
1959 }
1960
1961 static void ack_ioapic_quirk_irq(unsigned int irq)
1962 {
1963         unsigned long v;
1964         int i;
1965
1966         move_native_irq(irq);
1967 /*
1968  * It appears there is an erratum which affects at least version 0x11
1969  * of I/O APIC (that's the 82093AA and cores integrated into various
1970  * chipsets).  Under certain conditions a level-triggered interrupt is
1971  * erroneously delivered as edge-triggered one but the respective IRR
1972  * bit gets set nevertheless.  As a result the I/O unit expects an EOI
1973  * message but it will never arrive and further interrupts are blocked
1974  * from the source.  The exact reason is so far unknown, but the
1975  * phenomenon was observed when two consecutive interrupt requests
1976  * from a given source get delivered to the same CPU and the source is
1977  * temporarily disabled in between.
1978  *
1979  * A workaround is to simulate an EOI message manually.  We achieve it
1980  * by setting the trigger mode to edge and then to level when the edge
1981  * trigger mode gets detected in the TMR of a local APIC for a
1982  * level-triggered interrupt.  We mask the source for the time of the
1983  * operation to prevent an edge-triggered interrupt escaping meanwhile.
1984  * The idea is from Manfred Spraul.  --macro
1985  */
1986         i = irq_vector[irq];
1987
1988         v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1989
1990         ack_APIC_irq();
1991
1992         if (!(v & (1 << (i & 0x1f)))) {
1993                 atomic_inc(&irq_mis_count);
1994                 spin_lock(&ioapic_lock);
1995                 __mask_and_edge_IO_APIC_irq(irq);
1996                 __unmask_and_level_IO_APIC_irq(irq);
1997                 spin_unlock(&ioapic_lock);
1998         }
1999 }
2000
2001 static int ioapic_retrigger_irq(unsigned int irq)
2002 {
2003         send_IPI_self(irq_vector[irq]);
2004
2005         return 1;
2006 }
2007
2008 static struct irq_chip ioapic_chip __read_mostly = {
2009         .name           = "IO-APIC",
2010         .startup        = startup_ioapic_irq,
2011         .mask           = mask_IO_APIC_irq,
2012         .unmask         = unmask_IO_APIC_irq,
2013         .ack            = ack_ioapic_irq,
2014         .eoi            = ack_ioapic_quirk_irq,
2015 #ifdef CONFIG_SMP
2016         .set_affinity   = set_ioapic_affinity_irq,
2017 #endif
2018         .retrigger      = ioapic_retrigger_irq,
2019 };
2020
2021
2022 static inline void init_IO_APIC_traps(void)
2023 {
2024         int irq;
2025
2026         /*
2027          * NOTE! The local APIC isn't very good at handling
2028          * multiple interrupts at the same interrupt level.
2029          * As the interrupt level is determined by taking the
2030          * vector number and shifting that right by 4, we
2031          * want to spread these out a bit so that they don't
2032          * all fall in the same interrupt level.
2033          *
2034          * Also, we've got to be careful not to trash gate
2035          * 0x80, because int 0x80 is hm, kind of importantish. ;)
2036          */
2037         for (irq = 0; irq < NR_IRQS ; irq++) {
2038                 int tmp = irq;
2039                 if (IO_APIC_IRQ(tmp) && !irq_vector[tmp]) {
2040                         /*
2041                          * Hmm.. We don't have an entry for this,
2042                          * so default to an old-fashioned 8259
2043                          * interrupt if we can..
2044                          */
2045                         if (irq < 16)
2046                                 make_8259A_irq(irq);
2047                         else
2048                                 /* Strange. Oh, well.. */
2049                                 irq_desc[irq].chip = &no_irq_chip;
2050                 }
2051         }
2052 }
2053
2054 /*
2055  * The local APIC irq-chip implementation:
2056  */
2057
2058 static void ack_apic(unsigned int irq)
2059 {
2060         ack_APIC_irq();
2061 }
2062
2063 static void mask_lapic_irq (unsigned int irq)
2064 {
2065         unsigned long v;
2066
2067         v = apic_read(APIC_LVT0);
2068         apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
2069 }
2070
2071 static void unmask_lapic_irq (unsigned int irq)
2072 {
2073         unsigned long v;
2074
2075         v = apic_read(APIC_LVT0);
2076         apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
2077 }
2078
2079 static struct irq_chip lapic_chip __read_mostly = {
2080         .name           = "local-APIC-edge",
2081         .mask           = mask_lapic_irq,
2082         .unmask         = unmask_lapic_irq,
2083         .eoi            = ack_apic,
2084 };
2085
2086 static void setup_nmi (void)
2087 {
2088         /*
2089          * Dirty trick to enable the NMI watchdog ...
2090          * We put the 8259A master into AEOI mode and
2091          * unmask on all local APICs LVT0 as NMI.
2092          *
2093          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2094          * is from Maciej W. Rozycki - so we do not have to EOI from
2095          * the NMI handler or the timer interrupt.
2096          */ 
2097         apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2098
2099         on_each_cpu(enable_NMI_through_LVT0, NULL, 1, 1);
2100
2101         apic_printk(APIC_VERBOSE, " done.\n");
2102 }
2103
2104 /*
2105  * This looks a bit hackish but it's about the only one way of sending
2106  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
2107  * not support the ExtINT mode, unfortunately.  We need to send these
2108  * cycles as some i82489DX-based boards have glue logic that keeps the
2109  * 8259A interrupt line asserted until INTA.  --macro
2110  */
2111 static inline void unlock_ExtINT_logic(void)
2112 {
2113         int apic, pin, i;
2114         struct IO_APIC_route_entry entry0, entry1;
2115         unsigned char save_control, save_freq_select;
2116
2117         pin  = find_isa_irq_pin(8, mp_INT);
2118         if (pin == -1) {
2119                 WARN_ON_ONCE(1);
2120                 return;
2121         }
2122         apic = find_isa_irq_apic(8, mp_INT);
2123         if (apic == -1) {
2124                 WARN_ON_ONCE(1);
2125                 return;
2126         }
2127
2128         entry0 = ioapic_read_entry(apic, pin);
2129         clear_IO_APIC_pin(apic, pin);
2130
2131         memset(&entry1, 0, sizeof(entry1));
2132
2133         entry1.dest_mode = 0;                   /* physical delivery */
2134         entry1.mask = 0;                        /* unmask IRQ now */
2135         entry1.dest.physical.physical_dest = hard_smp_processor_id();
2136         entry1.delivery_mode = dest_ExtINT;
2137         entry1.polarity = entry0.polarity;
2138         entry1.trigger = 0;
2139         entry1.vector = 0;
2140
2141         ioapic_write_entry(apic, pin, entry1);
2142
2143         save_control = CMOS_READ(RTC_CONTROL);
2144         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2145         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2146                    RTC_FREQ_SELECT);
2147         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2148
2149         i = 100;
2150         while (i-- > 0) {
2151                 mdelay(10);
2152                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2153                         i -= 10;
2154         }
2155
2156         CMOS_WRITE(save_control, RTC_CONTROL);
2157         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2158         clear_IO_APIC_pin(apic, pin);
2159
2160         ioapic_write_entry(apic, pin, entry0);
2161 }
2162
2163 int timer_uses_ioapic_pin_0;
2164
2165 /*
2166  * This code may look a bit paranoid, but it's supposed to cooperate with
2167  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
2168  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
2169  * fanatically on his truly buggy board.
2170  */
2171 static inline void __init check_timer(void)
2172 {
2173         int apic1, pin1, apic2, pin2;
2174         int vector;
2175
2176         /*
2177          * get/set the timer IRQ vector:
2178          */
2179         disable_8259A_irq(0);
2180         vector = assign_irq_vector(0);
2181         set_intr_gate(vector, interrupt[0]);
2182
2183         /*
2184          * Subtle, code in do_timer_interrupt() expects an AEOI
2185          * mode for the 8259A whenever interrupts are routed
2186          * through I/O APICs.  Also IRQ0 has to be enabled in
2187          * the 8259A which implies the virtual wire has to be
2188          * disabled in the local APIC.
2189          */
2190         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2191         init_8259A(1);
2192         timer_ack = 1;
2193         if (timer_over_8254 > 0)
2194                 enable_8259A_irq(0);
2195
2196         pin1  = find_isa_irq_pin(0, mp_INT);
2197         apic1 = find_isa_irq_apic(0, mp_INT);
2198         pin2  = ioapic_i8259.pin;
2199         apic2 = ioapic_i8259.apic;
2200
2201         if (pin1 == 0)
2202                 timer_uses_ioapic_pin_0 = 1;
2203
2204         printk(KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
2205                 vector, apic1, pin1, apic2, pin2);
2206
2207         if (pin1 != -1) {
2208                 /*
2209                  * Ok, does IRQ0 through the IOAPIC work?
2210                  */
2211                 unmask_IO_APIC_irq(0);
2212                 if (timer_irq_works()) {
2213                         if (nmi_watchdog == NMI_IO_APIC) {
2214                                 disable_8259A_irq(0);
2215                                 setup_nmi();
2216                                 enable_8259A_irq(0);
2217                         }
2218                         if (disable_timer_pin_1 > 0)
2219                                 clear_IO_APIC_pin(0, pin1);
2220                         return;
2221                 }
2222                 clear_IO_APIC_pin(apic1, pin1);
2223                 printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to "
2224                                 "IO-APIC\n");
2225         }
2226
2227         printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
2228         if (pin2 != -1) {
2229                 printk("\n..... (found pin %d) ...", pin2);
2230                 /*
2231                  * legacy devices should be connected to IO APIC #0
2232                  */
2233                 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
2234                 if (timer_irq_works()) {
2235                         printk("works.\n");
2236                         if (pin1 != -1)
2237                                 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
2238                         else
2239                                 add_pin_to_irq(0, apic2, pin2);
2240                         if (nmi_watchdog == NMI_IO_APIC) {
2241                                 setup_nmi();
2242                         }
2243                         return;
2244                 }
2245                 /*
2246                  * Cleanup, just in case ...
2247                  */
2248                 clear_IO_APIC_pin(apic2, pin2);
2249         }
2250         printk(" failed.\n");
2251
2252         if (nmi_watchdog == NMI_IO_APIC) {
2253                 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
2254                 nmi_watchdog = 0;
2255         }
2256
2257         printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
2258
2259         disable_8259A_irq(0);
2260         set_irq_chip_and_handler_name(0, &lapic_chip, handle_fasteoi_irq,
2261                                       "fasteoi");
2262         apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector);   /* Fixed mode */
2263         enable_8259A_irq(0);
2264
2265         if (timer_irq_works()) {
2266                 printk(" works.\n");
2267                 return;
2268         }
2269         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
2270         printk(" failed.\n");
2271
2272         printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
2273
2274         timer_ack = 0;
2275         init_8259A(0);
2276         make_8259A_irq(0);
2277         apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
2278
2279         unlock_ExtINT_logic();
2280
2281         if (timer_irq_works()) {
2282                 printk(" works.\n");
2283                 return;
2284         }
2285         printk(" failed :(.\n");
2286         panic("IO-APIC + timer doesn't work!  Boot with apic=debug and send a "
2287                 "report.  Then try booting with the 'noapic' option");
2288 }
2289
2290 /*
2291  *
2292  * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2293  * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2294  *   Linux doesn't really care, as it's not actually used
2295  *   for any interrupt handling anyway.
2296  */
2297 #define PIC_IRQS        (1 << PIC_CASCADE_IR)
2298
2299 void __init setup_IO_APIC(void)
2300 {
2301         enable_IO_APIC();
2302
2303         if (acpi_ioapic)
2304                 io_apic_irqs = ~0;      /* all IRQs go through IOAPIC */
2305         else
2306                 io_apic_irqs = ~PIC_IRQS;
2307
2308         printk("ENABLING IO-APIC IRQs\n");
2309
2310         /*
2311          * Set up IO-APIC IRQ routing.
2312          */
2313         if (!acpi_ioapic)
2314                 setup_ioapic_ids_from_mpc();
2315         sync_Arb_IDs();
2316         setup_IO_APIC_irqs();
2317         init_IO_APIC_traps();
2318         check_timer();
2319         if (!acpi_ioapic)
2320                 print_IO_APIC();
2321 }
2322
2323 static int __init setup_disable_8254_timer(char *s)
2324 {
2325         timer_over_8254 = -1;
2326         return 1;
2327 }
2328 static int __init setup_enable_8254_timer(char *s)
2329 {
2330         timer_over_8254 = 2;
2331         return 1;
2332 }
2333
2334 __setup("disable_8254_timer", setup_disable_8254_timer);
2335 __setup("enable_8254_timer", setup_enable_8254_timer);
2336
2337 /*
2338  *      Called after all the initialization is done. If we didnt find any
2339  *      APIC bugs then we can allow the modify fast path
2340  */
2341  
2342 static int __init io_apic_bug_finalize(void)
2343 {
2344         if(sis_apic_bug == -1)
2345                 sis_apic_bug = 0;
2346         return 0;
2347 }
2348
2349 late_initcall(io_apic_bug_finalize);
2350
2351 struct sysfs_ioapic_data {
2352         struct sys_device dev;
2353         struct IO_APIC_route_entry entry[0];
2354 };
2355 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2356
2357 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2358 {
2359         struct IO_APIC_route_entry *entry;
2360         struct sysfs_ioapic_data *data;
2361         int i;
2362         
2363         data = container_of(dev, struct sysfs_ioapic_data, dev);
2364         entry = data->entry;
2365         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++)
2366                 entry[i] = ioapic_read_entry(dev->id, i);
2367
2368         return 0;
2369 }
2370
2371 static int ioapic_resume(struct sys_device *dev)
2372 {
2373         struct IO_APIC_route_entry *entry;
2374         struct sysfs_ioapic_data *data;
2375         unsigned long flags;
2376         union IO_APIC_reg_00 reg_00;
2377         int i;
2378         
2379         data = container_of(dev, struct sysfs_ioapic_data, dev);
2380         entry = data->entry;
2381
2382         spin_lock_irqsave(&ioapic_lock, flags);
2383         reg_00.raw = io_apic_read(dev->id, 0);
2384         if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
2385                 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
2386                 io_apic_write(dev->id, 0, reg_00.raw);
2387         }
2388         spin_unlock_irqrestore(&ioapic_lock, flags);
2389         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++)
2390                 ioapic_write_entry(dev->id, i, entry[i]);
2391
2392         return 0;
2393 }
2394
2395 static struct sysdev_class ioapic_sysdev_class = {
2396         set_kset_name("ioapic"),
2397         .suspend = ioapic_suspend,
2398         .resume = ioapic_resume,
2399 };
2400
2401 static int __init ioapic_init_sysfs(void)
2402 {
2403         struct sys_device * dev;
2404         int i, size, error = 0;
2405
2406         error = sysdev_class_register(&ioapic_sysdev_class);
2407         if (error)
2408                 return error;
2409
2410         for (i = 0; i < nr_ioapics; i++ ) {
2411                 size = sizeof(struct sys_device) + nr_ioapic_registers[i] 
2412                         * sizeof(struct IO_APIC_route_entry);
2413                 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
2414                 if (!mp_ioapic_data[i]) {
2415                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2416                         continue;
2417                 }
2418                 memset(mp_ioapic_data[i], 0, size);
2419                 dev = &mp_ioapic_data[i]->dev;
2420                 dev->id = i; 
2421                 dev->cls = &ioapic_sysdev_class;
2422                 error = sysdev_register(dev);
2423                 if (error) {
2424                         kfree(mp_ioapic_data[i]);
2425                         mp_ioapic_data[i] = NULL;
2426                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2427                         continue;
2428                 }
2429         }
2430
2431         return 0;
2432 }
2433
2434 device_initcall(ioapic_init_sysfs);
2435
2436 /*
2437  * Dynamic irq allocate and deallocation
2438  */
2439 int create_irq(void)
2440 {
2441         /* Allocate an unused irq */
2442         int irq, new, vector = 0;
2443         unsigned long flags;
2444
2445         irq = -ENOSPC;
2446         spin_lock_irqsave(&vector_lock, flags);
2447         for (new = (NR_IRQS - 1); new >= 0; new--) {
2448                 if (platform_legacy_irq(new))
2449                         continue;
2450                 if (irq_vector[new] != 0)
2451                         continue;
2452                 vector = __assign_irq_vector(new);
2453                 if (likely(vector > 0))
2454                         irq = new;
2455                 break;
2456         }
2457         spin_unlock_irqrestore(&vector_lock, flags);
2458
2459         if (irq >= 0) {
2460                 set_intr_gate(vector, interrupt[irq]);
2461                 dynamic_irq_init(irq);
2462         }
2463         return irq;
2464 }
2465
2466 void destroy_irq(unsigned int irq)
2467 {
2468         unsigned long flags;
2469
2470         dynamic_irq_cleanup(irq);
2471
2472         spin_lock_irqsave(&vector_lock, flags);
2473         irq_vector[irq] = 0;
2474         spin_unlock_irqrestore(&vector_lock, flags);
2475 }
2476
2477 /*
2478  * MSI mesage composition
2479  */
2480 #ifdef CONFIG_PCI_MSI
2481 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
2482 {
2483         int vector;
2484         unsigned dest;
2485
2486         vector = assign_irq_vector(irq);
2487         if (vector >= 0) {
2488                 dest = cpu_mask_to_apicid(TARGET_CPUS);
2489
2490                 msg->address_hi = MSI_ADDR_BASE_HI;
2491                 msg->address_lo =
2492                         MSI_ADDR_BASE_LO |
2493                         ((INT_DEST_MODE == 0) ?
2494                                 MSI_ADDR_DEST_MODE_PHYSICAL:
2495                                 MSI_ADDR_DEST_MODE_LOGICAL) |
2496                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2497                                 MSI_ADDR_REDIRECTION_CPU:
2498                                 MSI_ADDR_REDIRECTION_LOWPRI) |
2499                         MSI_ADDR_DEST_ID(dest);
2500
2501                 msg->data =
2502                         MSI_DATA_TRIGGER_EDGE |
2503                         MSI_DATA_LEVEL_ASSERT |
2504                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2505                                 MSI_DATA_DELIVERY_FIXED:
2506                                 MSI_DATA_DELIVERY_LOWPRI) |
2507                         MSI_DATA_VECTOR(vector);
2508         }
2509         return vector;
2510 }
2511
2512 #ifdef CONFIG_SMP
2513 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
2514 {
2515         struct msi_msg msg;
2516         unsigned int dest;
2517         cpumask_t tmp;
2518         int vector;
2519
2520         cpus_and(tmp, mask, cpu_online_map);
2521         if (cpus_empty(tmp))
2522                 tmp = TARGET_CPUS;
2523
2524         vector = assign_irq_vector(irq);
2525         if (vector < 0)
2526                 return;
2527
2528         dest = cpu_mask_to_apicid(mask);
2529
2530         read_msi_msg(irq, &msg);
2531
2532         msg.data &= ~MSI_DATA_VECTOR_MASK;
2533         msg.data |= MSI_DATA_VECTOR(vector);
2534         msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2535         msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2536
2537         write_msi_msg(irq, &msg);
2538         irq_desc[irq].affinity = mask;
2539 }
2540 #endif /* CONFIG_SMP */
2541
2542 /*
2543  * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2544  * which implement the MSI or MSI-X Capability Structure.
2545  */
2546 static struct irq_chip msi_chip = {
2547         .name           = "PCI-MSI",
2548         .unmask         = unmask_msi_irq,
2549         .mask           = mask_msi_irq,
2550         .ack            = ack_ioapic_irq,
2551 #ifdef CONFIG_SMP
2552         .set_affinity   = set_msi_irq_affinity,
2553 #endif
2554         .retrigger      = ioapic_retrigger_irq,
2555 };
2556
2557 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
2558 {
2559         struct msi_msg msg;
2560         int irq, ret;
2561         irq = create_irq();
2562         if (irq < 0)
2563                 return irq;
2564
2565         ret = msi_compose_msg(dev, irq, &msg);
2566         if (ret < 0) {
2567                 destroy_irq(irq);
2568                 return ret;
2569         }
2570
2571         set_irq_msi(irq, desc);
2572         write_msi_msg(irq, &msg);
2573
2574         set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq,
2575                                       "edge");
2576
2577         return 0;
2578 }
2579
2580 void arch_teardown_msi_irq(unsigned int irq)
2581 {
2582         destroy_irq(irq);
2583 }
2584
2585 #endif /* CONFIG_PCI_MSI */
2586
2587 /*
2588  * Hypertransport interrupt support
2589  */
2590 #ifdef CONFIG_HT_IRQ
2591
2592 #ifdef CONFIG_SMP
2593
2594 static void target_ht_irq(unsigned int irq, unsigned int dest)
2595 {
2596         struct ht_irq_msg msg;
2597         fetch_ht_irq_msg(irq, &msg);
2598
2599         msg.address_lo &= ~(HT_IRQ_LOW_DEST_ID_MASK);
2600         msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
2601
2602         msg.address_lo |= HT_IRQ_LOW_DEST_ID(dest);
2603         msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
2604
2605         write_ht_irq_msg(irq, &msg);
2606 }
2607
2608 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
2609 {
2610         unsigned int dest;
2611         cpumask_t tmp;
2612
2613         cpus_and(tmp, mask, cpu_online_map);
2614         if (cpus_empty(tmp))
2615                 tmp = TARGET_CPUS;
2616
2617         cpus_and(mask, tmp, CPU_MASK_ALL);
2618
2619         dest = cpu_mask_to_apicid(mask);
2620
2621         target_ht_irq(irq, dest);
2622         irq_desc[irq].affinity = mask;
2623 }
2624 #endif
2625
2626 static struct irq_chip ht_irq_chip = {
2627         .name           = "PCI-HT",
2628         .mask           = mask_ht_irq,
2629         .unmask         = unmask_ht_irq,
2630         .ack            = ack_ioapic_irq,
2631 #ifdef CONFIG_SMP
2632         .set_affinity   = set_ht_irq_affinity,
2633 #endif
2634         .retrigger      = ioapic_retrigger_irq,
2635 };
2636
2637 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2638 {
2639         int vector;
2640
2641         vector = assign_irq_vector(irq);
2642         if (vector >= 0) {
2643                 struct ht_irq_msg msg;
2644                 unsigned dest;
2645                 cpumask_t tmp;
2646
2647                 cpus_clear(tmp);
2648                 cpu_set(vector >> 8, tmp);
2649                 dest = cpu_mask_to_apicid(tmp);
2650
2651                 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
2652
2653                 msg.address_lo =
2654                         HT_IRQ_LOW_BASE |
2655                         HT_IRQ_LOW_DEST_ID(dest) |
2656                         HT_IRQ_LOW_VECTOR(vector) |
2657                         ((INT_DEST_MODE == 0) ?
2658                                 HT_IRQ_LOW_DM_PHYSICAL :
2659                                 HT_IRQ_LOW_DM_LOGICAL) |
2660                         HT_IRQ_LOW_RQEOI_EDGE |
2661                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2662                                 HT_IRQ_LOW_MT_FIXED :
2663                                 HT_IRQ_LOW_MT_ARBITRATED) |
2664                         HT_IRQ_LOW_IRQ_MASKED;
2665
2666                 write_ht_irq_msg(irq, &msg);
2667
2668                 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2669                                               handle_edge_irq, "edge");
2670         }
2671         return vector;
2672 }
2673 #endif /* CONFIG_HT_IRQ */
2674
2675 /* --------------------------------------------------------------------------
2676                           ACPI-based IOAPIC Configuration
2677    -------------------------------------------------------------------------- */
2678
2679 #ifdef CONFIG_ACPI
2680
2681 int __init io_apic_get_unique_id (int ioapic, int apic_id)
2682 {
2683         union IO_APIC_reg_00 reg_00;
2684         static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2685         physid_mask_t tmp;
2686         unsigned long flags;
2687         int i = 0;
2688
2689         /*
2690          * The P4 platform supports up to 256 APIC IDs on two separate APIC 
2691          * buses (one for LAPICs, one for IOAPICs), where predecessors only 
2692          * supports up to 16 on one shared APIC bus.
2693          * 
2694          * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2695          *      advantage of new APIC bus architecture.
2696          */
2697
2698         if (physids_empty(apic_id_map))
2699                 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
2700
2701         spin_lock_irqsave(&ioapic_lock, flags);
2702         reg_00.raw = io_apic_read(ioapic, 0);
2703         spin_unlock_irqrestore(&ioapic_lock, flags);
2704
2705         if (apic_id >= get_physical_broadcast()) {
2706                 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2707                         "%d\n", ioapic, apic_id, reg_00.bits.ID);
2708                 apic_id = reg_00.bits.ID;
2709         }
2710
2711         /*
2712          * Every APIC in a system must have a unique ID or we get lots of nice 
2713          * 'stuck on smp_invalidate_needed IPI wait' messages.
2714          */
2715         if (check_apicid_used(apic_id_map, apic_id)) {
2716
2717                 for (i = 0; i < get_physical_broadcast(); i++) {
2718                         if (!check_apicid_used(apic_id_map, i))
2719                                 break;
2720                 }
2721
2722                 if (i == get_physical_broadcast())
2723                         panic("Max apic_id exceeded!\n");
2724
2725                 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2726                         "trying %d\n", ioapic, apic_id, i);
2727
2728                 apic_id = i;
2729         } 
2730
2731         tmp = apicid_to_cpu_present(apic_id);
2732         physids_or(apic_id_map, apic_id_map, tmp);
2733
2734         if (reg_00.bits.ID != apic_id) {
2735                 reg_00.bits.ID = apic_id;
2736
2737                 spin_lock_irqsave(&ioapic_lock, flags);
2738                 io_apic_write(ioapic, 0, reg_00.raw);
2739                 reg_00.raw = io_apic_read(ioapic, 0);
2740                 spin_unlock_irqrestore(&ioapic_lock, flags);
2741
2742                 /* Sanity check */
2743                 if (reg_00.bits.ID != apic_id) {
2744                         printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
2745                         return -1;
2746                 }
2747         }
2748
2749         apic_printk(APIC_VERBOSE, KERN_INFO
2750                         "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2751
2752         return apic_id;
2753 }
2754
2755
2756 int __init io_apic_get_version (int ioapic)
2757 {
2758         union IO_APIC_reg_01    reg_01;
2759         unsigned long flags;
2760
2761         spin_lock_irqsave(&ioapic_lock, flags);
2762         reg_01.raw = io_apic_read(ioapic, 1);
2763         spin_unlock_irqrestore(&ioapic_lock, flags);
2764
2765         return reg_01.bits.version;
2766 }
2767
2768
2769 int __init io_apic_get_redir_entries (int ioapic)
2770 {
2771         union IO_APIC_reg_01    reg_01;
2772         unsigned long flags;
2773
2774         spin_lock_irqsave(&ioapic_lock, flags);
2775         reg_01.raw = io_apic_read(ioapic, 1);
2776         spin_unlock_irqrestore(&ioapic_lock, flags);
2777
2778         return reg_01.bits.entries;
2779 }
2780
2781
2782 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
2783 {
2784         struct IO_APIC_route_entry entry;
2785         unsigned long flags;
2786
2787         if (!IO_APIC_IRQ(irq)) {
2788                 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2789                         ioapic);
2790                 return -EINVAL;
2791         }
2792
2793         /*
2794          * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2795          * Note that we mask (disable) IRQs now -- these get enabled when the
2796          * corresponding device driver registers for this IRQ.
2797          */
2798
2799         memset(&entry,0,sizeof(entry));
2800
2801         entry.delivery_mode = INT_DELIVERY_MODE;
2802         entry.dest_mode = INT_DEST_MODE;
2803         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2804         entry.trigger = edge_level;
2805         entry.polarity = active_high_low;
2806         entry.mask  = 1;
2807
2808         /*
2809          * IRQs < 16 are already in the irq_2_pin[] map
2810          */
2811         if (irq >= 16)
2812                 add_pin_to_irq(irq, ioapic, pin);
2813
2814         entry.vector = assign_irq_vector(irq);
2815
2816         apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry "
2817                 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic,
2818                 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2819                 edge_level, active_high_low);
2820
2821         ioapic_register_intr(irq, entry.vector, edge_level);
2822
2823         if (!ioapic && (irq < 16))
2824                 disable_8259A_irq(irq);
2825
2826         spin_lock_irqsave(&ioapic_lock, flags);
2827         __ioapic_write_entry(ioapic, pin, entry);
2828         spin_unlock_irqrestore(&ioapic_lock, flags);
2829
2830         return 0;
2831 }
2832
2833 #endif /* CONFIG_ACPI */
2834
2835 static int __init parse_disable_timer_pin_1(char *arg)
2836 {
2837         disable_timer_pin_1 = 1;
2838         return 0;
2839 }
2840 early_param("disable_timer_pin_1", parse_disable_timer_pin_1);
2841
2842 static int __init parse_enable_timer_pin_1(char *arg)
2843 {
2844         disable_timer_pin_1 = -1;
2845         return 0;
2846 }
2847 early_param("enable_timer_pin_1", parse_enable_timer_pin_1);
2848
2849 static int __init parse_noapic(char *arg)
2850 {
2851         /* disable IO-APIC */
2852         disable_ioapic_setup();
2853         return 0;
2854 }
2855 early_param("noapic", parse_noapic);