Revert "[CPUFREQ] constify cpufreq_driver where possible."
[linux-2.6.git] / arch / i386 / kernel / cpu / cpufreq / longhaul.c
1 /*
2  *  (C) 2001-2004  Dave Jones. <davej@codemonkey.org.uk>
3  *  (C) 2002  Padraig Brady. <padraig@antefacto.com>
4  *
5  *  Licensed under the terms of the GNU GPL License version 2.
6  *  Based upon datasheets & sample CPUs kindly provided by VIA.
7  *
8  *  VIA have currently 3 different versions of Longhaul.
9  *  Version 1 (Longhaul) uses the BCR2 MSR at 0x1147.
10  *   It is present only in Samuel 1 (C5A), Samuel 2 (C5B) stepping 0.
11  *  Version 2 of longhaul is backward compatible with v1, but adds
12  *   LONGHAUL MSR for purpose of both frequency and voltage scaling.
13  *   Present in Samuel 2 (steppings 1-7 only) (C5B), and Ezra (C5C).
14  *  Version 3 of longhaul got renamed to Powersaver and redesigned
15  *   to use only the POWERSAVER MSR at 0x110a.
16  *   It is present in Ezra-T (C5M), Nehemiah (C5X) and above.
17  *   It's pretty much the same feature wise to longhaul v2, though
18  *   there is provision for scaling FSB too, but this doesn't work
19  *   too well in practice so we don't even try to use this.
20  *
21  *  BIG FAT DISCLAIMER: Work in progress code. Possibly *dangerous*
22  */
23
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/moduleparam.h>
27 #include <linux/init.h>
28 #include <linux/cpufreq.h>
29 #include <linux/pci.h>
30 #include <linux/slab.h>
31 #include <linux/string.h>
32
33 #include <asm/msr.h>
34 #include <asm/timex.h>
35 #include <asm/io.h>
36 #include <asm/acpi.h>
37 #include <linux/acpi.h>
38 #include <acpi/processor.h>
39
40 #include "longhaul.h"
41
42 #define PFX "longhaul: "
43
44 #define TYPE_LONGHAUL_V1        1
45 #define TYPE_LONGHAUL_V2        2
46 #define TYPE_POWERSAVER         3
47
48 #define CPU_SAMUEL      1
49 #define CPU_SAMUEL2     2
50 #define CPU_EZRA        3
51 #define CPU_EZRA_T      4
52 #define CPU_NEHEMIAH    5
53 #define CPU_NEHEMIAH_C  6
54
55 /* Flags */
56 #define USE_ACPI_C3             (1 << 1)
57 #define USE_NORTHBRIDGE         (1 << 2)
58 #define USE_VT8235              (1 << 3)
59
60 static int cpu_model;
61 static unsigned int numscales=16;
62 static unsigned int fsb;
63
64 static const struct mV_pos *vrm_mV_table;
65 static const unsigned char *mV_vrm_table;
66 struct f_msr {
67         u8 vrm;
68         u8 pos;
69 };
70 static struct f_msr f_msr_table[32];
71
72 static unsigned int highest_speed, lowest_speed; /* kHz */
73 static unsigned int minmult, maxmult;
74 static int can_scale_voltage;
75 static struct acpi_processor *pr = NULL;
76 static struct acpi_processor_cx *cx = NULL;
77 static u8 longhaul_flags;
78 static u8 longhaul_pos;
79
80 /* Module parameters */
81 static int scale_voltage;
82
83 #define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "longhaul", msg)
84
85
86 /* Clock ratios multiplied by 10 */
87 static int clock_ratio[32];
88 static int eblcr_table[32];
89 static int longhaul_version;
90 static struct cpufreq_frequency_table *longhaul_table;
91
92 #ifdef CONFIG_CPU_FREQ_DEBUG
93 static char speedbuffer[8];
94
95 static char *print_speed(int speed)
96 {
97         if (speed < 1000) {
98                 snprintf(speedbuffer, sizeof(speedbuffer),"%dMHz", speed);
99                 return speedbuffer;
100         }
101
102         if (speed%1000 == 0)
103                 snprintf(speedbuffer, sizeof(speedbuffer),
104                         "%dGHz", speed/1000);
105         else
106                 snprintf(speedbuffer, sizeof(speedbuffer),
107                         "%d.%dGHz", speed/1000, (speed%1000)/100);
108
109         return speedbuffer;
110 }
111 #endif
112
113
114 static unsigned int calc_speed(int mult)
115 {
116         int khz;
117         khz = (mult/10)*fsb;
118         if (mult%10)
119                 khz += fsb/2;
120         khz *= 1000;
121         return khz;
122 }
123
124
125 static int longhaul_get_cpu_mult(void)
126 {
127         unsigned long invalue=0,lo, hi;
128
129         rdmsr (MSR_IA32_EBL_CR_POWERON, lo, hi);
130         invalue = (lo & (1<<22|1<<23|1<<24|1<<25)) >>22;
131         if (longhaul_version==TYPE_LONGHAUL_V2 || longhaul_version==TYPE_POWERSAVER) {
132                 if (lo & (1<<27))
133                         invalue+=16;
134         }
135         return eblcr_table[invalue];
136 }
137
138 /* For processor with BCR2 MSR */
139
140 static void do_longhaul1(unsigned int clock_ratio_index)
141 {
142         union msr_bcr2 bcr2;
143
144         rdmsrl(MSR_VIA_BCR2, bcr2.val);
145         /* Enable software clock multiplier */
146         bcr2.bits.ESOFTBF = 1;
147         bcr2.bits.CLOCKMUL = clock_ratio_index;
148
149         /* Sync to timer tick */
150         safe_halt();
151         /* Change frequency on next halt or sleep */
152         wrmsrl(MSR_VIA_BCR2, bcr2.val);
153         /* Invoke transition */
154         ACPI_FLUSH_CPU_CACHE();
155         halt();
156
157         /* Disable software clock multiplier */
158         local_irq_disable();
159         rdmsrl(MSR_VIA_BCR2, bcr2.val);
160         bcr2.bits.ESOFTBF = 0;
161         wrmsrl(MSR_VIA_BCR2, bcr2.val);
162 }
163
164 /* For processor with Longhaul MSR */
165
166 static void do_powersaver(int cx_address, unsigned int clock_ratio_index)
167 {
168         union msr_longhaul longhaul;
169         u8 dest_pos;
170         u32 t;
171
172         dest_pos = f_msr_table[clock_ratio_index].pos;
173
174         rdmsrl(MSR_VIA_LONGHAUL, longhaul.val);
175         /* Setup new frequency */
176         longhaul.bits.RevisionKey = longhaul.bits.RevisionID;
177         longhaul.bits.SoftBusRatio = clock_ratio_index & 0xf;
178         longhaul.bits.SoftBusRatio4 = (clock_ratio_index & 0x10) >> 4;
179         /* Setup new voltage */
180         if (can_scale_voltage)
181                 longhaul.bits.SoftVID = f_msr_table[clock_ratio_index].vrm;
182         /* Sync to timer tick */
183         safe_halt();
184         /* Raise voltage if necessary */
185         if (can_scale_voltage && longhaul_pos < dest_pos) {
186                 longhaul.bits.EnableSoftVID = 1;
187                 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
188                 /* Change voltage */
189                 if (!cx_address) {
190                         ACPI_FLUSH_CPU_CACHE();
191                         halt();
192                 } else {
193                         ACPI_FLUSH_CPU_CACHE();
194                         /* Invoke C3 */
195                         inb(cx_address);
196                         /* Dummy op - must do something useless after P_LVL3
197                          * read */
198                         t = inl(acpi_gbl_FADT.xpm_timer_block.address);
199                 }
200                 longhaul.bits.EnableSoftVID = 0;
201                 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
202                 longhaul_pos = dest_pos;
203         }
204
205         /* Change frequency on next halt or sleep */
206         longhaul.bits.EnableSoftBusRatio = 1;
207         wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
208         if (!cx_address) {
209                 ACPI_FLUSH_CPU_CACHE();
210                 halt();
211         } else {
212                 ACPI_FLUSH_CPU_CACHE();
213                 /* Invoke C3 */
214                 inb(cx_address);
215                 /* Dummy op - must do something useless after P_LVL3 read */
216                 t = inl(acpi_gbl_FADT.xpm_timer_block.address);
217         }
218         /* Disable bus ratio bit */
219         longhaul.bits.EnableSoftBusRatio = 0;
220         wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
221
222         /* Reduce voltage if necessary */
223         if (can_scale_voltage && longhaul_pos > dest_pos) {
224                 longhaul.bits.EnableSoftVID = 1;
225                 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
226                 /* Change voltage */
227                 if (!cx_address) {
228                         ACPI_FLUSH_CPU_CACHE();
229                         halt();
230                 } else {
231                         ACPI_FLUSH_CPU_CACHE();
232                         /* Invoke C3 */
233                         inb(cx_address);
234                         /* Dummy op - must do something useless after P_LVL3
235                          * read */
236                         t = inl(acpi_gbl_FADT.xpm_timer_block.address);
237                 }
238                 longhaul.bits.EnableSoftVID = 0;
239                 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
240                 longhaul_pos = dest_pos;
241         }
242 }
243
244 /**
245  * longhaul_set_cpu_frequency()
246  * @clock_ratio_index : bitpattern of the new multiplier.
247  *
248  * Sets a new clock ratio.
249  */
250
251 static void longhaul_setstate(unsigned int clock_ratio_index)
252 {
253         int speed, mult;
254         struct cpufreq_freqs freqs;
255         static unsigned int old_ratio=-1;
256         unsigned long flags;
257         unsigned int pic1_mask, pic2_mask;
258
259         if (old_ratio == clock_ratio_index)
260                 return;
261         old_ratio = clock_ratio_index;
262
263         mult = clock_ratio[clock_ratio_index];
264         if (mult == -1)
265                 return;
266
267         speed = calc_speed(mult);
268         if ((speed > highest_speed) || (speed < lowest_speed))
269                 return;
270
271         freqs.old = calc_speed(longhaul_get_cpu_mult());
272         freqs.new = speed;
273         freqs.cpu = 0; /* longhaul.c is UP only driver */
274
275         cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
276
277         dprintk ("Setting to FSB:%dMHz Mult:%d.%dx (%s)\n",
278                         fsb, mult/10, mult%10, print_speed(speed/1000));
279
280         preempt_disable();
281         local_irq_save(flags);
282
283         pic2_mask = inb(0xA1);
284         pic1_mask = inb(0x21);  /* works on C3. save mask. */
285         outb(0xFF,0xA1);        /* Overkill */
286         outb(0xFE,0x21);        /* TMR0 only */
287
288         if (longhaul_flags & USE_NORTHBRIDGE) {
289                 /* Disable AGP and PCI arbiters */
290                 outb(3, 0x22);
291         } else if ((pr != NULL) && pr->flags.bm_control) {
292                 /* Disable bus master arbitration */
293                 acpi_set_register(ACPI_BITREG_ARB_DISABLE, 1);
294         }
295         switch (longhaul_version) {
296
297         /*
298          * Longhaul v1. (Samuel[C5A] and Samuel2 stepping 0[C5B])
299          * Software controlled multipliers only.
300          */
301         case TYPE_LONGHAUL_V1:
302                 do_longhaul1(clock_ratio_index);
303                 break;
304
305         /*
306          * Longhaul v2 appears in Samuel2 Steppings 1->7 [C5B] and Ezra [C5C]
307          *
308          * Longhaul v3 (aka Powersaver). (Ezra-T [C5M] & Nehemiah [C5N])
309          * Nehemiah can do FSB scaling too, but this has never been proven
310          * to work in practice.
311          */
312         case TYPE_LONGHAUL_V2:
313         case TYPE_POWERSAVER:
314                 if (longhaul_flags & USE_ACPI_C3) {
315                         /* Don't allow wakeup */
316                         acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 0);
317                         do_powersaver(cx->address, clock_ratio_index);
318                 } else {
319                         do_powersaver(0, clock_ratio_index);
320                 }
321                 break;
322         }
323
324         if (longhaul_flags & USE_NORTHBRIDGE) {
325                 /* Enable arbiters */
326                 outb(0, 0x22);
327         } else if ((pr != NULL) && pr->flags.bm_control) {
328                 /* Enable bus master arbitration */
329                 acpi_set_register(ACPI_BITREG_ARB_DISABLE, 0);
330         }
331         outb(pic2_mask,0xA1);   /* restore mask */
332         outb(pic1_mask,0x21);
333
334         local_irq_restore(flags);
335         preempt_enable();
336
337         freqs.new = calc_speed(longhaul_get_cpu_mult());
338         cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
339 }
340
341 /*
342  * Centaur decided to make life a little more tricky.
343  * Only longhaul v1 is allowed to read EBLCR BSEL[0:1].
344  * Samuel2 and above have to try and guess what the FSB is.
345  * We do this by assuming we booted at maximum multiplier, and interpolate
346  * between that value multiplied by possible FSBs and cpu_mhz which
347  * was calculated at boot time. Really ugly, but no other way to do this.
348  */
349
350 #define ROUNDING        0xf
351
352 static int guess_fsb(int mult)
353 {
354         int speed = cpu_khz / 1000;
355         int i;
356         int speeds[] = { 666, 1000, 1333, 2000 };
357         int f_max, f_min;
358
359         for (i = 0; i < 4; i++) {
360                 f_max = ((speeds[i] * mult) + 50) / 100;
361                 f_max += (ROUNDING / 2);
362                 f_min = f_max - ROUNDING;
363                 if ((speed <= f_max) && (speed >= f_min))
364                         return speeds[i] / 10;
365         }
366         return 0;
367 }
368
369
370 static int __init longhaul_get_ranges(void)
371 {
372         unsigned int j, k = 0;
373         int mult;
374
375         /* Get current frequency */
376         mult = longhaul_get_cpu_mult();
377         if (mult == -1) {
378                 printk(KERN_INFO PFX "Invalid (reserved) multiplier!\n");
379                 return -EINVAL;
380         }
381         fsb = guess_fsb(mult);
382         if (fsb == 0) {
383                 printk(KERN_INFO PFX "Invalid (reserved) FSB!\n");
384                 return -EINVAL;
385         }
386         /* Get max multiplier - as we always did.
387          * Longhaul MSR is usefull only when voltage scaling is enabled.
388          * C3 is booting at max anyway. */
389         maxmult = mult;
390         /* Get min multiplier */
391         switch (cpu_model) {
392         case CPU_NEHEMIAH:
393                 minmult = 50;
394                 break;
395         case CPU_NEHEMIAH_C:
396                 minmult = 40;
397                 break;
398         default:
399                 minmult = 30;
400                 break;
401         }
402
403         dprintk ("MinMult:%d.%dx MaxMult:%d.%dx\n",
404                  minmult/10, minmult%10, maxmult/10, maxmult%10);
405
406         highest_speed = calc_speed(maxmult);
407         lowest_speed = calc_speed(minmult);
408         dprintk ("FSB:%dMHz  Lowest speed: %s   Highest speed:%s\n", fsb,
409                  print_speed(lowest_speed/1000),
410                  print_speed(highest_speed/1000));
411
412         if (lowest_speed == highest_speed) {
413                 printk (KERN_INFO PFX "highestspeed == lowest, aborting.\n");
414                 return -EINVAL;
415         }
416         if (lowest_speed > highest_speed) {
417                 printk (KERN_INFO PFX "nonsense! lowest (%d > %d) !\n",
418                         lowest_speed, highest_speed);
419                 return -EINVAL;
420         }
421
422         longhaul_table = kmalloc((numscales + 1) * sizeof(struct cpufreq_frequency_table), GFP_KERNEL);
423         if(!longhaul_table)
424                 return -ENOMEM;
425
426         for (j=0; j < numscales; j++) {
427                 unsigned int ratio;
428                 ratio = clock_ratio[j];
429                 if (ratio == -1)
430                         continue;
431                 if (ratio > maxmult || ratio < minmult)
432                         continue;
433                 longhaul_table[k].frequency = calc_speed(ratio);
434                 longhaul_table[k].index = j;
435                 k++;
436         }
437
438         longhaul_table[k].frequency = CPUFREQ_TABLE_END;
439         if (!k) {
440                 kfree (longhaul_table);
441                 return -EINVAL;
442         }
443
444         return 0;
445 }
446
447
448 static void __init longhaul_setup_voltagescaling(void)
449 {
450         union msr_longhaul longhaul;
451         struct mV_pos minvid, maxvid;
452         unsigned int j, speed, pos, kHz_step, numvscales;
453         int min_vid_speed;
454
455         rdmsrl(MSR_VIA_LONGHAUL, longhaul.val);
456         if (!(longhaul.bits.RevisionID & 1)) {
457                 printk(KERN_INFO PFX "Voltage scaling not supported by CPU.\n");
458                 return;
459         }
460
461         if (!longhaul.bits.VRMRev) {
462                 printk (KERN_INFO PFX "VRM 8.5\n");
463                 vrm_mV_table = &vrm85_mV[0];
464                 mV_vrm_table = &mV_vrm85[0];
465         } else {
466                 printk (KERN_INFO PFX "Mobile VRM\n");
467                 if (cpu_model < CPU_NEHEMIAH)
468                         return;
469                 vrm_mV_table = &mobilevrm_mV[0];
470                 mV_vrm_table = &mV_mobilevrm[0];
471         }
472
473         minvid = vrm_mV_table[longhaul.bits.MinimumVID];
474         maxvid = vrm_mV_table[longhaul.bits.MaximumVID];
475
476         if (minvid.mV == 0 || maxvid.mV == 0 || minvid.mV > maxvid.mV) {
477                 printk (KERN_INFO PFX "Bogus values Min:%d.%03d Max:%d.%03d. "
478                                         "Voltage scaling disabled.\n",
479                                         minvid.mV/1000, minvid.mV%1000, maxvid.mV/1000, maxvid.mV%1000);
480                 return;
481         }
482
483         if (minvid.mV == maxvid.mV) {
484                 printk (KERN_INFO PFX "Claims to support voltage scaling but min & max are "
485                                 "both %d.%03d. Voltage scaling disabled\n",
486                                 maxvid.mV/1000, maxvid.mV%1000);
487                 return;
488         }
489
490         /* How many voltage steps */
491         numvscales = maxvid.pos - minvid.pos + 1;
492         printk(KERN_INFO PFX
493                 "Max VID=%d.%03d  "
494                 "Min VID=%d.%03d, "
495                 "%d possible voltage scales\n",
496                 maxvid.mV/1000, maxvid.mV%1000,
497                 minvid.mV/1000, minvid.mV%1000,
498                 numvscales);
499
500         /* Calculate max frequency at min voltage */
501         j = longhaul.bits.MinMHzBR;
502         if (longhaul.bits.MinMHzBR4)
503                 j += 16;
504         min_vid_speed = eblcr_table[j];
505         if (min_vid_speed == -1)
506                 return;
507         switch (longhaul.bits.MinMHzFSB) {
508         case 0:
509                 min_vid_speed *= 13333;
510                 break;
511         case 1:
512                 min_vid_speed *= 10000;
513                 break;
514         case 3:
515                 min_vid_speed *= 6666;
516                 break;
517         default:
518                 return;
519                 break;
520         }
521         if (min_vid_speed >= highest_speed)
522                 return;
523         /* Calculate kHz for one voltage step */
524         kHz_step = (highest_speed - min_vid_speed) / numvscales;
525
526
527         j = 0;
528         while (longhaul_table[j].frequency != CPUFREQ_TABLE_END) {
529                 speed = longhaul_table[j].frequency;
530                 if (speed > min_vid_speed)
531                         pos = (speed - min_vid_speed) / kHz_step + minvid.pos;
532                 else
533                         pos = minvid.pos;
534                 f_msr_table[longhaul_table[j].index].vrm = mV_vrm_table[pos];
535                 f_msr_table[longhaul_table[j].index].pos = pos;
536                 j++;
537         }
538
539         longhaul_pos = maxvid.pos;
540         can_scale_voltage = 1;
541         printk(KERN_INFO PFX "Voltage scaling enabled. "
542                 "Use of \"conservative\" governor is highly recommended.\n");
543 }
544
545
546 static int longhaul_verify(struct cpufreq_policy *policy)
547 {
548         return cpufreq_frequency_table_verify(policy, longhaul_table);
549 }
550
551
552 static int longhaul_target(struct cpufreq_policy *policy,
553                             unsigned int target_freq, unsigned int relation)
554 {
555         unsigned int table_index = 0;
556         unsigned int new_clock_ratio = 0;
557
558         if (cpufreq_frequency_table_target(policy, longhaul_table, target_freq, relation, &table_index))
559                 return -EINVAL;
560
561         new_clock_ratio = longhaul_table[table_index].index & 0xFF;
562
563         longhaul_setstate(new_clock_ratio);
564
565         return 0;
566 }
567
568
569 static unsigned int longhaul_get(unsigned int cpu)
570 {
571         if (cpu)
572                 return 0;
573         return calc_speed(longhaul_get_cpu_mult());
574 }
575
576 static acpi_status longhaul_walk_callback(acpi_handle obj_handle,
577                                           u32 nesting_level,
578                                           void *context, void **return_value)
579 {
580         struct acpi_device *d;
581
582         if ( acpi_bus_get_device(obj_handle, &d) ) {
583                 return 0;
584         }
585         *return_value = (void *)acpi_driver_data(d);
586         return 1;
587 }
588
589 /* VIA don't support PM2 reg, but have something similar */
590 static int enable_arbiter_disable(void)
591 {
592         struct pci_dev *dev;
593         int reg;
594         u8 pci_cmd;
595
596         /* Find PLE133 host bridge */
597         reg = 0x78;
598         dev = pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8601_0, NULL);
599         /* Find CLE266 host bridge */
600         if (dev == NULL) {
601                 reg = 0x76;
602                 dev = pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_862X_0, NULL);
603                 /* Find CN400 V-Link host bridge */
604                 if (dev == NULL)
605                         dev = pci_find_device(PCI_VENDOR_ID_VIA, 0x7259, NULL);
606
607         }
608         if (dev != NULL) {
609                 /* Enable access to port 0x22 */
610                 pci_read_config_byte(dev, reg, &pci_cmd);
611                 if (!(pci_cmd & 1<<7)) {
612                         pci_cmd |= 1<<7;
613                         pci_write_config_byte(dev, reg, pci_cmd);
614                         pci_read_config_byte(dev, reg, &pci_cmd);
615                         if (!(pci_cmd & 1<<7)) {
616                                 printk(KERN_ERR PFX
617                                         "Can't enable access to port 0x22.\n");
618                                 return 0;
619                         }
620                 }
621                 return 1;
622         }
623         return 0;
624 }
625
626 static int longhaul_setup_vt8235(void)
627 {
628         struct pci_dev *dev;
629         u8 pci_cmd;
630
631         /* Find VT8235 southbridge */
632         dev = pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, NULL);
633         if (dev != NULL) {
634                 /* Set transition time to max */
635                 pci_read_config_byte(dev, 0xec, &pci_cmd);
636                 pci_cmd &= ~(1 << 2);
637                 pci_write_config_byte(dev, 0xec, pci_cmd);
638                 pci_read_config_byte(dev, 0xe4, &pci_cmd);
639                 pci_cmd &= ~(1 << 7);
640                 pci_write_config_byte(dev, 0xe4, pci_cmd);
641                 pci_read_config_byte(dev, 0xe5, &pci_cmd);
642                 pci_cmd |= 1 << 7;
643                 pci_write_config_byte(dev, 0xe5, pci_cmd);
644                 return 1;
645         }
646         return 0;
647 }
648
649 static int __init longhaul_cpu_init(struct cpufreq_policy *policy)
650 {
651         struct cpuinfo_x86 *c = cpu_data;
652         char *cpuname=NULL;
653         int ret;
654         u32 lo, hi;
655         int vt8235_present;
656
657         /* Check what we have on this motherboard */
658         switch (c->x86_model) {
659         case 6:
660                 cpu_model = CPU_SAMUEL;
661                 cpuname = "C3 'Samuel' [C5A]";
662                 longhaul_version = TYPE_LONGHAUL_V1;
663                 memcpy (clock_ratio, samuel1_clock_ratio, sizeof(samuel1_clock_ratio));
664                 memcpy (eblcr_table, samuel1_eblcr, sizeof(samuel1_eblcr));
665                 break;
666
667         case 7:
668                 switch (c->x86_mask) {
669                 case 0:
670                         longhaul_version = TYPE_LONGHAUL_V1;
671                         cpu_model = CPU_SAMUEL2;
672                         cpuname = "C3 'Samuel 2' [C5B]";
673                         /* Note, this is not a typo, early Samuel2's had
674                          * Samuel1 ratios. */
675                         memcpy(clock_ratio, samuel1_clock_ratio,
676                                 sizeof(samuel1_clock_ratio));
677                         memcpy(eblcr_table, samuel2_eblcr,
678                                 sizeof(samuel2_eblcr));
679                         break;
680                 case 1 ... 15:
681                         longhaul_version = TYPE_LONGHAUL_V2;
682                         if (c->x86_mask < 8) {
683                                 cpu_model = CPU_SAMUEL2;
684                                 cpuname = "C3 'Samuel 2' [C5B]";
685                         } else {
686                                 cpu_model = CPU_EZRA;
687                                 cpuname = "C3 'Ezra' [C5C]";
688                         }
689                         memcpy(clock_ratio, ezra_clock_ratio,
690                                 sizeof(ezra_clock_ratio));
691                         memcpy(eblcr_table, ezra_eblcr,
692                                 sizeof(ezra_eblcr));
693                         break;
694                 }
695                 break;
696
697         case 8:
698                 cpu_model = CPU_EZRA_T;
699                 cpuname = "C3 'Ezra-T' [C5M]";
700                 longhaul_version = TYPE_POWERSAVER;
701                 numscales=32;
702                 memcpy (clock_ratio, ezrat_clock_ratio, sizeof(ezrat_clock_ratio));
703                 memcpy (eblcr_table, ezrat_eblcr, sizeof(ezrat_eblcr));
704                 break;
705
706         case 9:
707                 longhaul_version = TYPE_POWERSAVER;
708                 numscales = 32;
709                 memcpy(clock_ratio,
710                        nehemiah_clock_ratio,
711                        sizeof(nehemiah_clock_ratio));
712                 memcpy(eblcr_table, nehemiah_eblcr, sizeof(nehemiah_eblcr));
713                 switch (c->x86_mask) {
714                 case 0 ... 1:
715                         cpu_model = CPU_NEHEMIAH;
716                         cpuname = "C3 'Nehemiah A' [C5XLOE]";
717                         break;
718                 case 2 ... 4:
719                         cpu_model = CPU_NEHEMIAH;
720                         cpuname = "C3 'Nehemiah B' [C5XLOH]";
721                         break;
722                 case 5 ... 15:
723                         cpu_model = CPU_NEHEMIAH_C;
724                         cpuname = "C3 'Nehemiah C' [C5P]";
725                         break;
726                 }
727                 break;
728
729         default:
730                 cpuname = "Unknown";
731                 break;
732         }
733         /* Check Longhaul ver. 2 */
734         if (longhaul_version == TYPE_LONGHAUL_V2) {
735                 rdmsr(MSR_VIA_LONGHAUL, lo, hi);
736                 if (lo == 0 && hi == 0)
737                         /* Looks like MSR isn't present */
738                         longhaul_version = TYPE_LONGHAUL_V1;
739         }
740
741         printk (KERN_INFO PFX "VIA %s CPU detected.  ", cpuname);
742         switch (longhaul_version) {
743         case TYPE_LONGHAUL_V1:
744         case TYPE_LONGHAUL_V2:
745                 printk ("Longhaul v%d supported.\n", longhaul_version);
746                 break;
747         case TYPE_POWERSAVER:
748                 printk ("Powersaver supported.\n");
749                 break;
750         };
751
752         /* Doesn't hurt */
753         vt8235_present = longhaul_setup_vt8235();
754
755         /* Find ACPI data for processor */
756         acpi_walk_namespace(ACPI_TYPE_PROCESSOR, ACPI_ROOT_OBJECT,
757                                 ACPI_UINT32_MAX, &longhaul_walk_callback,
758                                 NULL, (void *)&pr);
759
760         /* Check ACPI support for C3 state */
761         if (pr != NULL && longhaul_version != TYPE_LONGHAUL_V1) {
762                 cx = &pr->power.states[ACPI_STATE_C3];
763                 if (cx->address > 0 && cx->latency <= 1000) {
764                         longhaul_flags |= USE_ACPI_C3;
765                         goto print_support_type;
766                 }
767         }
768         /* Check if northbridge is friendly */
769         if (enable_arbiter_disable()) {
770                 longhaul_flags |= USE_NORTHBRIDGE;
771                 goto print_support_type;
772         }
773         /* Use VT8235 southbridge if present */
774         if (longhaul_version == TYPE_POWERSAVER && vt8235_present) {
775                 longhaul_flags |= USE_VT8235;
776                 goto print_support_type;
777         }
778         /* Check ACPI support for bus master arbiter disable */
779         if ((pr == NULL) || !(pr->flags.bm_control)) {
780                 printk(KERN_ERR PFX
781                         "No ACPI support. Unsupported northbridge.\n");
782                 return -ENODEV;
783         }
784
785 print_support_type:
786         if (longhaul_flags & USE_NORTHBRIDGE)
787                 printk (KERN_INFO PFX "Using northbridge support.\n");
788         else if (longhaul_flags & USE_VT8235)
789                 printk (KERN_INFO PFX "Using VT8235 support.\n");
790         else
791                 printk (KERN_INFO PFX "Using ACPI support.\n");
792
793         ret = longhaul_get_ranges();
794         if (ret != 0)
795                 return ret;
796
797         if ((longhaul_version != TYPE_LONGHAUL_V1) && (scale_voltage != 0))
798                 longhaul_setup_voltagescaling();
799
800         policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
801         policy->cpuinfo.transition_latency = 200000;    /* nsec */
802         policy->cur = calc_speed(longhaul_get_cpu_mult());
803
804         ret = cpufreq_frequency_table_cpuinfo(policy, longhaul_table);
805         if (ret)
806                 return ret;
807
808         cpufreq_frequency_table_get_attr(longhaul_table, policy->cpu);
809
810         return 0;
811 }
812
813 static int __devexit longhaul_cpu_exit(struct cpufreq_policy *policy)
814 {
815         cpufreq_frequency_table_put_attr(policy->cpu);
816         return 0;
817 }
818
819 static struct freq_attr* longhaul_attr[] = {
820         &cpufreq_freq_attr_scaling_available_freqs,
821         NULL,
822 };
823
824 static struct cpufreq_driver longhaul_driver = {
825         .verify = longhaul_verify,
826         .target = longhaul_target,
827         .get    = longhaul_get,
828         .init   = longhaul_cpu_init,
829         .exit   = __devexit_p(longhaul_cpu_exit),
830         .name   = "longhaul",
831         .owner  = THIS_MODULE,
832         .attr   = longhaul_attr,
833 };
834
835
836 static int __init longhaul_init(void)
837 {
838         struct cpuinfo_x86 *c = cpu_data;
839
840         if (c->x86_vendor != X86_VENDOR_CENTAUR || c->x86 != 6)
841                 return -ENODEV;
842
843 #ifdef CONFIG_SMP
844         if (num_online_cpus() > 1) {
845                 printk(KERN_ERR PFX "More than 1 CPU detected, longhaul disabled.\n");
846                 return -ENODEV;
847         }
848 #endif
849 #ifdef CONFIG_X86_IO_APIC
850         if (cpu_has_apic) {
851                 printk(KERN_ERR PFX "APIC detected. Longhaul is currently broken in this configuration.\n");
852                 return -ENODEV;
853         }
854 #endif
855         switch (c->x86_model) {
856         case 6 ... 9:
857                 return cpufreq_register_driver(&longhaul_driver);
858         case 10:
859                 printk(KERN_ERR PFX "Use acpi-cpufreq driver for VIA C7\n");
860         default:
861                 ;;
862         }
863
864         return -ENODEV;
865 }
866
867
868 static void __exit longhaul_exit(void)
869 {
870         int i;
871
872         for (i=0; i < numscales; i++) {
873                 if (clock_ratio[i] == maxmult) {
874                         longhaul_setstate(i);
875                         break;
876                 }
877         }
878
879         cpufreq_unregister_driver(&longhaul_driver);
880         kfree(longhaul_table);
881 }
882
883 module_param (scale_voltage, int, 0644);
884 MODULE_PARM_DESC(scale_voltage, "Scale voltage of processor");
885
886 MODULE_AUTHOR ("Dave Jones <davej@codemonkey.org.uk>");
887 MODULE_DESCRIPTION ("Longhaul driver for VIA Cyrix processors.");
888 MODULE_LICENSE ("GPL");
889
890 late_initcall(longhaul_init);
891 module_exit(longhaul_exit);