[PATCH] x86_64: Final support for AMD dual core
[linux-2.6.git] / arch / i386 / kernel / cpu / amd.c
1 #include <linux/init.h>
2 #include <linux/bitops.h>
3 #include <linux/mm.h>
4 #include <asm/io.h>
5 #include <asm/processor.h>
6
7 #include "cpu.h"
8
9 /*
10  *      B step AMD K6 before B 9730xxxx have hardware bugs that can cause
11  *      misexecution of code under Linux. Owners of such processors should
12  *      contact AMD for precise details and a CPU swap.
13  *
14  *      See     http://www.multimania.com/poulot/k6bug.html
15  *              http://www.amd.com/K6/k6docs/revgd.html
16  *
17  *      The following test is erm.. interesting. AMD neglected to up
18  *      the chip setting when fixing the bug but they also tweaked some
19  *      performance at the same time..
20  */
21  
22 extern void vide(void);
23 __asm__(".align 4\nvide: ret");
24
25 static void __init init_amd(struct cpuinfo_x86 *c)
26 {
27 #ifdef CONFIG_SMP
28         int cpu = c == &boot_cpu_data ? 0 : c - cpu_data;
29 #endif
30         u32 l, h;
31         int mbytes = num_physpages >> (20-PAGE_SHIFT);
32         int r;
33
34         /*
35          *      FIXME: We should handle the K5 here. Set up the write
36          *      range and also turn on MSR 83 bits 4 and 31 (write alloc,
37          *      no bus pipeline)
38          */
39
40         /* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
41            3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
42         clear_bit(0*32+31, c->x86_capability);
43         
44         r = get_model_name(c);
45
46         switch(c->x86)
47         {
48                 case 4:
49                 /*
50                  * General Systems BIOSen alias the cpu frequency registers
51                  * of the Elan at 0x000df000. Unfortuantly, one of the Linux
52                  * drivers subsequently pokes it, and changes the CPU speed.
53                  * Workaround : Remove the unneeded alias.
54                  */
55 #define CBAR            (0xfffc) /* Configuration Base Address  (32-bit) */
56 #define CBAR_ENB        (0x80000000)
57 #define CBAR_KEY        (0X000000CB)
58                         if (c->x86_model==9 || c->x86_model == 10) {
59                                 if (inl (CBAR) & CBAR_ENB)
60                                         outl (0 | CBAR_KEY, CBAR);
61                         }
62                         break;
63                 case 5:
64                         if( c->x86_model < 6 )
65                         {
66                                 /* Based on AMD doc 20734R - June 2000 */
67                                 if ( c->x86_model == 0 ) {
68                                         clear_bit(X86_FEATURE_APIC, c->x86_capability);
69                                         set_bit(X86_FEATURE_PGE, c->x86_capability);
70                                 }
71                                 break;
72                         }
73                         
74                         if ( c->x86_model == 6 && c->x86_mask == 1 ) {
75                                 const int K6_BUG_LOOP = 1000000;
76                                 int n;
77                                 void (*f_vide)(void);
78                                 unsigned long d, d2;
79                                 
80                                 printk(KERN_INFO "AMD K6 stepping B detected - ");
81                                 
82                                 /*
83                                  * It looks like AMD fixed the 2.6.2 bug and improved indirect 
84                                  * calls at the same time.
85                                  */
86
87                                 n = K6_BUG_LOOP;
88                                 f_vide = vide;
89                                 rdtscl(d);
90                                 while (n--) 
91                                         f_vide();
92                                 rdtscl(d2);
93                                 d = d2-d;
94                                 
95                                 /* Knock these two lines out if it debugs out ok */
96                                 printk(KERN_INFO "AMD K6 stepping B detected - ");
97                                 /* -- cut here -- */
98                                 if (d > 20*K6_BUG_LOOP) 
99                                         printk("system stability may be impaired when more than 32 MB are used.\n");
100                                 else 
101                                         printk("probably OK (after B9730xxxx).\n");
102                                 printk(KERN_INFO "Please see http://membres.lycos.fr/poulot/k6bug.html\n");
103                         }
104
105                         /* K6 with old style WHCR */
106                         if (c->x86_model < 8 ||
107                            (c->x86_model== 8 && c->x86_mask < 8)) {
108                                 /* We can only write allocate on the low 508Mb */
109                                 if(mbytes>508)
110                                         mbytes=508;
111
112                                 rdmsr(MSR_K6_WHCR, l, h);
113                                 if ((l&0x0000FFFF)==0) {
114                                         unsigned long flags;
115                                         l=(1<<0)|((mbytes/4)<<1);
116                                         local_irq_save(flags);
117                                         wbinvd();
118                                         wrmsr(MSR_K6_WHCR, l, h);
119                                         local_irq_restore(flags);
120                                         printk(KERN_INFO "Enabling old style K6 write allocation for %d Mb\n",
121                                                 mbytes);
122                                 }
123                                 break;
124                         }
125
126                         if ((c->x86_model == 8 && c->x86_mask >7) ||
127                              c->x86_model == 9 || c->x86_model == 13) {
128                                 /* The more serious chips .. */
129
130                                 if(mbytes>4092)
131                                         mbytes=4092;
132
133                                 rdmsr(MSR_K6_WHCR, l, h);
134                                 if ((l&0xFFFF0000)==0) {
135                                         unsigned long flags;
136                                         l=((mbytes>>2)<<22)|(1<<16);
137                                         local_irq_save(flags);
138                                         wbinvd();
139                                         wrmsr(MSR_K6_WHCR, l, h);
140                                         local_irq_restore(flags);
141                                         printk(KERN_INFO "Enabling new style K6 write allocation for %d Mb\n",
142                                                 mbytes);
143                                 }
144
145                                 /*  Set MTRR capability flag if appropriate */
146                                 if (c->x86_model == 13 || c->x86_model == 9 ||
147                                    (c->x86_model == 8 && c->x86_mask >= 8))
148                                         set_bit(X86_FEATURE_K6_MTRR, c->x86_capability);
149                                 break;
150                         }
151                         break;
152
153                 case 6: /* An Athlon/Duron */
154  
155                         /* Bit 15 of Athlon specific MSR 15, needs to be 0
156                          * to enable SSE on Palomino/Morgan/Barton CPU's.
157                          * If the BIOS didn't enable it already, enable it here.
158                          */
159                         if (c->x86_model >= 6 && c->x86_model <= 10) {
160                                 if (!cpu_has(c, X86_FEATURE_XMM)) {
161                                         printk(KERN_INFO "Enabling disabled K7/SSE Support.\n");
162                                         rdmsr(MSR_K7_HWCR, l, h);
163                                         l &= ~0x00008000;
164                                         wrmsr(MSR_K7_HWCR, l, h);
165                                         set_bit(X86_FEATURE_XMM, c->x86_capability);
166                                 }
167                         }
168
169                         /* It's been determined by AMD that Athlons since model 8 stepping 1
170                          * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
171                          * As per AMD technical note 27212 0.2
172                          */
173                         if ((c->x86_model == 8 && c->x86_mask>=1) || (c->x86_model > 8)) {
174                                 rdmsr(MSR_K7_CLK_CTL, l, h);
175                                 if ((l & 0xfff00000) != 0x20000000) {
176                                         printk ("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", l,
177                                                 ((l & 0x000fffff)|0x20000000));
178                                         wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h);
179                                 }
180                         }
181                         break;
182         }
183
184         switch (c->x86) {
185         case 15:
186                 set_bit(X86_FEATURE_K8, c->x86_capability);
187                 break;
188         case 6:
189                 set_bit(X86_FEATURE_K7, c->x86_capability); 
190                 break;
191         }
192
193         display_cacheinfo(c);
194
195         if (cpuid_eax(0x80000000) >= 0x80000008) {
196                 c->x86_num_cores = (cpuid_ecx(0x80000008) & 0xff) + 1;
197                 if (c->x86_num_cores & (c->x86_num_cores - 1))
198                         c->x86_num_cores = 1;
199         }
200
201 #ifdef CONFIG_SMP
202         /*
203          * On a AMD dual core setup the lower bits of the APIC id
204          * distingush the cores.  Assumes number of cores is a power
205          * of two.
206          */
207         if (c->x86_num_cores > 1) {
208                 cpu_core_id[cpu] = cpu >> hweight32(c->x86_num_cores - 1);
209                 printk(KERN_INFO "CPU %d(%d) -> Core %d\n",
210                        cpu, c->x86_num_cores, cpu_core_id[cpu]);
211         }
212 #endif
213 }
214
215 static unsigned int amd_size_cache(struct cpuinfo_x86 * c, unsigned int size)
216 {
217         /* AMD errata T13 (order #21922) */
218         if ((c->x86 == 6)) {
219                 if (c->x86_model == 3 && c->x86_mask == 0)      /* Duron Rev A0 */
220                         size = 64;
221                 if (c->x86_model == 4 &&
222                     (c->x86_mask==0 || c->x86_mask==1)) /* Tbird rev A1/A2 */
223                         size = 256;
224         }
225         return size;
226 }
227
228 static struct cpu_dev amd_cpu_dev __initdata = {
229         .c_vendor       = "AMD",
230         .c_ident        = { "AuthenticAMD" },
231         .c_models = {
232                 { .vendor = X86_VENDOR_AMD, .family = 4, .model_names =
233                   {
234                           [3] = "486 DX/2",
235                           [7] = "486 DX/2-WB",
236                           [8] = "486 DX/4", 
237                           [9] = "486 DX/4-WB", 
238                           [14] = "Am5x86-WT",
239                           [15] = "Am5x86-WB" 
240                   }
241                 },
242         },
243         .c_init         = init_amd,
244         .c_identify     = generic_identify,
245         .c_size_cache   = amd_size_cache,
246 };
247
248 int __init amd_init_cpu(void)
249 {
250         cpu_devs[X86_VENDOR_AMD] = &amd_cpu_dev;
251         return 0;
252 }
253
254 //early_arch_initcall(amd_init_cpu);