[PATCH] i386: Don't discard upper 32bits of HWCR on K8
[linux-2.6.git] / arch / i386 / kernel / cpu / amd.c
1 #include <linux/init.h>
2 #include <linux/bitops.h>
3 #include <linux/mm.h>
4 #include <asm/io.h>
5 #include <asm/processor.h>
6
7 #include "cpu.h"
8
9 /*
10  *      B step AMD K6 before B 9730xxxx have hardware bugs that can cause
11  *      misexecution of code under Linux. Owners of such processors should
12  *      contact AMD for precise details and a CPU swap.
13  *
14  *      See     http://www.multimania.com/poulot/k6bug.html
15  *              http://www.amd.com/K6/k6docs/revgd.html
16  *
17  *      The following test is erm.. interesting. AMD neglected to up
18  *      the chip setting when fixing the bug but they also tweaked some
19  *      performance at the same time..
20  */
21  
22 extern void vide(void);
23 __asm__(".align 4\nvide: ret");
24
25 static void __init init_amd(struct cpuinfo_x86 *c)
26 {
27         u32 l, h;
28         int mbytes = num_physpages >> (20-PAGE_SHIFT);
29         int r;
30
31 #ifdef CONFIG_SMP
32         unsigned long long value;
33
34         /* Disable TLB flush filter by setting HWCR.FFDIS on K8
35          * bit 6 of msr C001_0015
36          *
37          * Errata 63 for SH-B3 steppings
38          * Errata 122 for all steppings (F+ have it disabled by default)
39          */
40         if (c->x86 == 15) {
41                 rdmsrl(MSR_K7_HWCR, value);
42                 value |= 1 << 6;
43                 wrmsrl(MSR_K7_HWCR, value);
44         }
45 #endif
46
47         /*
48          *      FIXME: We should handle the K5 here. Set up the write
49          *      range and also turn on MSR 83 bits 4 and 31 (write alloc,
50          *      no bus pipeline)
51          */
52
53         /* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
54            3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
55         clear_bit(0*32+31, c->x86_capability);
56         
57         r = get_model_name(c);
58
59         switch(c->x86)
60         {
61                 case 4:
62                 /*
63                  * General Systems BIOSen alias the cpu frequency registers
64                  * of the Elan at 0x000df000. Unfortuantly, one of the Linux
65                  * drivers subsequently pokes it, and changes the CPU speed.
66                  * Workaround : Remove the unneeded alias.
67                  */
68 #define CBAR            (0xfffc) /* Configuration Base Address  (32-bit) */
69 #define CBAR_ENB        (0x80000000)
70 #define CBAR_KEY        (0X000000CB)
71                         if (c->x86_model==9 || c->x86_model == 10) {
72                                 if (inl (CBAR) & CBAR_ENB)
73                                         outl (0 | CBAR_KEY, CBAR);
74                         }
75                         break;
76                 case 5:
77                         if( c->x86_model < 6 )
78                         {
79                                 /* Based on AMD doc 20734R - June 2000 */
80                                 if ( c->x86_model == 0 ) {
81                                         clear_bit(X86_FEATURE_APIC, c->x86_capability);
82                                         set_bit(X86_FEATURE_PGE, c->x86_capability);
83                                 }
84                                 break;
85                         }
86                         
87                         if ( c->x86_model == 6 && c->x86_mask == 1 ) {
88                                 const int K6_BUG_LOOP = 1000000;
89                                 int n;
90                                 void (*f_vide)(void);
91                                 unsigned long d, d2;
92                                 
93                                 printk(KERN_INFO "AMD K6 stepping B detected - ");
94                                 
95                                 /*
96                                  * It looks like AMD fixed the 2.6.2 bug and improved indirect 
97                                  * calls at the same time.
98                                  */
99
100                                 n = K6_BUG_LOOP;
101                                 f_vide = vide;
102                                 rdtscl(d);
103                                 while (n--) 
104                                         f_vide();
105                                 rdtscl(d2);
106                                 d = d2-d;
107                                 
108                                 /* Knock these two lines out if it debugs out ok */
109                                 printk(KERN_INFO "AMD K6 stepping B detected - ");
110                                 /* -- cut here -- */
111                                 if (d > 20*K6_BUG_LOOP) 
112                                         printk("system stability may be impaired when more than 32 MB are used.\n");
113                                 else 
114                                         printk("probably OK (after B9730xxxx).\n");
115                                 printk(KERN_INFO "Please see http://membres.lycos.fr/poulot/k6bug.html\n");
116                         }
117
118                         /* K6 with old style WHCR */
119                         if (c->x86_model < 8 ||
120                            (c->x86_model== 8 && c->x86_mask < 8)) {
121                                 /* We can only write allocate on the low 508Mb */
122                                 if(mbytes>508)
123                                         mbytes=508;
124
125                                 rdmsr(MSR_K6_WHCR, l, h);
126                                 if ((l&0x0000FFFF)==0) {
127                                         unsigned long flags;
128                                         l=(1<<0)|((mbytes/4)<<1);
129                                         local_irq_save(flags);
130                                         wbinvd();
131                                         wrmsr(MSR_K6_WHCR, l, h);
132                                         local_irq_restore(flags);
133                                         printk(KERN_INFO "Enabling old style K6 write allocation for %d Mb\n",
134                                                 mbytes);
135                                 }
136                                 break;
137                         }
138
139                         if ((c->x86_model == 8 && c->x86_mask >7) ||
140                              c->x86_model == 9 || c->x86_model == 13) {
141                                 /* The more serious chips .. */
142
143                                 if(mbytes>4092)
144                                         mbytes=4092;
145
146                                 rdmsr(MSR_K6_WHCR, l, h);
147                                 if ((l&0xFFFF0000)==0) {
148                                         unsigned long flags;
149                                         l=((mbytes>>2)<<22)|(1<<16);
150                                         local_irq_save(flags);
151                                         wbinvd();
152                                         wrmsr(MSR_K6_WHCR, l, h);
153                                         local_irq_restore(flags);
154                                         printk(KERN_INFO "Enabling new style K6 write allocation for %d Mb\n",
155                                                 mbytes);
156                                 }
157
158                                 /*  Set MTRR capability flag if appropriate */
159                                 if (c->x86_model == 13 || c->x86_model == 9 ||
160                                    (c->x86_model == 8 && c->x86_mask >= 8))
161                                         set_bit(X86_FEATURE_K6_MTRR, c->x86_capability);
162                                 break;
163                         }
164                         break;
165
166                 case 6: /* An Athlon/Duron */
167  
168                         /* Bit 15 of Athlon specific MSR 15, needs to be 0
169                          * to enable SSE on Palomino/Morgan/Barton CPU's.
170                          * If the BIOS didn't enable it already, enable it here.
171                          */
172                         if (c->x86_model >= 6 && c->x86_model <= 10) {
173                                 if (!cpu_has(c, X86_FEATURE_XMM)) {
174                                         printk(KERN_INFO "Enabling disabled K7/SSE Support.\n");
175                                         rdmsr(MSR_K7_HWCR, l, h);
176                                         l &= ~0x00008000;
177                                         wrmsr(MSR_K7_HWCR, l, h);
178                                         set_bit(X86_FEATURE_XMM, c->x86_capability);
179                                 }
180                         }
181
182                         /* It's been determined by AMD that Athlons since model 8 stepping 1
183                          * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
184                          * As per AMD technical note 27212 0.2
185                          */
186                         if ((c->x86_model == 8 && c->x86_mask>=1) || (c->x86_model > 8)) {
187                                 rdmsr(MSR_K7_CLK_CTL, l, h);
188                                 if ((l & 0xfff00000) != 0x20000000) {
189                                         printk ("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", l,
190                                                 ((l & 0x000fffff)|0x20000000));
191                                         wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h);
192                                 }
193                         }
194                         break;
195         }
196
197         switch (c->x86) {
198         case 15:
199                 set_bit(X86_FEATURE_K8, c->x86_capability);
200                 break;
201         case 6:
202                 set_bit(X86_FEATURE_K7, c->x86_capability); 
203                 break;
204         }
205
206         display_cacheinfo(c);
207
208         if (cpuid_eax(0x80000000) >= 0x80000008) {
209                 c->x86_num_cores = (cpuid_ecx(0x80000008) & 0xff) + 1;
210                 if (c->x86_num_cores & (c->x86_num_cores - 1))
211                         c->x86_num_cores = 1;
212         }
213
214 #ifdef CONFIG_X86_HT
215         /*
216          * On a AMD dual core setup the lower bits of the APIC id
217          * distingush the cores.  Assumes number of cores is a power
218          * of two.
219          */
220         if (c->x86_num_cores > 1) {
221                 int cpu = smp_processor_id();
222                 unsigned bits = 0;
223                 while ((1 << bits) < c->x86_num_cores)
224                         bits++;
225                 cpu_core_id[cpu] = phys_proc_id[cpu] & ((1<<bits)-1);
226                 phys_proc_id[cpu] >>= bits;
227                 printk(KERN_INFO "CPU %d(%d) -> Core %d\n",
228                        cpu, c->x86_num_cores, cpu_core_id[cpu]);
229         }
230 #endif
231 }
232
233 static unsigned int amd_size_cache(struct cpuinfo_x86 * c, unsigned int size)
234 {
235         /* AMD errata T13 (order #21922) */
236         if ((c->x86 == 6)) {
237                 if (c->x86_model == 3 && c->x86_mask == 0)      /* Duron Rev A0 */
238                         size = 64;
239                 if (c->x86_model == 4 &&
240                     (c->x86_mask==0 || c->x86_mask==1)) /* Tbird rev A1/A2 */
241                         size = 256;
242         }
243         return size;
244 }
245
246 static struct cpu_dev amd_cpu_dev __initdata = {
247         .c_vendor       = "AMD",
248         .c_ident        = { "AuthenticAMD" },
249         .c_models = {
250                 { .vendor = X86_VENDOR_AMD, .family = 4, .model_names =
251                   {
252                           [3] = "486 DX/2",
253                           [7] = "486 DX/2-WB",
254                           [8] = "486 DX/4", 
255                           [9] = "486 DX/4-WB", 
256                           [14] = "Am5x86-WT",
257                           [15] = "Am5x86-WB" 
258                   }
259                 },
260         },
261         .c_init         = init_amd,
262         .c_identify     = generic_identify,
263         .c_size_cache   = amd_size_cache,
264 };
265
266 int __init amd_init_cpu(void)
267 {
268         cpu_devs[X86_VENDOR_AMD] = &amd_cpu_dev;
269         return 0;
270 }
271
272 //early_arch_initcall(amd_init_cpu);