Blackfin arch: Cleanup and unify Blackfin IRQ and GPIO IRQ handling
[linux-2.6.git] / arch / blackfin / mach-common / ints-priority.c
1 /*
2  * File:         arch/blackfin/mach-common/ints-priority.c
3  *
4  * Description:  Set up the interrupt priorities
5  *
6  * Modified:
7  *               1996 Roman Zippel
8  *               1999 D. Jeff Dionne <jeff@uclinux.org>
9  *               2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
10  *               2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
11  *               2003 Metrowerks/Motorola
12  *               2003 Bas Vermeulen <bas@buyways.nl>
13  *               Copyright 2004-2008 Analog Devices Inc.
14  *
15  * Bugs:         Enter bugs at http://blackfin.uclinux.org/
16  *
17  * This program is free software; you can redistribute it and/or modify
18  * it under the terms of the GNU General Public License as published by
19  * the Free Software Foundation; either version 2 of the License, or
20  * (at your option) any later version.
21  *
22  * This program is distributed in the hope that it will be useful,
23  * but WITHOUT ANY WARRANTY; without even the implied warranty of
24  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
25  * GNU General Public License for more details.
26  *
27  * You should have received a copy of the GNU General Public License
28  * along with this program; if not, see the file COPYING, or write
29  * to the Free Software Foundation, Inc.,
30  * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
31  */
32
33 #include <linux/module.h>
34 #include <linux/kernel_stat.h>
35 #include <linux/seq_file.h>
36 #include <linux/irq.h>
37 #ifdef CONFIG_KGDB
38 #include <linux/kgdb.h>
39 #endif
40 #include <asm/traps.h>
41 #include <asm/blackfin.h>
42 #include <asm/gpio.h>
43 #include <asm/irq_handler.h>
44
45 #ifdef BF537_FAMILY
46 # define BF537_GENERIC_ERROR_INT_DEMUX
47 #else
48 # undef BF537_GENERIC_ERROR_INT_DEMUX
49 #endif
50
51 /*
52  * NOTES:
53  * - we have separated the physical Hardware interrupt from the
54  * levels that the LINUX kernel sees (see the description in irq.h)
55  * -
56  */
57
58 /* Initialize this to an actual value to force it into the .data
59  * section so that we know it is properly initialized at entry into
60  * the kernel but before bss is initialized to zero (which is where
61  * it would live otherwise).  The 0x1f magic represents the IRQs we
62  * cannot actually mask out in hardware.
63  */
64 unsigned long irq_flags = 0x1f;
65 EXPORT_SYMBOL(irq_flags);
66
67 /* The number of spurious interrupts */
68 atomic_t num_spurious;
69
70 #ifdef CONFIG_PM
71 unsigned long bfin_sic_iwr[3];  /* Up to 3 SIC_IWRx registers */
72 unsigned vr_wakeup;
73 #endif
74
75 struct ivgx {
76         /* irq number for request_irq, available in mach-bf5xx/irq.h */
77         unsigned int irqno;
78         /* corresponding bit in the SIC_ISR register */
79         unsigned int isrflag;
80 } ivg_table[NR_PERI_INTS];
81
82 struct ivg_slice {
83         /* position of first irq in ivg_table for given ivg */
84         struct ivgx *ifirst;
85         struct ivgx *istop;
86 } ivg7_13[IVG13 - IVG7 + 1];
87
88
89 /*
90  * Search SIC_IAR and fill tables with the irqvalues
91  * and their positions in the SIC_ISR register.
92  */
93 static void __init search_IAR(void)
94 {
95         unsigned ivg, irq_pos = 0;
96         for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) {
97                 int irqn;
98
99                 ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos];
100
101                 for (irqn = 0; irqn < NR_PERI_INTS; irqn++) {
102                         int iar_shift = (irqn & 7) * 4;
103                                 if (ivg == (0xf &
104 #if defined(CONFIG_BF52x) || defined(CONFIG_BF538) \
105         || defined(CONFIG_BF539) || defined(CONFIG_BF51x)
106                              bfin_read32((unsigned long *)SIC_IAR0 +
107                                          ((irqn % 32) >> 3) + ((irqn / 32) *
108                                          ((SIC_IAR4 - SIC_IAR0) / 4))) >> iar_shift)) {
109 #else
110                              bfin_read32((unsigned long *)SIC_IAR0 +
111                                          (irqn >> 3)) >> iar_shift)) {
112 #endif
113                                 ivg_table[irq_pos].irqno = IVG7 + irqn;
114                                 ivg_table[irq_pos].isrflag = 1 << (irqn % 32);
115                                 ivg7_13[ivg].istop++;
116                                 irq_pos++;
117                         }
118                 }
119         }
120 }
121
122 /*
123  * This is for core internal IRQs
124  */
125
126 static void bfin_ack_noop(unsigned int irq)
127 {
128         /* Dummy function.  */
129 }
130
131 static void bfin_core_mask_irq(unsigned int irq)
132 {
133         irq_flags &= ~(1 << irq);
134         if (!irqs_disabled())
135                 local_irq_enable();
136 }
137
138 static void bfin_core_unmask_irq(unsigned int irq)
139 {
140         irq_flags |= 1 << irq;
141         /*
142          * If interrupts are enabled, IMASK must contain the same value
143          * as irq_flags.  Make sure that invariant holds.  If interrupts
144          * are currently disabled we need not do anything; one of the
145          * callers will take care of setting IMASK to the proper value
146          * when reenabling interrupts.
147          * local_irq_enable just does "STI irq_flags", so it's exactly
148          * what we need.
149          */
150         if (!irqs_disabled())
151                 local_irq_enable();
152         return;
153 }
154
155 static void bfin_internal_mask_irq(unsigned int irq)
156 {
157 #ifdef CONFIG_BF53x
158         bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
159                              ~(1 << SIC_SYSIRQ(irq)));
160 #else
161         unsigned mask_bank, mask_bit;
162         mask_bank = SIC_SYSIRQ(irq) / 32;
163         mask_bit = SIC_SYSIRQ(irq) % 32;
164         bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
165                              ~(1 << mask_bit));
166 #endif
167 }
168
169 static void bfin_internal_unmask_irq(unsigned int irq)
170 {
171 #ifdef CONFIG_BF53x
172         bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
173                              (1 << SIC_SYSIRQ(irq)));
174 #else
175         unsigned mask_bank, mask_bit;
176         mask_bank = SIC_SYSIRQ(irq) / 32;
177         mask_bit = SIC_SYSIRQ(irq) % 32;
178         bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) |
179                              (1 << mask_bit));
180 #endif
181 }
182
183 #ifdef CONFIG_PM
184 int bfin_internal_set_wake(unsigned int irq, unsigned int state)
185 {
186         u32 bank, bit, wakeup = 0;
187         unsigned long flags;
188         bank = SIC_SYSIRQ(irq) / 32;
189         bit = SIC_SYSIRQ(irq) % 32;
190
191         switch (irq) {
192 #ifdef IRQ_RTC
193         case IRQ_RTC:
194         wakeup |= WAKE;
195         break;
196 #endif
197 #ifdef IRQ_CAN0_RX
198         case IRQ_CAN0_RX:
199         wakeup |= CANWE;
200         break;
201 #endif
202 #ifdef IRQ_CAN1_RX
203         case IRQ_CAN1_RX:
204         wakeup |= CANWE;
205         break;
206 #endif
207 #ifdef IRQ_USB_INT0
208         case IRQ_USB_INT0:
209         wakeup |= USBWE;
210         break;
211 #endif
212 #ifdef IRQ_KEY
213         case IRQ_KEY:
214         wakeup |= KPADWE;
215         break;
216 #endif
217 #ifdef CONFIG_BF54x
218         case IRQ_CNT:
219         wakeup |= ROTWE;
220         break;
221 #endif
222         default:
223         break;
224         }
225
226         local_irq_save(flags);
227
228         if (state) {
229                 bfin_sic_iwr[bank] |= (1 << bit);
230                 vr_wakeup  |= wakeup;
231
232         } else {
233                 bfin_sic_iwr[bank] &= ~(1 << bit);
234                 vr_wakeup  &= ~wakeup;
235         }
236
237         local_irq_restore(flags);
238
239         return 0;
240 }
241 #endif
242
243 static struct irq_chip bfin_core_irqchip = {
244         .name = "CORE",
245         .ack = bfin_ack_noop,
246         .mask = bfin_core_mask_irq,
247         .unmask = bfin_core_unmask_irq,
248 };
249
250 static struct irq_chip bfin_internal_irqchip = {
251         .name = "INTN",
252         .ack = bfin_ack_noop,
253         .mask = bfin_internal_mask_irq,
254         .unmask = bfin_internal_unmask_irq,
255         .mask_ack = bfin_internal_mask_irq,
256         .disable = bfin_internal_mask_irq,
257         .enable = bfin_internal_unmask_irq,
258 #ifdef CONFIG_PM
259         .set_wake = bfin_internal_set_wake,
260 #endif
261 };
262
263 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
264 static int error_int_mask;
265
266 static void bfin_generic_error_mask_irq(unsigned int irq)
267 {
268         error_int_mask &= ~(1L << (irq - IRQ_PPI_ERROR));
269
270         if (!error_int_mask)
271                 bfin_internal_mask_irq(IRQ_GENERIC_ERROR);
272 }
273
274 static void bfin_generic_error_unmask_irq(unsigned int irq)
275 {
276         bfin_internal_unmask_irq(IRQ_GENERIC_ERROR);
277         error_int_mask |= 1L << (irq - IRQ_PPI_ERROR);
278 }
279
280 static struct irq_chip bfin_generic_error_irqchip = {
281         .name = "ERROR",
282         .ack = bfin_ack_noop,
283         .mask_ack = bfin_generic_error_mask_irq,
284         .mask = bfin_generic_error_mask_irq,
285         .unmask = bfin_generic_error_unmask_irq,
286 };
287
288 static void bfin_demux_error_irq(unsigned int int_err_irq,
289                                  struct irq_desc *inta_desc)
290 {
291         int irq = 0;
292
293 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
294         if (bfin_read_EMAC_SYSTAT() & EMAC_ERR_MASK)
295                 irq = IRQ_MAC_ERROR;
296         else
297 #endif
298         if (bfin_read_SPORT0_STAT() & SPORT_ERR_MASK)
299                 irq = IRQ_SPORT0_ERROR;
300         else if (bfin_read_SPORT1_STAT() & SPORT_ERR_MASK)
301                 irq = IRQ_SPORT1_ERROR;
302         else if (bfin_read_PPI_STATUS() & PPI_ERR_MASK)
303                 irq = IRQ_PPI_ERROR;
304         else if (bfin_read_CAN_GIF() & CAN_ERR_MASK)
305                 irq = IRQ_CAN_ERROR;
306         else if (bfin_read_SPI_STAT() & SPI_ERR_MASK)
307                 irq = IRQ_SPI_ERROR;
308         else if ((bfin_read_UART0_IIR() & UART_ERR_MASK_STAT1) &&
309                  (bfin_read_UART0_IIR() & UART_ERR_MASK_STAT0))
310                 irq = IRQ_UART0_ERROR;
311         else if ((bfin_read_UART1_IIR() & UART_ERR_MASK_STAT1) &&
312                  (bfin_read_UART1_IIR() & UART_ERR_MASK_STAT0))
313                 irq = IRQ_UART1_ERROR;
314
315         if (irq) {
316                 if (error_int_mask & (1L << (irq - IRQ_PPI_ERROR))) {
317                         struct irq_desc *desc = irq_desc + irq;
318                         desc->handle_irq(irq, desc);
319                 } else {
320
321                         switch (irq) {
322                         case IRQ_PPI_ERROR:
323                                 bfin_write_PPI_STATUS(PPI_ERR_MASK);
324                                 break;
325 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
326                         case IRQ_MAC_ERROR:
327                                 bfin_write_EMAC_SYSTAT(EMAC_ERR_MASK);
328                                 break;
329 #endif
330                         case IRQ_SPORT0_ERROR:
331                                 bfin_write_SPORT0_STAT(SPORT_ERR_MASK);
332                                 break;
333
334                         case IRQ_SPORT1_ERROR:
335                                 bfin_write_SPORT1_STAT(SPORT_ERR_MASK);
336                                 break;
337
338                         case IRQ_CAN_ERROR:
339                                 bfin_write_CAN_GIS(CAN_ERR_MASK);
340                                 break;
341
342                         case IRQ_SPI_ERROR:
343                                 bfin_write_SPI_STAT(SPI_ERR_MASK);
344                                 break;
345
346                         default:
347                                 break;
348                         }
349
350                         pr_debug("IRQ %d:"
351                                  " MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n",
352                                  irq);
353                 }
354         } else
355                 printk(KERN_ERR
356                        "%s : %s : LINE %d :\nIRQ ?: PERIPHERAL ERROR"
357                        " INTERRUPT ASSERTED BUT NO SOURCE FOUND\n",
358                        __func__, __FILE__, __LINE__);
359
360 }
361 #endif                          /* BF537_GENERIC_ERROR_INT_DEMUX */
362
363 static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle)
364 {
365         struct irq_desc *desc = irq_desc + irq;
366         /* May not call generic set_irq_handler() due to spinlock
367            recursion. */
368         desc->handle_irq = handle;
369 }
370
371 static DECLARE_BITMAP(gpio_enabled, MAX_BLACKFIN_GPIOS);
372 extern void bfin_gpio_irq_prepare(unsigned gpio);
373
374 #if !defined(CONFIG_BF54x)
375
376 static void bfin_gpio_ack_irq(unsigned int irq)
377 {
378         /* AFAIK ack_irq in case mask_ack is provided
379          * get's only called for edge sense irqs
380          */
381         set_gpio_data(irq_to_gpio(irq), 0);
382 }
383
384 static void bfin_gpio_mask_ack_irq(unsigned int irq)
385 {
386         struct irq_desc *desc = irq_desc + irq;
387         u32 gpionr = irq_to_gpio(irq);
388
389         if (desc->handle_irq == handle_edge_irq)
390                 set_gpio_data(gpionr, 0);
391
392         set_gpio_maska(gpionr, 0);
393 }
394
395 static void bfin_gpio_mask_irq(unsigned int irq)
396 {
397         set_gpio_maska(irq_to_gpio(irq), 0);
398 }
399
400 static void bfin_gpio_unmask_irq(unsigned int irq)
401 {
402         set_gpio_maska(irq_to_gpio(irq), 1);
403 }
404
405 static unsigned int bfin_gpio_irq_startup(unsigned int irq)
406 {
407         u32 gpionr = irq_to_gpio(irq);
408
409         if (__test_and_set_bit(gpionr, gpio_enabled))
410                 bfin_gpio_irq_prepare(gpionr);
411
412         bfin_gpio_unmask_irq(irq);
413
414         return 0;
415 }
416
417 static void bfin_gpio_irq_shutdown(unsigned int irq)
418 {
419         bfin_gpio_mask_irq(irq);
420         __clear_bit(irq_to_gpio(irq), gpio_enabled);
421 }
422
423 static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
424 {
425         u32 gpionr = irq_to_gpio(irq);
426
427         if (type == IRQ_TYPE_PROBE) {
428                 /* only probe unenabled GPIO interrupt lines */
429                 if (__test_bit(gpionr, gpio_enabled))
430                         return 0;
431                 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
432         }
433
434         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
435                     IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
436
437                 if (__test_and_set_bit(gpionr, gpio_enabled))
438                         bfin_gpio_irq_prepare(gpionr);
439
440         } else {
441                 __clear_bit(gpionr, gpio_enabled);
442                 return 0;
443         }
444
445         set_gpio_inen(gpionr, 0);
446         set_gpio_dir(gpionr, 0);
447
448         if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
449             == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
450                 set_gpio_both(gpionr, 1);
451         else
452                 set_gpio_both(gpionr, 0);
453
454         if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
455                 set_gpio_polar(gpionr, 1);      /* low or falling edge denoted by one */
456         else
457                 set_gpio_polar(gpionr, 0);      /* high or rising edge denoted by zero */
458
459         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
460                 set_gpio_edge(gpionr, 1);
461                 set_gpio_inen(gpionr, 1);
462                 set_gpio_data(gpionr, 0);
463
464         } else {
465                 set_gpio_edge(gpionr, 0);
466                 set_gpio_inen(gpionr, 1);
467         }
468
469         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
470                 bfin_set_irq_handler(irq, handle_edge_irq);
471         else
472                 bfin_set_irq_handler(irq, handle_level_irq);
473
474         return 0;
475 }
476
477 #ifdef CONFIG_PM
478 int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
479 {
480         unsigned gpio = irq_to_gpio(irq);
481
482         if (state)
483                 gpio_pm_wakeup_request(gpio, PM_WAKE_IGNORE);
484         else
485                 gpio_pm_wakeup_free(gpio);
486
487         return 0;
488 }
489 #endif
490
491 static void bfin_demux_gpio_irq(unsigned int inta_irq,
492                                 struct irq_desc *desc)
493 {
494         unsigned int i, gpio, mask, irq, search = 0;
495
496         switch (inta_irq) {
497 #if defined(CONFIG_BF53x)
498         case IRQ_PROG_INTA:
499                 irq = IRQ_PF0;
500                 search = 1;
501                 break;
502 # if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
503         case IRQ_MAC_RX:
504                 irq = IRQ_PH0;
505                 break;
506 # endif
507 #elif defined(CONFIG_BF538) || defined(CONFIG_BF539)
508         case IRQ_PORTF_INTA:
509                 irq = IRQ_PF0;
510                 break;
511 #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
512         case IRQ_PORTF_INTA:
513                 irq = IRQ_PF0;
514                 break;
515         case IRQ_PORTG_INTA:
516                 irq = IRQ_PG0;
517                 break;
518         case IRQ_PORTH_INTA:
519                 irq = IRQ_PH0;
520                 break;
521 #elif defined(CONFIG_BF561)
522         case IRQ_PROG0_INTA:
523                 irq = IRQ_PF0;
524                 break;
525         case IRQ_PROG1_INTA:
526                 irq = IRQ_PF16;
527                 break;
528         case IRQ_PROG2_INTA:
529                 irq = IRQ_PF32;
530                 break;
531 #endif
532         default:
533                 BUG();
534                 return;
535         }
536
537         if (search) {
538                 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
539                         irq += i;
540
541                         mask = get_gpiop_data(i) & get_gpiop_maska(i);
542
543                         while (mask) {
544                                 if (mask & 1) {
545                                         desc = irq_desc + irq;
546                                         desc->handle_irq(irq, desc);
547                                 }
548                                 irq++;
549                                 mask >>= 1;
550                         }
551                 }
552         } else {
553                         gpio = irq_to_gpio(irq);
554                         mask = get_gpiop_data(gpio) & get_gpiop_maska(gpio);
555
556                         do {
557                                 if (mask & 1) {
558                                         desc = irq_desc + irq;
559                                         desc->handle_irq(irq, desc);
560                                 }
561                                 irq++;
562                                 mask >>= 1;
563                         } while (mask);
564         }
565
566 }
567
568 #else                           /* CONFIG_BF54x */
569
570 #define NR_PINT_SYS_IRQS        4
571 #define NR_PINT_BITS            32
572 #define NR_PINTS                160
573 #define IRQ_NOT_AVAIL           0xFF
574
575 #define PINT_2_BANK(x)          ((x) >> 5)
576 #define PINT_2_BIT(x)           ((x) & 0x1F)
577 #define PINT_BIT(x)             (1 << (PINT_2_BIT(x)))
578
579 static unsigned char irq2pint_lut[NR_PINTS];
580 static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS];
581
582 struct pin_int_t {
583         unsigned int mask_set;
584         unsigned int mask_clear;
585         unsigned int request;
586         unsigned int assign;
587         unsigned int edge_set;
588         unsigned int edge_clear;
589         unsigned int invert_set;
590         unsigned int invert_clear;
591         unsigned int pinstate;
592         unsigned int latch;
593 };
594
595 static struct pin_int_t *pint[NR_PINT_SYS_IRQS] = {
596         (struct pin_int_t *)PINT0_MASK_SET,
597         (struct pin_int_t *)PINT1_MASK_SET,
598         (struct pin_int_t *)PINT2_MASK_SET,
599         (struct pin_int_t *)PINT3_MASK_SET,
600 };
601
602 inline unsigned int get_irq_base(u32 bank, u8 bmap)
603 {
604         unsigned int irq_base;
605
606         if (bank < 2) {         /*PA-PB */
607                 irq_base = IRQ_PA0 + bmap * 16;
608         } else {                /*PC-PJ */
609                 irq_base = IRQ_PC0 + bmap * 16;
610         }
611
612         return irq_base;
613 }
614
615         /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
616 void init_pint_lut(void)
617 {
618         u16 bank, bit, irq_base, bit_pos;
619         u32 pint_assign;
620         u8 bmap;
621
622         memset(irq2pint_lut, IRQ_NOT_AVAIL, sizeof(irq2pint_lut));
623
624         for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) {
625
626                 pint_assign = pint[bank]->assign;
627
628                 for (bit = 0; bit < NR_PINT_BITS; bit++) {
629
630                         bmap = (pint_assign >> ((bit / 8) * 8)) & 0xFF;
631
632                         irq_base = get_irq_base(bank, bmap);
633
634                         irq_base += (bit % 8) + ((bit / 8) & 1 ? 8 : 0);
635                         bit_pos = bit + bank * NR_PINT_BITS;
636
637                         pint2irq_lut[bit_pos] = irq_base - SYS_IRQS;
638                         irq2pint_lut[irq_base - SYS_IRQS] = bit_pos;
639                 }
640         }
641 }
642
643 static void bfin_gpio_ack_irq(unsigned int irq)
644 {
645         struct irq_desc *desc = irq_desc + irq;
646         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
647         u32 pintbit = PINT_BIT(pint_val);
648         u32 bank = PINT_2_BANK(pint_val);
649
650         if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
651                 if (pint[bank]->invert_set & pintbit)
652                         pint[bank]->invert_clear = pintbit;
653                 else
654                         pint[bank]->invert_set = pintbit;
655         }
656         pint[bank]->request = pintbit;
657
658 }
659
660 static void bfin_gpio_mask_ack_irq(unsigned int irq)
661 {
662         struct irq_desc *desc = irq_desc + irq;
663         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
664         u32 pintbit = PINT_BIT(pint_val);
665         u32 bank = PINT_2_BANK(pint_val);
666
667         if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
668                 if (pint[bank]->invert_set & pintbit)
669                         pint[bank]->invert_clear = pintbit;
670                 else
671                         pint[bank]->invert_set = pintbit;
672         }
673
674         pint[bank]->request = pintbit;
675         pint[bank]->mask_clear = pintbit;
676 }
677
678 static void bfin_gpio_mask_irq(unsigned int irq)
679 {
680         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
681
682         pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val);
683 }
684
685 static void bfin_gpio_unmask_irq(unsigned int irq)
686 {
687         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
688         u32 pintbit = PINT_BIT(pint_val);
689         u32 bank = PINT_2_BANK(pint_val);
690
691         pint[bank]->request = pintbit;
692         pint[bank]->mask_set = pintbit;
693 }
694
695 static unsigned int bfin_gpio_irq_startup(unsigned int irq)
696 {
697         u32 gpionr = irq_to_gpio(irq);
698         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
699
700         if (pint_val == IRQ_NOT_AVAIL) {
701                 printk(KERN_ERR
702                 "GPIO IRQ %d :Not in PINT Assign table "
703                 "Reconfigure Interrupt to Port Assignemt\n", irq);
704                 return -ENODEV;
705         }
706
707         if (__test_and_set_bit(gpionr, gpio_enabled))
708                 bfin_gpio_irq_prepare(gpionr);
709
710         bfin_gpio_unmask_irq(irq);
711
712         return 0;
713 }
714
715 static void bfin_gpio_irq_shutdown(unsigned int irq)
716 {
717         u32 gpionr = irq_to_gpio(irq);
718
719         bfin_gpio_mask_irq(irq);
720         __clear_bit(gpionr, gpio_enabled);
721 }
722
723 static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
724 {
725
726         u32 gpionr = irq_to_gpio(irq);
727         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
728         u32 pintbit = PINT_BIT(pint_val);
729         u32 bank = PINT_2_BANK(pint_val);
730
731         if (pint_val == IRQ_NOT_AVAIL)
732                 return -ENODEV;
733
734         if (type == IRQ_TYPE_PROBE) {
735                 /* only probe unenabled GPIO interrupt lines */
736                 if (__test_bit(gpionr, gpio_enabled))
737                         return 0;
738                 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
739         }
740
741         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
742                     IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
743                 if (__test_and_set_bit(gpionr, gpio_enabled))
744                         bfin_gpio_irq_prepare(gpionr);
745
746         } else {
747                 __clear_bit(gpionr, gpio_enabled);
748                 return 0;
749         }
750
751         if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
752                 pint[bank]->invert_set = pintbit;       /* low or falling edge denoted by one */
753         else
754                 pint[bank]->invert_clear = pintbit;     /* high or rising edge denoted by zero */
755
756         if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
757             == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
758                 if (gpio_get_value(gpionr))
759                         pint[bank]->invert_set = pintbit;
760                 else
761                         pint[bank]->invert_clear = pintbit;
762         }
763
764         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
765                 pint[bank]->edge_set = pintbit;
766                 bfin_set_irq_handler(irq, handle_edge_irq);
767         } else {
768                 pint[bank]->edge_clear = pintbit;
769                 bfin_set_irq_handler(irq, handle_level_irq);
770         }
771
772         return 0;
773 }
774
775 #ifdef CONFIG_PM
776 u32 pint_saved_masks[NR_PINT_SYS_IRQS];
777 u32 pint_wakeup_masks[NR_PINT_SYS_IRQS];
778
779 int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
780 {
781         u32 pint_irq;
782         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
783         u32 bank = PINT_2_BANK(pint_val);
784         u32 pintbit = PINT_BIT(pint_val);
785
786         switch (bank) {
787         case 0:
788                 pint_irq = IRQ_PINT0;
789                 break;
790         case 2:
791                 pint_irq = IRQ_PINT2;
792                 break;
793         case 3:
794                 pint_irq = IRQ_PINT3;
795                 break;
796         case 1:
797                 pint_irq = IRQ_PINT1;
798                 break;
799         default:
800                 return -EINVAL;
801         }
802
803         bfin_internal_set_wake(pint_irq, state);
804
805         if (state)
806                 pint_wakeup_masks[bank] |= pintbit;
807         else
808                 pint_wakeup_masks[bank] &= ~pintbit;
809
810         return 0;
811 }
812
813 u32 bfin_pm_setup(void)
814 {
815         u32 val, i;
816
817         for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
818                 val = pint[i]->mask_clear;
819                 pint_saved_masks[i] = val;
820                 if (val ^ pint_wakeup_masks[i]) {
821                         pint[i]->mask_clear = val;
822                         pint[i]->mask_set = pint_wakeup_masks[i];
823                 }
824         }
825
826         return 0;
827 }
828
829 void bfin_pm_restore(void)
830 {
831         u32 i, val;
832
833         for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
834                 val = pint_saved_masks[i];
835                 if (val ^ pint_wakeup_masks[i]) {
836                         pint[i]->mask_clear = pint[i]->mask_clear;
837                         pint[i]->mask_set = val;
838                 }
839         }
840 }
841 #endif
842
843 static void bfin_demux_gpio_irq(unsigned int inta_irq,
844                                 struct irq_desc *desc)
845 {
846         u32 bank, pint_val;
847         u32 request, irq;
848
849         switch (inta_irq) {
850         case IRQ_PINT0:
851                 bank = 0;
852                 break;
853         case IRQ_PINT2:
854                 bank = 2;
855                 break;
856         case IRQ_PINT3:
857                 bank = 3;
858                 break;
859         case IRQ_PINT1:
860                 bank = 1;
861                 break;
862         default:
863                 return;
864         }
865
866         pint_val = bank * NR_PINT_BITS;
867
868         request = pint[bank]->request;
869
870         while (request) {
871                 if (request & 1) {
872                         irq = pint2irq_lut[pint_val] + SYS_IRQS;
873                         desc = irq_desc + irq;
874                         desc->handle_irq(irq, desc);
875                 }
876                 pint_val++;
877                 request >>= 1;
878         }
879
880 }
881 #endif
882
883 static struct irq_chip bfin_gpio_irqchip = {
884         .name = "GPIO",
885         .ack = bfin_gpio_ack_irq,
886         .mask = bfin_gpio_mask_irq,
887         .mask_ack = bfin_gpio_mask_ack_irq,
888         .unmask = bfin_gpio_unmask_irq,
889         .disable = bfin_gpio_mask_irq,
890         .enable = bfin_gpio_unmask_irq,
891         .set_type = bfin_gpio_irq_type,
892         .startup = bfin_gpio_irq_startup,
893         .shutdown = bfin_gpio_irq_shutdown,
894 #ifdef CONFIG_PM
895         .set_wake = bfin_gpio_set_wake,
896 #endif
897 };
898
899 void __init init_exception_vectors(void)
900 {
901         /* cannot program in software:
902          * evt0 - emulation (jtag)
903          * evt1 - reset
904          */
905         bfin_write_EVT2(evt_nmi);
906         bfin_write_EVT3(trap);
907         bfin_write_EVT5(evt_ivhw);
908         bfin_write_EVT6(evt_timer);
909         bfin_write_EVT7(evt_evt7);
910         bfin_write_EVT8(evt_evt8);
911         bfin_write_EVT9(evt_evt9);
912         bfin_write_EVT10(evt_evt10);
913         bfin_write_EVT11(evt_evt11);
914         bfin_write_EVT12(evt_evt12);
915         bfin_write_EVT13(evt_evt13);
916         bfin_write_EVT14(evt14_softirq);
917         bfin_write_EVT15(evt_system_call);
918         CSYNC();
919 }
920
921 /*
922  * This function should be called during kernel startup to initialize
923  * the BFin IRQ handling routines.
924  */
925
926 int __init init_arch_irq(void)
927 {
928         int irq;
929         unsigned long ilat = 0;
930         /*  Disable all the peripheral intrs  - page 4-29 HW Ref manual */
931 #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) \
932         || defined(BF538_FAMILY) || defined(CONFIG_BF51x)
933         bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
934         bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
935 # ifdef CONFIG_BF54x
936         bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
937 # endif
938 #else
939         bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
940 #endif
941
942         local_irq_disable();
943
944 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
945         /* Clear EMAC Interrupt Status bits so we can demux it later */
946         bfin_write_EMAC_SYSTAT(-1);
947 #endif
948
949 #ifdef CONFIG_BF54x
950 # ifdef CONFIG_PINTx_REASSIGN
951         pint[0]->assign = CONFIG_PINT0_ASSIGN;
952         pint[1]->assign = CONFIG_PINT1_ASSIGN;
953         pint[2]->assign = CONFIG_PINT2_ASSIGN;
954         pint[3]->assign = CONFIG_PINT3_ASSIGN;
955 # endif
956         /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
957         init_pint_lut();
958 #endif
959
960         for (irq = 0; irq <= SYS_IRQS; irq++) {
961                 if (irq <= IRQ_CORETMR)
962                         set_irq_chip(irq, &bfin_core_irqchip);
963                 else
964                         set_irq_chip(irq, &bfin_internal_irqchip);
965
966                 switch (irq) {
967 #if defined(CONFIG_BF53x)
968                 case IRQ_PROG_INTA:
969 # if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
970                 case IRQ_MAC_RX:
971 # endif
972 #elif defined(CONFIG_BF54x)
973                 case IRQ_PINT0:
974                 case IRQ_PINT1:
975                 case IRQ_PINT2:
976                 case IRQ_PINT3:
977 #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
978                 case IRQ_PORTF_INTA:
979                 case IRQ_PORTG_INTA:
980                 case IRQ_PORTH_INTA:
981 #elif defined(CONFIG_BF561)
982                 case IRQ_PROG0_INTA:
983                 case IRQ_PROG1_INTA:
984                 case IRQ_PROG2_INTA:
985 #elif defined(CONFIG_BF538) || defined(CONFIG_BF539)
986                 case IRQ_PORTF_INTA:
987 #endif
988
989                         set_irq_chained_handler(irq,
990                                                 bfin_demux_gpio_irq);
991                         break;
992 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
993                 case IRQ_GENERIC_ERROR:
994                         set_irq_handler(irq, bfin_demux_error_irq);
995
996                         break;
997 #endif
998                 default:
999                         set_irq_handler(irq, handle_simple_irq);
1000                         break;
1001                 }
1002         }
1003
1004 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
1005         for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++)
1006                 set_irq_chip_and_handler(irq, &bfin_generic_error_irqchip,
1007                                          handle_level_irq);
1008 #endif
1009
1010         /* if configured as edge, then will be changed to do_edge_IRQ */
1011         for (irq = GPIO_IRQ_BASE; irq < NR_IRQS; irq++)
1012                 set_irq_chip_and_handler(irq, &bfin_gpio_irqchip,
1013                                          handle_level_irq);
1014
1015
1016         bfin_write_IMASK(0);
1017         CSYNC();
1018         ilat = bfin_read_ILAT();
1019         CSYNC();
1020         bfin_write_ILAT(ilat);
1021         CSYNC();
1022
1023         printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
1024         /* IMASK=xxx is equivalent to STI xx or irq_flags=xx,
1025          * local_irq_enable()
1026          */
1027         program_IAR();
1028         /* Therefore it's better to setup IARs before interrupts enabled */
1029         search_IAR();
1030
1031         /* Enable interrupts IVG7-15 */
1032         irq_flags = irq_flags | IMASK_IVG15 |
1033             IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
1034             IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
1035
1036 #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) \
1037         || defined(BF538_FAMILY) || defined(CONFIG_BF51x)
1038         bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
1039 #if defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
1040         /* BF52x/BF51x system reset does not properly reset SIC_IWR1 which
1041          * will screw up the bootrom as it relies on MDMA0/1 waking it
1042          * up from IDLE instructions.  See this report for more info:
1043          * http://blackfin.uclinux.org/gf/tracker/4323
1044          */
1045         bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
1046 #else
1047         bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
1048 #endif
1049 # ifdef CONFIG_BF54x
1050         bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
1051 # endif
1052 #else
1053         bfin_write_SIC_IWR(IWR_DISABLE_ALL);
1054 #endif
1055
1056         return 0;
1057 }
1058
1059 #ifdef CONFIG_DO_IRQ_L1
1060 __attribute__((l1_text))
1061 #endif
1062 void do_irq(int vec, struct pt_regs *fp)
1063 {
1064         if (vec == EVT_IVTMR_P) {
1065                 vec = IRQ_CORETMR;
1066         } else {
1067                 struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
1068                 struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
1069 #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) \
1070         || defined(BF538_FAMILY) || defined(CONFIG_BF51x)
1071                 unsigned long sic_status[3];
1072
1073                 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
1074                 sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
1075 #ifdef CONFIG_BF54x
1076                 sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
1077 #endif
1078                 for (;; ivg++) {
1079                         if (ivg >= ivg_stop) {
1080                                 atomic_inc(&num_spurious);
1081                                 return;
1082                         }
1083                         if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
1084                                 break;
1085                 }
1086 #else
1087                 unsigned long sic_status;
1088
1089                 sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
1090
1091                 for (;; ivg++) {
1092                         if (ivg >= ivg_stop) {
1093                                 atomic_inc(&num_spurious);
1094                                 return;
1095                         } else if (sic_status & ivg->isrflag)
1096                                 break;
1097                 }
1098 #endif
1099                 vec = ivg->irqno;
1100         }
1101         asm_do_IRQ(vec, fp);
1102 }