Blackfin: add support for the on-chip MAC status interrupts
[linux-2.6.git] / arch / blackfin / mach-common / ints-priority.c
1 /*
2  * Set up the interrupt priorities
3  *
4  * Copyright  2004-2009 Analog Devices Inc.
5  *                 2003 Bas Vermeulen <bas@buyways.nl>
6  *                 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
7  *            2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
8  *                 1999 D. Jeff Dionne <jeff@uclinux.org>
9  *                 1996 Roman Zippel
10  *
11  * Licensed under the GPL-2
12  */
13
14 #include <linux/module.h>
15 #include <linux/kernel_stat.h>
16 #include <linux/seq_file.h>
17 #include <linux/irq.h>
18 #ifdef CONFIG_IPIPE
19 #include <linux/ipipe.h>
20 #endif
21 #ifdef CONFIG_KGDB
22 #include <linux/kgdb.h>
23 #endif
24 #include <asm/traps.h>
25 #include <asm/blackfin.h>
26 #include <asm/gpio.h>
27 #include <asm/irq_handler.h>
28 #include <asm/dpmc.h>
29 #include <asm/bfin5xx_spi.h>
30 #include <asm/bfin_sport.h>
31 #include <asm/bfin_can.h>
32
33 #define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1))
34
35 #ifdef BF537_FAMILY
36 # define BF537_GENERIC_ERROR_INT_DEMUX
37 # define SPI_ERR_MASK   (BIT_STAT_TXCOL | BIT_STAT_RBSY | BIT_STAT_MODF | BIT_STAT_TXE) /* SPI_STAT */
38 # define SPORT_ERR_MASK (ROVF | RUVF | TOVF | TUVF)     /* SPORT_STAT */
39 # define PPI_ERR_MASK   (0xFFFF & ~FLD) /* PPI_STATUS */
40 # define EMAC_ERR_MASK  (PHYINT | MMCINT | RXFSINT | TXFSINT | WAKEDET | RXDMAERR | TXDMAERR | STMDONE) /* EMAC_SYSTAT */
41 # define UART_ERR_MASK  (0x6)   /* UART_IIR */
42 # define CAN_ERR_MASK   (EWTIF | EWRIF | EPIF | BOIF | WUIF | UIAIF | AAIF | RMLIF | UCEIF | EXTIF | ADIF)      /* CAN_GIF */
43 #else
44 # undef BF537_GENERIC_ERROR_INT_DEMUX
45 #endif
46
47 /*
48  * NOTES:
49  * - we have separated the physical Hardware interrupt from the
50  * levels that the LINUX kernel sees (see the description in irq.h)
51  * -
52  */
53
54 #ifndef CONFIG_SMP
55 /* Initialize this to an actual value to force it into the .data
56  * section so that we know it is properly initialized at entry into
57  * the kernel but before bss is initialized to zero (which is where
58  * it would live otherwise).  The 0x1f magic represents the IRQs we
59  * cannot actually mask out in hardware.
60  */
61 unsigned long bfin_irq_flags = 0x1f;
62 EXPORT_SYMBOL(bfin_irq_flags);
63 #endif
64
65 /* The number of spurious interrupts */
66 atomic_t num_spurious;
67
68 #ifdef CONFIG_PM
69 unsigned long bfin_sic_iwr[3];  /* Up to 3 SIC_IWRx registers */
70 unsigned vr_wakeup;
71 #endif
72
73 struct ivgx {
74         /* irq number for request_irq, available in mach-bf5xx/irq.h */
75         unsigned int irqno;
76         /* corresponding bit in the SIC_ISR register */
77         unsigned int isrflag;
78 } ivg_table[NR_PERI_INTS];
79
80 struct ivg_slice {
81         /* position of first irq in ivg_table for given ivg */
82         struct ivgx *ifirst;
83         struct ivgx *istop;
84 } ivg7_13[IVG13 - IVG7 + 1];
85
86
87 /*
88  * Search SIC_IAR and fill tables with the irqvalues
89  * and their positions in the SIC_ISR register.
90  */
91 static void __init search_IAR(void)
92 {
93         unsigned ivg, irq_pos = 0;
94         for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) {
95                 int irqn;
96
97                 ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos];
98
99                 for (irqn = 0; irqn < NR_PERI_INTS; irqn++) {
100                         int iar_shift = (irqn & 7) * 4;
101                                 if (ivg == (0xf &
102 #if defined(CONFIG_BF52x) || defined(CONFIG_BF538) \
103         || defined(CONFIG_BF539) || defined(CONFIG_BF51x)
104                              bfin_read32((unsigned long *)SIC_IAR0 +
105                                          ((irqn % 32) >> 3) + ((irqn / 32) *
106                                          ((SIC_IAR4 - SIC_IAR0) / 4))) >> iar_shift)) {
107 #else
108                              bfin_read32((unsigned long *)SIC_IAR0 +
109                                          (irqn >> 3)) >> iar_shift)) {
110 #endif
111                                 ivg_table[irq_pos].irqno = IVG7 + irqn;
112                                 ivg_table[irq_pos].isrflag = 1 << (irqn % 32);
113                                 ivg7_13[ivg].istop++;
114                                 irq_pos++;
115                         }
116                 }
117         }
118 }
119
120 /*
121  * This is for core internal IRQs
122  */
123
124 static void bfin_ack_noop(unsigned int irq)
125 {
126         /* Dummy function.  */
127 }
128
129 static void bfin_core_mask_irq(unsigned int irq)
130 {
131         bfin_irq_flags &= ~(1 << irq);
132         if (!irqs_disabled_hw())
133                 local_irq_enable_hw();
134 }
135
136 static void bfin_core_unmask_irq(unsigned int irq)
137 {
138         bfin_irq_flags |= 1 << irq;
139         /*
140          * If interrupts are enabled, IMASK must contain the same value
141          * as bfin_irq_flags.  Make sure that invariant holds.  If interrupts
142          * are currently disabled we need not do anything; one of the
143          * callers will take care of setting IMASK to the proper value
144          * when reenabling interrupts.
145          * local_irq_enable just does "STI bfin_irq_flags", so it's exactly
146          * what we need.
147          */
148         if (!irqs_disabled_hw())
149                 local_irq_enable_hw();
150         return;
151 }
152
153 static void bfin_internal_mask_irq(unsigned int irq)
154 {
155         unsigned long flags;
156
157 #ifdef CONFIG_BF53x
158         local_irq_save_hw(flags);
159         bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
160                              ~(1 << SIC_SYSIRQ(irq)));
161 #else
162         unsigned mask_bank, mask_bit;
163         local_irq_save_hw(flags);
164         mask_bank = SIC_SYSIRQ(irq) / 32;
165         mask_bit = SIC_SYSIRQ(irq) % 32;
166         bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
167                              ~(1 << mask_bit));
168 #ifdef CONFIG_SMP
169         bfin_write_SICB_IMASK(mask_bank, bfin_read_SICB_IMASK(mask_bank) &
170                              ~(1 << mask_bit));
171 #endif
172 #endif
173         local_irq_restore_hw(flags);
174 }
175
176 #ifdef CONFIG_SMP
177 static void bfin_internal_unmask_irq_affinity(unsigned int irq,
178                 const struct cpumask *affinity)
179 #else
180 static void bfin_internal_unmask_irq(unsigned int irq)
181 #endif
182 {
183         unsigned long flags;
184
185 #ifdef CONFIG_BF53x
186         local_irq_save_hw(flags);
187         bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
188                              (1 << SIC_SYSIRQ(irq)));
189 #else
190         unsigned mask_bank, mask_bit;
191         local_irq_save_hw(flags);
192         mask_bank = SIC_SYSIRQ(irq) / 32;
193         mask_bit = SIC_SYSIRQ(irq) % 32;
194 #ifdef CONFIG_SMP
195         if (cpumask_test_cpu(0, affinity))
196 #endif
197                 bfin_write_SIC_IMASK(mask_bank,
198                         bfin_read_SIC_IMASK(mask_bank) |
199                         (1 << mask_bit));
200 #ifdef CONFIG_SMP
201         if (cpumask_test_cpu(1, affinity))
202                 bfin_write_SICB_IMASK(mask_bank,
203                         bfin_read_SICB_IMASK(mask_bank) |
204                         (1 << mask_bit));
205 #endif
206 #endif
207         local_irq_restore_hw(flags);
208 }
209
210 #ifdef CONFIG_SMP
211 static void bfin_internal_unmask_irq(unsigned int irq)
212 {
213         struct irq_desc *desc = irq_to_desc(irq);
214         bfin_internal_unmask_irq_affinity(irq, desc->affinity);
215 }
216
217 static int bfin_internal_set_affinity(unsigned int irq, const struct cpumask *mask)
218 {
219         bfin_internal_mask_irq(irq);
220         bfin_internal_unmask_irq_affinity(irq, mask);
221
222         return 0;
223 }
224 #endif
225
226 #ifdef CONFIG_PM
227 int bfin_internal_set_wake(unsigned int irq, unsigned int state)
228 {
229         u32 bank, bit, wakeup = 0;
230         unsigned long flags;
231         bank = SIC_SYSIRQ(irq) / 32;
232         bit = SIC_SYSIRQ(irq) % 32;
233
234         switch (irq) {
235 #ifdef IRQ_RTC
236         case IRQ_RTC:
237         wakeup |= WAKE;
238         break;
239 #endif
240 #ifdef IRQ_CAN0_RX
241         case IRQ_CAN0_RX:
242         wakeup |= CANWE;
243         break;
244 #endif
245 #ifdef IRQ_CAN1_RX
246         case IRQ_CAN1_RX:
247         wakeup |= CANWE;
248         break;
249 #endif
250 #ifdef IRQ_USB_INT0
251         case IRQ_USB_INT0:
252         wakeup |= USBWE;
253         break;
254 #endif
255 #ifdef IRQ_KEY
256         case IRQ_KEY:
257         wakeup |= KPADWE;
258         break;
259 #endif
260 #ifdef CONFIG_BF54x
261         case IRQ_CNT:
262         wakeup |= ROTWE;
263         break;
264 #endif
265         default:
266         break;
267         }
268
269         local_irq_save_hw(flags);
270
271         if (state) {
272                 bfin_sic_iwr[bank] |= (1 << bit);
273                 vr_wakeup  |= wakeup;
274
275         } else {
276                 bfin_sic_iwr[bank] &= ~(1 << bit);
277                 vr_wakeup  &= ~wakeup;
278         }
279
280         local_irq_restore_hw(flags);
281
282         return 0;
283 }
284 #endif
285
286 static struct irq_chip bfin_core_irqchip = {
287         .name = "CORE",
288         .ack = bfin_ack_noop,
289         .mask = bfin_core_mask_irq,
290         .unmask = bfin_core_unmask_irq,
291 };
292
293 static struct irq_chip bfin_internal_irqchip = {
294         .name = "INTN",
295         .ack = bfin_ack_noop,
296         .mask = bfin_internal_mask_irq,
297         .unmask = bfin_internal_unmask_irq,
298         .mask_ack = bfin_internal_mask_irq,
299         .disable = bfin_internal_mask_irq,
300         .enable = bfin_internal_unmask_irq,
301 #ifdef CONFIG_SMP
302         .set_affinity = bfin_internal_set_affinity,
303 #endif
304 #ifdef CONFIG_PM
305         .set_wake = bfin_internal_set_wake,
306 #endif
307 };
308
309 static void bfin_handle_irq(unsigned irq)
310 {
311 #ifdef CONFIG_IPIPE
312         struct pt_regs regs;    /* Contents not used. */
313         ipipe_trace_irq_entry(irq);
314         __ipipe_handle_irq(irq, &regs);
315         ipipe_trace_irq_exit(irq);
316 #else /* !CONFIG_IPIPE */
317         struct irq_desc *desc = irq_desc + irq;
318         desc->handle_irq(irq, desc);
319 #endif  /* !CONFIG_IPIPE */
320 }
321
322 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
323 static int error_int_mask;
324
325 static void bfin_generic_error_mask_irq(unsigned int irq)
326 {
327         error_int_mask &= ~(1L << (irq - IRQ_PPI_ERROR));
328         if (!error_int_mask)
329                 bfin_internal_mask_irq(IRQ_GENERIC_ERROR);
330 }
331
332 static void bfin_generic_error_unmask_irq(unsigned int irq)
333 {
334         bfin_internal_unmask_irq(IRQ_GENERIC_ERROR);
335         error_int_mask |= 1L << (irq - IRQ_PPI_ERROR);
336 }
337
338 static struct irq_chip bfin_generic_error_irqchip = {
339         .name = "ERROR",
340         .ack = bfin_ack_noop,
341         .mask_ack = bfin_generic_error_mask_irq,
342         .mask = bfin_generic_error_mask_irq,
343         .unmask = bfin_generic_error_unmask_irq,
344 };
345
346 static void bfin_demux_error_irq(unsigned int int_err_irq,
347                                  struct irq_desc *inta_desc)
348 {
349         int irq = 0;
350
351 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
352         if (bfin_read_EMAC_SYSTAT() & EMAC_ERR_MASK)
353                 irq = IRQ_MAC_ERROR;
354         else
355 #endif
356         if (bfin_read_SPORT0_STAT() & SPORT_ERR_MASK)
357                 irq = IRQ_SPORT0_ERROR;
358         else if (bfin_read_SPORT1_STAT() & SPORT_ERR_MASK)
359                 irq = IRQ_SPORT1_ERROR;
360         else if (bfin_read_PPI_STATUS() & PPI_ERR_MASK)
361                 irq = IRQ_PPI_ERROR;
362         else if (bfin_read_CAN_GIF() & CAN_ERR_MASK)
363                 irq = IRQ_CAN_ERROR;
364         else if (bfin_read_SPI_STAT() & SPI_ERR_MASK)
365                 irq = IRQ_SPI_ERROR;
366         else if ((bfin_read_UART0_IIR() & UART_ERR_MASK) == UART_ERR_MASK)
367                 irq = IRQ_UART0_ERROR;
368         else if ((bfin_read_UART1_IIR() & UART_ERR_MASK) == UART_ERR_MASK)
369                 irq = IRQ_UART1_ERROR;
370
371         if (irq) {
372                 if (error_int_mask & (1L << (irq - IRQ_PPI_ERROR)))
373                         bfin_handle_irq(irq);
374                 else {
375
376                         switch (irq) {
377                         case IRQ_PPI_ERROR:
378                                 bfin_write_PPI_STATUS(PPI_ERR_MASK);
379                                 break;
380 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
381                         case IRQ_MAC_ERROR:
382                                 bfin_write_EMAC_SYSTAT(EMAC_ERR_MASK);
383                                 break;
384 #endif
385                         case IRQ_SPORT0_ERROR:
386                                 bfin_write_SPORT0_STAT(SPORT_ERR_MASK);
387                                 break;
388
389                         case IRQ_SPORT1_ERROR:
390                                 bfin_write_SPORT1_STAT(SPORT_ERR_MASK);
391                                 break;
392
393                         case IRQ_CAN_ERROR:
394                                 bfin_write_CAN_GIS(CAN_ERR_MASK);
395                                 break;
396
397                         case IRQ_SPI_ERROR:
398                                 bfin_write_SPI_STAT(SPI_ERR_MASK);
399                                 break;
400
401                         default:
402                                 break;
403                         }
404
405                         pr_debug("IRQ %d:"
406                                  " MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n",
407                                  irq);
408                 }
409         } else
410                 printk(KERN_ERR
411                        "%s : %s : LINE %d :\nIRQ ?: PERIPHERAL ERROR"
412                        " INTERRUPT ASSERTED BUT NO SOURCE FOUND\n",
413                        __func__, __FILE__, __LINE__);
414
415 }
416 #endif                          /* BF537_GENERIC_ERROR_INT_DEMUX */
417
418 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
419 static int mac_stat_int_mask;
420
421 static void bfin_mac_status_ack_irq(unsigned int irq)
422 {
423         switch (irq) {
424         case IRQ_MAC_MMCINT:
425                 bfin_write_EMAC_MMC_TIRQS(
426                         bfin_read_EMAC_MMC_TIRQE() &
427                         bfin_read_EMAC_MMC_TIRQS());
428                 bfin_write_EMAC_MMC_RIRQS(
429                         bfin_read_EMAC_MMC_RIRQE() &
430                         bfin_read_EMAC_MMC_RIRQS());
431                 break;
432         case IRQ_MAC_RXFSINT:
433                 bfin_write_EMAC_RX_STKY(
434                         bfin_read_EMAC_RX_IRQE() &
435                         bfin_read_EMAC_RX_STKY());
436                 break;
437         case IRQ_MAC_TXFSINT:
438                 bfin_write_EMAC_TX_STKY(
439                         bfin_read_EMAC_TX_IRQE() &
440                         bfin_read_EMAC_TX_STKY());
441                 break;
442         case IRQ_MAC_WAKEDET:
443                  bfin_write_EMAC_WKUP_CTL(
444                         bfin_read_EMAC_WKUP_CTL() | MPKS | RWKS);
445                 break;
446         default:
447                 /* These bits are W1C */
448                 bfin_write_EMAC_SYSTAT(1L << (irq - IRQ_MAC_PHYINT));
449                 break;
450         }
451 }
452
453 static void bfin_mac_status_mask_irq(unsigned int irq)
454 {
455         mac_stat_int_mask &= ~(1L << (irq - IRQ_MAC_PHYINT));
456 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
457         switch (irq) {
458         case IRQ_MAC_PHYINT:
459                 bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() & ~PHYIE);
460                 break;
461         default:
462                 break;
463         }
464 #else
465         if (!mac_stat_int_mask)
466                 bfin_internal_mask_irq(IRQ_MAC_ERROR);
467 #endif
468         bfin_mac_status_ack_irq(irq);
469 }
470
471 static void bfin_mac_status_unmask_irq(unsigned int irq)
472 {
473 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
474         switch (irq) {
475         case IRQ_MAC_PHYINT:
476                 bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() | PHYIE);
477                 break;
478         default:
479                 break;
480         }
481 #else
482         if (!mac_stat_int_mask)
483                 bfin_internal_unmask_irq(IRQ_MAC_ERROR);
484 #endif
485         mac_stat_int_mask |= 1L << (irq - IRQ_MAC_PHYINT);
486 }
487
488 #ifdef CONFIG_PM
489 int bfin_mac_status_set_wake(unsigned int irq, unsigned int state)
490 {
491 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
492         return bfin_internal_set_wake(IRQ_GENERIC_ERROR, state);
493 #else
494         return bfin_internal_set_wake(IRQ_MAC_ERROR, state);
495 #endif
496 }
497 #endif
498
499 static struct irq_chip bfin_mac_status_irqchip = {
500         .name = "MACST",
501         .ack = bfin_ack_noop,
502         .mask_ack = bfin_mac_status_mask_irq,
503         .mask = bfin_mac_status_mask_irq,
504         .unmask = bfin_mac_status_unmask_irq,
505 #ifdef CONFIG_PM
506         .set_wake = bfin_mac_status_set_wake,
507 #endif
508 };
509
510 static void bfin_demux_mac_status_irq(unsigned int int_err_irq,
511                                  struct irq_desc *inta_desc)
512 {
513         int i, irq = 0;
514         u32 status = bfin_read_EMAC_SYSTAT();
515
516         for (i = 0; i < (IRQ_MAC_STMDONE - IRQ_MAC_PHYINT); i++)
517                 if (status & (1L << i)) {
518                         irq = IRQ_MAC_PHYINT + i;
519                         break;
520                 }
521
522         if (irq) {
523                 if (mac_stat_int_mask & (1L << (irq - IRQ_MAC_PHYINT))) {
524                         bfin_handle_irq(irq);
525                 } else {
526                         bfin_mac_status_ack_irq(irq);
527                         pr_debug("IRQ %d:"
528                                  " MASKED MAC ERROR INTERRUPT ASSERTED\n",
529                                  irq);
530                 }
531         } else
532                 printk(KERN_ERR
533                        "%s : %s : LINE %d :\nIRQ ?: MAC ERROR"
534                        " INTERRUPT ASSERTED BUT NO SOURCE FOUND\n",
535                        __func__, __FILE__, __LINE__);
536 }
537 #endif
538
539 static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle)
540 {
541 #ifdef CONFIG_IPIPE
542         _set_irq_handler(irq, handle_level_irq);
543 #else
544         struct irq_desc *desc = irq_desc + irq;
545         /* May not call generic set_irq_handler() due to spinlock
546            recursion. */
547         desc->handle_irq = handle;
548 #endif
549 }
550
551 static DECLARE_BITMAP(gpio_enabled, MAX_BLACKFIN_GPIOS);
552 extern void bfin_gpio_irq_prepare(unsigned gpio);
553
554 #if !defined(CONFIG_BF54x)
555
556 static void bfin_gpio_ack_irq(unsigned int irq)
557 {
558         /* AFAIK ack_irq in case mask_ack is provided
559          * get's only called for edge sense irqs
560          */
561         set_gpio_data(irq_to_gpio(irq), 0);
562 }
563
564 static void bfin_gpio_mask_ack_irq(unsigned int irq)
565 {
566         struct irq_desc *desc = irq_desc + irq;
567         u32 gpionr = irq_to_gpio(irq);
568
569         if (desc->handle_irq == handle_edge_irq)
570                 set_gpio_data(gpionr, 0);
571
572         set_gpio_maska(gpionr, 0);
573 }
574
575 static void bfin_gpio_mask_irq(unsigned int irq)
576 {
577         set_gpio_maska(irq_to_gpio(irq), 0);
578 }
579
580 static void bfin_gpio_unmask_irq(unsigned int irq)
581 {
582         set_gpio_maska(irq_to_gpio(irq), 1);
583 }
584
585 static unsigned int bfin_gpio_irq_startup(unsigned int irq)
586 {
587         u32 gpionr = irq_to_gpio(irq);
588
589         if (__test_and_set_bit(gpionr, gpio_enabled))
590                 bfin_gpio_irq_prepare(gpionr);
591
592         bfin_gpio_unmask_irq(irq);
593
594         return 0;
595 }
596
597 static void bfin_gpio_irq_shutdown(unsigned int irq)
598 {
599         u32 gpionr = irq_to_gpio(irq);
600
601         bfin_gpio_mask_irq(irq);
602         __clear_bit(gpionr, gpio_enabled);
603         bfin_gpio_irq_free(gpionr);
604 }
605
606 static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
607 {
608         int ret;
609         char buf[16];
610         u32 gpionr = irq_to_gpio(irq);
611
612         if (type == IRQ_TYPE_PROBE) {
613                 /* only probe unenabled GPIO interrupt lines */
614                 if (test_bit(gpionr, gpio_enabled))
615                         return 0;
616                 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
617         }
618
619         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
620                     IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
621
622                 snprintf(buf, 16, "gpio-irq%d", irq);
623                 ret = bfin_gpio_irq_request(gpionr, buf);
624                 if (ret)
625                         return ret;
626
627                 if (__test_and_set_bit(gpionr, gpio_enabled))
628                         bfin_gpio_irq_prepare(gpionr);
629
630         } else {
631                 __clear_bit(gpionr, gpio_enabled);
632                 return 0;
633         }
634
635         set_gpio_inen(gpionr, 0);
636         set_gpio_dir(gpionr, 0);
637
638         if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
639             == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
640                 set_gpio_both(gpionr, 1);
641         else
642                 set_gpio_both(gpionr, 0);
643
644         if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
645                 set_gpio_polar(gpionr, 1);      /* low or falling edge denoted by one */
646         else
647                 set_gpio_polar(gpionr, 0);      /* high or rising edge denoted by zero */
648
649         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
650                 set_gpio_edge(gpionr, 1);
651                 set_gpio_inen(gpionr, 1);
652                 set_gpio_data(gpionr, 0);
653
654         } else {
655                 set_gpio_edge(gpionr, 0);
656                 set_gpio_inen(gpionr, 1);
657         }
658
659         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
660                 bfin_set_irq_handler(irq, handle_edge_irq);
661         else
662                 bfin_set_irq_handler(irq, handle_level_irq);
663
664         return 0;
665 }
666
667 #ifdef CONFIG_PM
668 int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
669 {
670         unsigned gpio = irq_to_gpio(irq);
671
672         if (state)
673                 gpio_pm_wakeup_request(gpio, PM_WAKE_IGNORE);
674         else
675                 gpio_pm_wakeup_free(gpio);
676
677         return 0;
678 }
679 #endif
680
681 static void bfin_demux_gpio_irq(unsigned int inta_irq,
682                                 struct irq_desc *desc)
683 {
684         unsigned int i, gpio, mask, irq, search = 0;
685
686         switch (inta_irq) {
687 #if defined(CONFIG_BF53x)
688         case IRQ_PROG_INTA:
689                 irq = IRQ_PF0;
690                 search = 1;
691                 break;
692 # if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
693         case IRQ_MAC_RX:
694                 irq = IRQ_PH0;
695                 break;
696 # endif
697 #elif defined(CONFIG_BF538) || defined(CONFIG_BF539)
698         case IRQ_PORTF_INTA:
699                 irq = IRQ_PF0;
700                 break;
701 #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
702         case IRQ_PORTF_INTA:
703                 irq = IRQ_PF0;
704                 break;
705         case IRQ_PORTG_INTA:
706                 irq = IRQ_PG0;
707                 break;
708         case IRQ_PORTH_INTA:
709                 irq = IRQ_PH0;
710                 break;
711 #elif defined(CONFIG_BF561)
712         case IRQ_PROG0_INTA:
713                 irq = IRQ_PF0;
714                 break;
715         case IRQ_PROG1_INTA:
716                 irq = IRQ_PF16;
717                 break;
718         case IRQ_PROG2_INTA:
719                 irq = IRQ_PF32;
720                 break;
721 #endif
722         default:
723                 BUG();
724                 return;
725         }
726
727         if (search) {
728                 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
729                         irq += i;
730
731                         mask = get_gpiop_data(i) & get_gpiop_maska(i);
732
733                         while (mask) {
734                                 if (mask & 1)
735                                         bfin_handle_irq(irq);
736                                 irq++;
737                                 mask >>= 1;
738                         }
739                 }
740         } else {
741                         gpio = irq_to_gpio(irq);
742                         mask = get_gpiop_data(gpio) & get_gpiop_maska(gpio);
743
744                         do {
745                                 if (mask & 1)
746                                         bfin_handle_irq(irq);
747                                 irq++;
748                                 mask >>= 1;
749                         } while (mask);
750         }
751
752 }
753
754 #else                           /* CONFIG_BF54x */
755
756 #define NR_PINT_SYS_IRQS        4
757 #define NR_PINT_BITS            32
758 #define NR_PINTS                160
759 #define IRQ_NOT_AVAIL           0xFF
760
761 #define PINT_2_BANK(x)          ((x) >> 5)
762 #define PINT_2_BIT(x)           ((x) & 0x1F)
763 #define PINT_BIT(x)             (1 << (PINT_2_BIT(x)))
764
765 static unsigned char irq2pint_lut[NR_PINTS];
766 static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS];
767
768 struct pin_int_t {
769         unsigned int mask_set;
770         unsigned int mask_clear;
771         unsigned int request;
772         unsigned int assign;
773         unsigned int edge_set;
774         unsigned int edge_clear;
775         unsigned int invert_set;
776         unsigned int invert_clear;
777         unsigned int pinstate;
778         unsigned int latch;
779 };
780
781 static struct pin_int_t *pint[NR_PINT_SYS_IRQS] = {
782         (struct pin_int_t *)PINT0_MASK_SET,
783         (struct pin_int_t *)PINT1_MASK_SET,
784         (struct pin_int_t *)PINT2_MASK_SET,
785         (struct pin_int_t *)PINT3_MASK_SET,
786 };
787
788 inline unsigned int get_irq_base(u32 bank, u8 bmap)
789 {
790         unsigned int irq_base;
791
792         if (bank < 2) {         /*PA-PB */
793                 irq_base = IRQ_PA0 + bmap * 16;
794         } else {                /*PC-PJ */
795                 irq_base = IRQ_PC0 + bmap * 16;
796         }
797
798         return irq_base;
799 }
800
801         /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
802 void init_pint_lut(void)
803 {
804         u16 bank, bit, irq_base, bit_pos;
805         u32 pint_assign;
806         u8 bmap;
807
808         memset(irq2pint_lut, IRQ_NOT_AVAIL, sizeof(irq2pint_lut));
809
810         for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) {
811
812                 pint_assign = pint[bank]->assign;
813
814                 for (bit = 0; bit < NR_PINT_BITS; bit++) {
815
816                         bmap = (pint_assign >> ((bit / 8) * 8)) & 0xFF;
817
818                         irq_base = get_irq_base(bank, bmap);
819
820                         irq_base += (bit % 8) + ((bit / 8) & 1 ? 8 : 0);
821                         bit_pos = bit + bank * NR_PINT_BITS;
822
823                         pint2irq_lut[bit_pos] = irq_base - SYS_IRQS;
824                         irq2pint_lut[irq_base - SYS_IRQS] = bit_pos;
825                 }
826         }
827 }
828
829 static void bfin_gpio_ack_irq(unsigned int irq)
830 {
831         struct irq_desc *desc = irq_desc + irq;
832         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
833         u32 pintbit = PINT_BIT(pint_val);
834         u32 bank = PINT_2_BANK(pint_val);
835
836         if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
837                 if (pint[bank]->invert_set & pintbit)
838                         pint[bank]->invert_clear = pintbit;
839                 else
840                         pint[bank]->invert_set = pintbit;
841         }
842         pint[bank]->request = pintbit;
843
844 }
845
846 static void bfin_gpio_mask_ack_irq(unsigned int irq)
847 {
848         struct irq_desc *desc = irq_desc + irq;
849         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
850         u32 pintbit = PINT_BIT(pint_val);
851         u32 bank = PINT_2_BANK(pint_val);
852
853         if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
854                 if (pint[bank]->invert_set & pintbit)
855                         pint[bank]->invert_clear = pintbit;
856                 else
857                         pint[bank]->invert_set = pintbit;
858         }
859
860         pint[bank]->request = pintbit;
861         pint[bank]->mask_clear = pintbit;
862 }
863
864 static void bfin_gpio_mask_irq(unsigned int irq)
865 {
866         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
867
868         pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val);
869 }
870
871 static void bfin_gpio_unmask_irq(unsigned int irq)
872 {
873         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
874         u32 pintbit = PINT_BIT(pint_val);
875         u32 bank = PINT_2_BANK(pint_val);
876
877         pint[bank]->request = pintbit;
878         pint[bank]->mask_set = pintbit;
879 }
880
881 static unsigned int bfin_gpio_irq_startup(unsigned int irq)
882 {
883         u32 gpionr = irq_to_gpio(irq);
884         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
885
886         if (pint_val == IRQ_NOT_AVAIL) {
887                 printk(KERN_ERR
888                 "GPIO IRQ %d :Not in PINT Assign table "
889                 "Reconfigure Interrupt to Port Assignemt\n", irq);
890                 return -ENODEV;
891         }
892
893         if (__test_and_set_bit(gpionr, gpio_enabled))
894                 bfin_gpio_irq_prepare(gpionr);
895
896         bfin_gpio_unmask_irq(irq);
897
898         return 0;
899 }
900
901 static void bfin_gpio_irq_shutdown(unsigned int irq)
902 {
903         u32 gpionr = irq_to_gpio(irq);
904
905         bfin_gpio_mask_irq(irq);
906         __clear_bit(gpionr, gpio_enabled);
907         bfin_gpio_irq_free(gpionr);
908 }
909
910 static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
911 {
912         int ret;
913         char buf[16];
914         u32 gpionr = irq_to_gpio(irq);
915         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
916         u32 pintbit = PINT_BIT(pint_val);
917         u32 bank = PINT_2_BANK(pint_val);
918
919         if (pint_val == IRQ_NOT_AVAIL)
920                 return -ENODEV;
921
922         if (type == IRQ_TYPE_PROBE) {
923                 /* only probe unenabled GPIO interrupt lines */
924                 if (test_bit(gpionr, gpio_enabled))
925                         return 0;
926                 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
927         }
928
929         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
930                     IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
931
932                 snprintf(buf, 16, "gpio-irq%d", irq);
933                 ret = bfin_gpio_irq_request(gpionr, buf);
934                 if (ret)
935                         return ret;
936
937                 if (__test_and_set_bit(gpionr, gpio_enabled))
938                         bfin_gpio_irq_prepare(gpionr);
939
940         } else {
941                 __clear_bit(gpionr, gpio_enabled);
942                 return 0;
943         }
944
945         if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
946                 pint[bank]->invert_set = pintbit;       /* low or falling edge denoted by one */
947         else
948                 pint[bank]->invert_clear = pintbit;     /* high or rising edge denoted by zero */
949
950         if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
951             == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
952                 if (gpio_get_value(gpionr))
953                         pint[bank]->invert_set = pintbit;
954                 else
955                         pint[bank]->invert_clear = pintbit;
956         }
957
958         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
959                 pint[bank]->edge_set = pintbit;
960                 bfin_set_irq_handler(irq, handle_edge_irq);
961         } else {
962                 pint[bank]->edge_clear = pintbit;
963                 bfin_set_irq_handler(irq, handle_level_irq);
964         }
965
966         return 0;
967 }
968
969 #ifdef CONFIG_PM
970 u32 pint_saved_masks[NR_PINT_SYS_IRQS];
971 u32 pint_wakeup_masks[NR_PINT_SYS_IRQS];
972
973 int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
974 {
975         u32 pint_irq;
976         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
977         u32 bank = PINT_2_BANK(pint_val);
978         u32 pintbit = PINT_BIT(pint_val);
979
980         switch (bank) {
981         case 0:
982                 pint_irq = IRQ_PINT0;
983                 break;
984         case 2:
985                 pint_irq = IRQ_PINT2;
986                 break;
987         case 3:
988                 pint_irq = IRQ_PINT3;
989                 break;
990         case 1:
991                 pint_irq = IRQ_PINT1;
992                 break;
993         default:
994                 return -EINVAL;
995         }
996
997         bfin_internal_set_wake(pint_irq, state);
998
999         if (state)
1000                 pint_wakeup_masks[bank] |= pintbit;
1001         else
1002                 pint_wakeup_masks[bank] &= ~pintbit;
1003
1004         return 0;
1005 }
1006
1007 u32 bfin_pm_setup(void)
1008 {
1009         u32 val, i;
1010
1011         for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
1012                 val = pint[i]->mask_clear;
1013                 pint_saved_masks[i] = val;
1014                 if (val ^ pint_wakeup_masks[i]) {
1015                         pint[i]->mask_clear = val;
1016                         pint[i]->mask_set = pint_wakeup_masks[i];
1017                 }
1018         }
1019
1020         return 0;
1021 }
1022
1023 void bfin_pm_restore(void)
1024 {
1025         u32 i, val;
1026
1027         for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
1028                 val = pint_saved_masks[i];
1029                 if (val ^ pint_wakeup_masks[i]) {
1030                         pint[i]->mask_clear = pint[i]->mask_clear;
1031                         pint[i]->mask_set = val;
1032                 }
1033         }
1034 }
1035 #endif
1036
1037 static void bfin_demux_gpio_irq(unsigned int inta_irq,
1038                                 struct irq_desc *desc)
1039 {
1040         u32 bank, pint_val;
1041         u32 request, irq;
1042
1043         switch (inta_irq) {
1044         case IRQ_PINT0:
1045                 bank = 0;
1046                 break;
1047         case IRQ_PINT2:
1048                 bank = 2;
1049                 break;
1050         case IRQ_PINT3:
1051                 bank = 3;
1052                 break;
1053         case IRQ_PINT1:
1054                 bank = 1;
1055                 break;
1056         default:
1057                 return;
1058         }
1059
1060         pint_val = bank * NR_PINT_BITS;
1061
1062         request = pint[bank]->request;
1063
1064         while (request) {
1065                 if (request & 1) {
1066                         irq = pint2irq_lut[pint_val] + SYS_IRQS;
1067                         bfin_handle_irq(irq);
1068                 }
1069                 pint_val++;
1070                 request >>= 1;
1071         }
1072
1073 }
1074 #endif
1075
1076 static struct irq_chip bfin_gpio_irqchip = {
1077         .name = "GPIO",
1078         .ack = bfin_gpio_ack_irq,
1079         .mask = bfin_gpio_mask_irq,
1080         .mask_ack = bfin_gpio_mask_ack_irq,
1081         .unmask = bfin_gpio_unmask_irq,
1082         .disable = bfin_gpio_mask_irq,
1083         .enable = bfin_gpio_unmask_irq,
1084         .set_type = bfin_gpio_irq_type,
1085         .startup = bfin_gpio_irq_startup,
1086         .shutdown = bfin_gpio_irq_shutdown,
1087 #ifdef CONFIG_PM
1088         .set_wake = bfin_gpio_set_wake,
1089 #endif
1090 };
1091
1092 void __cpuinit init_exception_vectors(void)
1093 {
1094         /* cannot program in software:
1095          * evt0 - emulation (jtag)
1096          * evt1 - reset
1097          */
1098         bfin_write_EVT2(evt_nmi);
1099         bfin_write_EVT3(trap);
1100         bfin_write_EVT5(evt_ivhw);
1101         bfin_write_EVT6(evt_timer);
1102         bfin_write_EVT7(evt_evt7);
1103         bfin_write_EVT8(evt_evt8);
1104         bfin_write_EVT9(evt_evt9);
1105         bfin_write_EVT10(evt_evt10);
1106         bfin_write_EVT11(evt_evt11);
1107         bfin_write_EVT12(evt_evt12);
1108         bfin_write_EVT13(evt_evt13);
1109         bfin_write_EVT14(evt_evt14);
1110         bfin_write_EVT15(evt_system_call);
1111         CSYNC();
1112 }
1113
1114 /*
1115  * This function should be called during kernel startup to initialize
1116  * the BFin IRQ handling routines.
1117  */
1118
1119 int __init init_arch_irq(void)
1120 {
1121         int irq;
1122         unsigned long ilat = 0;
1123         /*  Disable all the peripheral intrs  - page 4-29 HW Ref manual */
1124 #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) \
1125         || defined(BF538_FAMILY) || defined(CONFIG_BF51x)
1126         bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
1127         bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
1128 # ifdef CONFIG_BF54x
1129         bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
1130 # endif
1131 # ifdef CONFIG_SMP
1132         bfin_write_SICB_IMASK0(SIC_UNMASK_ALL);
1133         bfin_write_SICB_IMASK1(SIC_UNMASK_ALL);
1134 # endif
1135 #else
1136         bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
1137 #endif
1138
1139         local_irq_disable();
1140
1141 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
1142         /* Clear EMAC Interrupt Status bits so we can demux it later */
1143         bfin_write_EMAC_SYSTAT(-1);
1144 #endif
1145
1146 #ifdef CONFIG_BF54x
1147 # ifdef CONFIG_PINTx_REASSIGN
1148         pint[0]->assign = CONFIG_PINT0_ASSIGN;
1149         pint[1]->assign = CONFIG_PINT1_ASSIGN;
1150         pint[2]->assign = CONFIG_PINT2_ASSIGN;
1151         pint[3]->assign = CONFIG_PINT3_ASSIGN;
1152 # endif
1153         /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
1154         init_pint_lut();
1155 #endif
1156
1157         for (irq = 0; irq <= SYS_IRQS; irq++) {
1158                 if (irq <= IRQ_CORETMR)
1159                         set_irq_chip(irq, &bfin_core_irqchip);
1160                 else
1161                         set_irq_chip(irq, &bfin_internal_irqchip);
1162
1163                 switch (irq) {
1164 #if defined(CONFIG_BF53x)
1165                 case IRQ_PROG_INTA:
1166 # if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
1167                 case IRQ_MAC_RX:
1168 # endif
1169 #elif defined(CONFIG_BF54x)
1170                 case IRQ_PINT0:
1171                 case IRQ_PINT1:
1172                 case IRQ_PINT2:
1173                 case IRQ_PINT3:
1174 #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
1175                 case IRQ_PORTF_INTA:
1176                 case IRQ_PORTG_INTA:
1177                 case IRQ_PORTH_INTA:
1178 #elif defined(CONFIG_BF561)
1179                 case IRQ_PROG0_INTA:
1180                 case IRQ_PROG1_INTA:
1181                 case IRQ_PROG2_INTA:
1182 #elif defined(CONFIG_BF538) || defined(CONFIG_BF539)
1183                 case IRQ_PORTF_INTA:
1184 #endif
1185                         set_irq_chained_handler(irq,
1186                                                 bfin_demux_gpio_irq);
1187                         break;
1188 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
1189                 case IRQ_GENERIC_ERROR:
1190                         set_irq_chained_handler(irq, bfin_demux_error_irq);
1191                         break;
1192 #endif
1193 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
1194                 case IRQ_MAC_ERROR:
1195                         set_irq_chained_handler(irq, bfin_demux_mac_status_irq);
1196                         break;
1197 #endif
1198 #ifdef CONFIG_SMP
1199                 case IRQ_SUPPLE_0:
1200                 case IRQ_SUPPLE_1:
1201                         set_irq_handler(irq, handle_percpu_irq);
1202                         break;
1203 #endif
1204
1205 #ifdef CONFIG_TICKSOURCE_CORETMR
1206                 case IRQ_CORETMR:
1207 # ifdef CONFIG_SMP
1208                         set_irq_handler(irq, handle_percpu_irq);
1209                         break;
1210 # else
1211                         set_irq_handler(irq, handle_simple_irq);
1212                         break;
1213 # endif
1214 #endif
1215
1216 #ifdef CONFIG_TICKSOURCE_GPTMR0
1217                 case IRQ_TIMER0:
1218                         set_irq_handler(irq, handle_simple_irq);
1219                         break;
1220 #endif
1221
1222 #ifdef CONFIG_IPIPE
1223                 default:
1224                         set_irq_handler(irq, handle_level_irq);
1225                         break;
1226 #else /* !CONFIG_IPIPE */
1227                 default:
1228                         set_irq_handler(irq, handle_simple_irq);
1229                         break;
1230 #endif /* !CONFIG_IPIPE */
1231                 }
1232         }
1233
1234 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
1235         for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++)
1236                 set_irq_chip_and_handler(irq, &bfin_generic_error_irqchip,
1237                                          handle_level_irq);
1238 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
1239         set_irq_chained_handler(IRQ_MAC_ERROR, bfin_demux_mac_status_irq);
1240 #endif
1241 #endif
1242
1243 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
1244         for (irq = IRQ_MAC_PHYINT; irq <= IRQ_MAC_STMDONE; irq++)
1245                 set_irq_chip_and_handler(irq, &bfin_mac_status_irqchip,
1246                                          handle_level_irq);
1247 #endif
1248         /* if configured as edge, then will be changed to do_edge_IRQ */
1249         for (irq = GPIO_IRQ_BASE;
1250                 irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++)
1251                 set_irq_chip_and_handler(irq, &bfin_gpio_irqchip,
1252                                          handle_level_irq);
1253
1254         bfin_write_IMASK(0);
1255         CSYNC();
1256         ilat = bfin_read_ILAT();
1257         CSYNC();
1258         bfin_write_ILAT(ilat);
1259         CSYNC();
1260
1261         printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
1262         /* IMASK=xxx is equivalent to STI xx or bfin_irq_flags=xx,
1263          * local_irq_enable()
1264          */
1265         program_IAR();
1266         /* Therefore it's better to setup IARs before interrupts enabled */
1267         search_IAR();
1268
1269         /* Enable interrupts IVG7-15 */
1270         bfin_irq_flags |= IMASK_IVG15 |
1271             IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
1272             IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
1273
1274         /* This implicitly covers ANOMALY_05000171
1275          * Boot-ROM code modifies SICA_IWRx wakeup registers
1276          */
1277 #ifdef SIC_IWR0
1278         bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
1279 # ifdef SIC_IWR1
1280         /* BF52x/BF51x system reset does not properly reset SIC_IWR1 which
1281          * will screw up the bootrom as it relies on MDMA0/1 waking it
1282          * up from IDLE instructions.  See this report for more info:
1283          * http://blackfin.uclinux.org/gf/tracker/4323
1284          */
1285         if (ANOMALY_05000435)
1286                 bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
1287         else
1288                 bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
1289 # endif
1290 # ifdef SIC_IWR2
1291         bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
1292 # endif
1293 #else
1294         bfin_write_SIC_IWR(IWR_DISABLE_ALL);
1295 #endif
1296
1297         return 0;
1298 }
1299
1300 #ifdef CONFIG_DO_IRQ_L1
1301 __attribute__((l1_text))
1302 #endif
1303 void do_irq(int vec, struct pt_regs *fp)
1304 {
1305         if (vec == EVT_IVTMR_P) {
1306                 vec = IRQ_CORETMR;
1307         } else {
1308                 struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
1309                 struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
1310 #if defined(SIC_ISR0) || defined(SICA_ISR0)
1311                 unsigned long sic_status[3];
1312
1313                 if (smp_processor_id()) {
1314 # ifdef SICB_ISR0
1315                         /* This will be optimized out in UP mode. */
1316                         sic_status[0] = bfin_read_SICB_ISR0() & bfin_read_SICB_IMASK0();
1317                         sic_status[1] = bfin_read_SICB_ISR1() & bfin_read_SICB_IMASK1();
1318 # endif
1319                 } else {
1320                         sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
1321                         sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
1322                 }
1323 # ifdef SIC_ISR2
1324                 sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
1325 # endif
1326                 for (;; ivg++) {
1327                         if (ivg >= ivg_stop) {
1328                                 atomic_inc(&num_spurious);
1329                                 return;
1330                         }
1331                         if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
1332                                 break;
1333                 }
1334 #else
1335                 unsigned long sic_status;
1336
1337                 sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
1338
1339                 for (;; ivg++) {
1340                         if (ivg >= ivg_stop) {
1341                                 atomic_inc(&num_spurious);
1342                                 return;
1343                         } else if (sic_status & ivg->isrflag)
1344                                 break;
1345                 }
1346 #endif
1347                 vec = ivg->irqno;
1348         }
1349         asm_do_IRQ(vec, fp);
1350 }
1351
1352 #ifdef CONFIG_IPIPE
1353
1354 int __ipipe_get_irq_priority(unsigned irq)
1355 {
1356         int ient, prio;
1357
1358         if (irq <= IRQ_CORETMR)
1359                 return irq;
1360
1361         for (ient = 0; ient < NR_PERI_INTS; ient++) {
1362                 struct ivgx *ivg = ivg_table + ient;
1363                 if (ivg->irqno == irq) {
1364                         for (prio = 0; prio <= IVG13-IVG7; prio++) {
1365                                 if (ivg7_13[prio].ifirst <= ivg &&
1366                                     ivg7_13[prio].istop > ivg)
1367                                         return IVG7 + prio;
1368                         }
1369                 }
1370         }
1371
1372         return IVG15;
1373 }
1374
1375 /* Hw interrupts are disabled on entry (check SAVE_CONTEXT). */
1376 #ifdef CONFIG_DO_IRQ_L1
1377 __attribute__((l1_text))
1378 #endif
1379 asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
1380 {
1381         struct ipipe_percpu_domain_data *p = ipipe_root_cpudom_ptr();
1382         struct ipipe_domain *this_domain = __ipipe_current_domain;
1383         struct ivgx *ivg_stop = ivg7_13[vec-IVG7].istop;
1384         struct ivgx *ivg = ivg7_13[vec-IVG7].ifirst;
1385         int irq, s;
1386
1387         if (likely(vec == EVT_IVTMR_P))
1388                 irq = IRQ_CORETMR;
1389         else {
1390 #if defined(SIC_ISR0) || defined(SICA_ISR0)
1391                 unsigned long sic_status[3];
1392
1393                 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
1394                 sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
1395 # ifdef SIC_ISR2
1396                 sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
1397 # endif
1398                 for (;; ivg++) {
1399                         if (ivg >= ivg_stop) {
1400                                 atomic_inc(&num_spurious);
1401                                 return 0;
1402                         }
1403                         if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
1404                                 break;
1405                 }
1406 #else
1407                 unsigned long sic_status;
1408
1409                 sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
1410
1411                 for (;; ivg++) {
1412                         if (ivg >= ivg_stop) {
1413                                 atomic_inc(&num_spurious);
1414                                 return 0;
1415                         } else if (sic_status & ivg->isrflag)
1416                                 break;
1417                 }
1418 #endif
1419                 irq = ivg->irqno;
1420         }
1421
1422         if (irq == IRQ_SYSTMR) {
1423 #if !defined(CONFIG_GENERIC_CLOCKEVENTS) || defined(CONFIG_TICKSOURCE_GPTMR0)
1424                 bfin_write_TIMER_STATUS(1); /* Latch TIMIL0 */
1425 #endif
1426                 /* This is basically what we need from the register frame. */
1427                 __raw_get_cpu_var(__ipipe_tick_regs).ipend = regs->ipend;
1428                 __raw_get_cpu_var(__ipipe_tick_regs).pc = regs->pc;
1429                 if (this_domain != ipipe_root_domain)
1430                         __raw_get_cpu_var(__ipipe_tick_regs).ipend &= ~0x10;
1431                 else
1432                         __raw_get_cpu_var(__ipipe_tick_regs).ipend |= 0x10;
1433         }
1434
1435         if (this_domain == ipipe_root_domain) {
1436                 s = __test_and_set_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
1437                 barrier();
1438         }
1439
1440         ipipe_trace_irq_entry(irq);
1441         __ipipe_handle_irq(irq, regs);
1442         ipipe_trace_irq_exit(irq);
1443
1444         if (this_domain == ipipe_root_domain) {
1445                 set_thread_flag(TIF_IRQ_SYNC);
1446                 if (!s) {
1447                         __clear_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
1448                         return !test_bit(IPIPE_STALL_FLAG, &p->status);
1449                 }
1450         }
1451
1452         return 0;
1453 }
1454
1455 #endif /* CONFIG_IPIPE */