[XTENSA] Fix argument list for pgd_ctor constructor.
[linux-2.6.git] / arch / blackfin / mach-common / dpmc.S
1 /*
2  * File:         arch/blackfin/mach-common/dpmc.S
3  * Based on:
4  * Author:       LG Soft India
5  *
6  * Created:      ?
7  * Description:  Watchdog Timer APIs
8  *
9  * Modified:
10  *               Copyright 2004-2006 Analog Devices Inc.
11  *
12  * Bugs:         Enter bugs at http://blackfin.uclinux.org/
13  *
14  * This program is free software; you can redistribute it and/or modify
15  * it under the terms of the GNU General Public License as published by
16  * the Free Software Foundation; either version 2 of the License, or
17  * (at your option) any later version.
18  *
19  * This program is distributed in the hope that it will be useful,
20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
22  * GNU General Public License for more details.
23  *
24  * You should have received a copy of the GNU General Public License
25  * along with this program; if not, see the file COPYING, or write
26  * to the Free Software Foundation, Inc.,
27  * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
28  */
29
30 #include <linux/linkage.h>
31 #include <asm/blackfin.h>
32 #include <asm/mach/irq.h>
33
34 .text
35
36 ENTRY(_unmask_wdog_wakeup_evt)
37         [--SP] = ( R7:0, P5:0 );
38 #if defined(CONFIG_BF561)
39         P0.H = hi(SICA_IWR1);
40         P0.L = lo(SICA_IWR1);
41 #elif defined(CONFIG_BF54x) || defined(CONFIG_BF52x)
42         P0.h = HI(SIC_IWR0);
43         P0.l = LO(SIC_IWR0);
44 #else
45         P0.h = HI(SIC_IWR);
46         P0.l = LO(SIC_IWR);
47 #endif
48         R7 = [P0];
49 #if defined(CONFIG_BF561)
50         BITSET(R7, 27);
51 #else
52         BITSET(R7,(IRQ_WATCH - IVG7));
53 #endif
54         [P0] = R7;
55         SSYNC;
56
57         ( R7:0, P5:0 ) = [SP++];
58         RTS;
59
60 .LWRITE_TO_STAT:
61         /* When watch dog timer is enabled, a write to STAT will load the
62          * contents of CNT to STAT
63          */
64         R7 = 0x0000(z);
65 #if defined(CONFIG_BF561)
66         P0.h = HI(WDOGA_STAT);
67         P0.l = LO(WDOGA_STAT);
68 #else
69         P0.h = HI(WDOG_STAT);
70         P0.l = LO(WDOG_STAT);
71 #endif
72         [P0] = R7;
73         SSYNC;
74         JUMP .LSKIP_WRITE_TO_STAT;
75
76 ENTRY(_program_wdog_timer)
77         [--SP] = ( R7:0, P5:0 );
78 #if defined(CONFIG_BF561)
79         P0.h = HI(WDOGA_CNT);
80         P0.l = LO(WDOGA_CNT);
81 #else
82         P0.h = HI(WDOG_CNT);
83         P0.l = LO(WDOG_CNT);
84 #endif
85         [P0] = R0;
86         SSYNC;
87
88 #if defined(CONFIG_BF561)
89         P0.h = HI(WDOGA_CTL);
90         P0.l = LO(WDOGA_CTL);
91 #else
92         P0.h = HI(WDOG_CTL);
93         P0.l = LO(WDOG_CTL);
94 #endif
95         R7 = W[P0](Z);
96         CC = BITTST(R7,1);
97         if !CC JUMP .LWRITE_TO_STAT;
98         CC = BITTST(R7,2);
99         if !CC JUMP .LWRITE_TO_STAT;
100
101 .LSKIP_WRITE_TO_STAT:
102 #if defined(CONFIG_BF561)
103         P0.h = HI(WDOGA_CTL);
104         P0.l = LO(WDOGA_CTL);
105 #else
106         P0.h = HI(WDOG_CTL);
107         P0.l = LO(WDOG_CTL);
108 #endif
109         R7 = W[P0](Z);
110         BITCLR(R7,1);   /* Enable GP event */
111         BITSET(R7,2);
112         W[P0] = R7.L;
113         SSYNC;
114         NOP;
115
116         R7 = W[P0](Z);
117         BITCLR(R7,4);   /* Enable the wdog counter */
118         W[P0] = R7.L;
119         SSYNC;
120
121         ( R7:0, P5:0 ) = [SP++];
122         RTS;
123
124 ENTRY(_clear_wdog_wakeup_evt)
125         [--SP] = ( R7:0, P5:0 );
126
127 #if defined(CONFIG_BF561)
128         P0.h = HI(WDOGA_CTL);
129         P0.l = LO(WDOGA_CTL);
130 #else
131         P0.h = HI(WDOG_CTL);
132         P0.l = LO(WDOG_CTL);
133 #endif
134         R7 = 0x0AD6(Z);
135         W[P0] = R7.L;
136         SSYNC;
137
138         R7 = W[P0](Z);
139         BITSET(R7,15);
140         W[P0] = R7.L;
141         SSYNC;
142
143         R7 = W[P0](Z);
144         BITSET(R7,1);
145         BITSET(R7,2);
146         W[P0] = R7.L;
147         SSYNC;
148
149         ( R7:0, P5:0 ) = [SP++];
150         RTS;
151
152 ENTRY(_disable_wdog_timer)
153         [--SP] = ( R7:0, P5:0 );
154 #if defined(CONFIG_BF561)
155         P0.h = HI(WDOGA_CTL);
156         P0.l = LO(WDOGA_CTL);
157 #else
158         P0.h = HI(WDOG_CTL);
159         P0.l = LO(WDOG_CTL);
160 #endif
161         R7 = 0xAD6(Z);
162         W[P0] = R7.L;
163         SSYNC;
164         ( R7:0, P5:0 ) = [SP++];
165         RTS;
166
167 #if !defined(CONFIG_BF561)
168
169 .section .l1.text
170
171 ENTRY(_sleep_mode)
172         [--SP] = ( R7:0, P5:0 );
173         [--SP] =  RETS;
174
175         call _set_sic_iwr;
176
177         R0 = 0xFFFF (Z);
178         call _set_rtc_istat;
179
180         P0.H = hi(PLL_CTL);
181         P0.L = lo(PLL_CTL);
182         R1 = W[P0](z);
183         BITSET (R1, 3);
184         W[P0] = R1.L;
185
186         CLI R2;
187         SSYNC;
188         IDLE;
189         STI R2;
190
191         call _test_pll_locked;
192
193         R0 = IWR_ENABLE(0);
194         R1 = IWR_DISABLE_ALL;
195         R2 = IWR_DISABLE_ALL;
196
197         call _set_sic_iwr;
198
199         P0.H = hi(PLL_CTL);
200         P0.L = lo(PLL_CTL);
201         R7 = w[p0](z);
202         BITCLR (R7, 3);
203         BITCLR (R7, 5);
204         w[p0] = R7.L;
205         IDLE;
206         call _test_pll_locked;
207
208         RETS = [SP++];
209         ( R7:0, P5:0 ) = [SP++];
210         RTS;
211
212 ENTRY(_hibernate_mode)
213         [--SP] = ( R7:0, P5:0 );
214         [--SP] =  RETS;
215
216         call _set_sic_iwr;
217
218         R0 = 0xFFFF (Z);
219         call _set_rtc_istat;
220
221         P0.H = hi(VR_CTL);
222         P0.L = lo(VR_CTL);
223         R1 = W[P0](z);
224         BITSET (R1, 8);
225         BITCLR (R1, 0);
226         BITCLR (R1, 1);
227         W[P0] = R1.L;
228         SSYNC;
229
230         CLI R2;
231         IDLE;
232
233         /* Actually, adding anything may not be necessary...SDRAM contents
234          * are lost
235          */
236
237 ENTRY(_deep_sleep)
238         [--SP] = ( R7:0, P5:0 );
239         [--SP] =  RETS;
240
241         CLI R4;
242
243         R0 = IWR_ENABLE(0);
244         R1 = IWR_DISABLE_ALL;
245         R2 = IWR_DISABLE_ALL;
246
247         call _set_sic_iwr;
248
249         call _set_dram_srfs;
250
251         /* Clear all the interrupts,bits sticky */
252         R0 = 0xFFFF (Z);
253         call _set_rtc_istat
254
255         P0.H = hi(PLL_CTL);
256         P0.L = lo(PLL_CTL);
257         R0 = W[P0](z);
258         BITSET (R0, 5);
259         W[P0] = R0.L;
260
261         call _test_pll_locked;
262
263         SSYNC;
264         IDLE;
265
266         call _unset_dram_srfs;
267
268         call _test_pll_locked;
269
270         R0 = IWR_ENABLE(0);
271         R1 = IWR_DISABLE_ALL;
272         R2 = IWR_DISABLE_ALL;
273
274         call _set_sic_iwr;
275
276         P0.H = hi(PLL_CTL);
277         P0.L = lo(PLL_CTL);
278         R0 = w[p0](z);
279         BITCLR (R0, 3);
280         BITCLR (R0, 5);
281         BITCLR (R0, 8);
282         w[p0] = R0;
283         IDLE;
284         call _test_pll_locked;
285
286         STI R4;
287
288         RETS = [SP++];
289         ( R7:0, P5:0 ) = [SP++];
290         RTS;
291
292 ENTRY(_sleep_deeper)
293         [--SP] = ( R7:0, P5:0 );
294         [--SP] =  RETS;
295
296         CLI R4;
297
298         P3 = R0;
299         P4 = R1;
300         P5 = R2;
301
302         R0 = IWR_ENABLE(0);
303         R1 = IWR_DISABLE_ALL;
304         R2 = IWR_DISABLE_ALL;
305
306         call _set_sic_iwr;
307         call _set_dram_srfs;    /* Set SDRAM Self Refresh */
308
309         /* Clear all the interrupts,bits sticky */
310         R0 = 0xFFFF (Z);
311         call _set_rtc_istat;
312         P0.H = hi(PLL_DIV);
313         P0.L = lo(PLL_DIV);
314         R6 = W[P0](z);
315         R0.L = 0xF;
316         W[P0] = R0.l;           /* Set Max VCO to SCLK divider */
317
318         P0.H = hi(PLL_CTL);
319         P0.L = lo(PLL_CTL);
320         R5 = W[P0](z);
321         R0.L = (CONFIG_MIN_VCO_HZ/CONFIG_CLKIN_HZ) << 9;
322         W[P0] = R0.l;           /* Set Min CLKIN to VCO multiplier */
323
324         SSYNC;
325         IDLE;
326
327         call _test_pll_locked;
328
329         P0.H = hi(VR_CTL);
330         P0.L = lo(VR_CTL);
331         R7 = W[P0](z);
332         R1 = 0x6;
333         R1 <<= 16;
334         R2 = 0x0404(Z);
335         R1 = R1|R2;
336
337         R2 = DEPOSIT(R7, R1);
338         W[P0] = R2;             /* Set Min Core Voltage */
339
340         SSYNC;
341         IDLE;
342
343         call _test_pll_locked;
344
345         R0 = P3;
346         R1 = P4;
347         R3 = P5;
348         call _set_sic_iwr;      /* Set Awake from IDLE */
349
350         P0.H = hi(PLL_CTL);
351         P0.L = lo(PLL_CTL);
352         R0 = W[P0](z);
353         BITSET (R0, 3);
354         W[P0] = R0.L;           /* Turn CCLK OFF */
355         SSYNC;
356         IDLE;
357
358         call _test_pll_locked;
359
360         R0 = IWR_ENABLE(0);
361         R1 = IWR_DISABLE_ALL;
362         R2 = IWR_DISABLE_ALL;
363
364         call _set_sic_iwr;      /* Set Awake from IDLE PLL */
365
366         P0.H = hi(VR_CTL);
367         P0.L = lo(VR_CTL);
368         W[P0]= R7;
369
370         SSYNC;
371         IDLE;
372
373         call _test_pll_locked;
374
375         P0.H = hi(PLL_DIV);
376         P0.L = lo(PLL_DIV);
377         W[P0]= R6;              /* Restore CCLK and SCLK divider */
378
379         P0.H = hi(PLL_CTL);
380         P0.L = lo(PLL_CTL);
381         w[p0] = R5;             /* Restore VCO multiplier */
382         IDLE;
383         call _test_pll_locked;
384
385         call _unset_dram_srfs;  /* SDRAM Self Refresh Off */
386
387         STI R4;
388
389         RETS = [SP++];
390         ( R7:0, P5:0 ) = [SP++];
391         RTS;
392
393 ENTRY(_set_dram_srfs)
394         /*  set the dram to self refresh mode */
395 #if defined(CONFIG_BF54x)
396         P0.H = hi(EBIU_RSTCTL);
397         P0.L = lo(EBIU_RSTCTL);
398         R2 = [P0];
399         R3.H = hi(SRREQ);
400         R3.L = lo(SRREQ);
401 #else
402         P0.H = hi(EBIU_SDGCTL);
403         P0.L = lo(EBIU_SDGCTL);
404         R2 = [P0];
405         R3.H = hi(SRFS);
406         R3.L = lo(SRFS);
407 #endif
408         R2 = R2|R3;
409         [P0] = R2;
410         ssync;
411 #if defined(CONFIG_BF54x)
412 .LSRR_MODE:
413         R2 = [P0];
414         CC = BITTST(R2, 4);
415         if !CC JUMP .LSRR_MODE;
416 #endif
417         RTS;
418
419 ENTRY(_unset_dram_srfs)
420         /*  set the dram out of self refresh mode */
421 #if defined(CONFIG_BF54x)
422         P0.H = hi(EBIU_RSTCTL);
423         P0.L = lo(EBIU_RSTCTL);
424         R2 = [P0];
425         R3.H = hi(SRREQ);
426         R3.L = lo(SRREQ);
427 #else
428         P0.H = hi(EBIU_SDGCTL);
429         P0.L = lo(EBIU_SDGCTL);
430         R2 = [P0];
431         R3.H = hi(SRFS);
432         R3.L = lo(SRFS);
433 #endif
434         R3 = ~R3;
435         R2 = R2&R3;
436         [P0] = R2;
437         ssync;
438         RTS;
439
440 ENTRY(_set_sic_iwr)
441 #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x)  || defined(CONFIG_BF561)
442         P0.H = hi(SIC_IWR0);
443         P0.L = lo(SIC_IWR0);
444         P1.H = hi(SIC_IWR1);
445         P1.L = lo(SIC_IWR1);
446         [P1] = R1;
447 #if defined(CONFIG_BF54x)
448         P1.H = hi(SIC_IWR2);
449         P1.L = lo(SIC_IWR2);
450         [P1] = R2;
451 #endif
452 #else
453         P0.H = hi(SIC_IWR);
454         P0.L = lo(SIC_IWR);
455 #endif
456         [P0] = R0;
457
458         SSYNC;
459         RTS;
460
461 ENTRY(_set_rtc_istat)
462         P0.H = hi(RTC_ISTAT);
463         P0.L = lo(RTC_ISTAT);
464         w[P0] = R0.L;
465         SSYNC;
466         RTS;
467
468 ENTRY(_test_pll_locked)
469         P0.H = hi(PLL_STAT);
470         P0.L = lo(PLL_STAT);
471 1:
472         R0 = W[P0] (Z);
473         CC = BITTST(R0,5);
474         IF !CC JUMP 1b;
475         RTS;
476 #endif