Blackfin arch: SMP supporting patchset: BF561 related code
[linux-2.6.git] / arch / blackfin / mach-bf561 / include / mach / blackfin.h
1 /*
2  * File:         include/asm-blackfin/mach-bf561/blackfin.h
3  * Based on:
4  * Author:
5  *
6  * Created:
7  * Description:
8  *
9  * Rev:
10  *
11  * Modified:
12  *
13  * Bugs:         Enter bugs at http://blackfin.uclinux.org/
14  *
15  * This program is free software; you can redistribute it and/or modify
16  * it under the terms of the GNU General Public License as published by
17  * the Free Software Foundation; either version 2, or (at your option)
18  * any later version.
19  *
20  * This program is distributed in the hope that it will be useful,
21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
23  * GNU General Public License for more details.
24  *
25  * You should have received a copy of the GNU General Public License
26  * along with this program; see the file COPYING.
27  * If not, write to the Free Software Foundation,
28  * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29  */
30
31 #ifndef _MACH_BLACKFIN_H_
32 #define _MACH_BLACKFIN_H_
33
34 #define BF561_FAMILY
35
36 #include "bf561.h"
37 #include "mem_map.h"
38 #include "defBF561.h"
39 #include "anomaly.h"
40
41 #if !defined(__ASSEMBLY__)
42 #include "cdefBF561.h"
43 #endif
44
45 #define bfin_read_FIO_FLAG_D() bfin_read_FIO0_FLAG_D()
46 #define bfin_write_FIO_FLAG_D(val) bfin_write_FIO0_FLAG_D(val)
47 #define bfin_read_FIO_DIR() bfin_read_FIO0_DIR()
48 #define bfin_write_FIO_DIR(val) bfin_write_FIO0_DIR(val)
49 #define bfin_read_FIO_INEN() bfin_read_FIO0_INEN()
50 #define bfin_write_FIO_INEN(val) bfin_write_FIO0_INEN(val)
51
52 #define SIC_IWR0 SICA_IWR0
53 #define SIC_IWR1 SICA_IWR1
54 #define SIC_IAR0 SICA_IAR0
55 #define bfin_write_SIC_IMASK0 bfin_write_SICA_IMASK0
56 #define bfin_write_SIC_IMASK1 bfin_write_SICA_IMASK1
57 #define bfin_write_SIC_IWR0   bfin_write_SICA_IWR0
58 #define bfin_write_SIC_IWR1   bfin_write_SICA_IWR1
59
60 #define bfin_read_SIC_IMASK0 bfin_read_SICA_IMASK0
61 #define bfin_read_SIC_IMASK1 bfin_read_SICA_IMASK1
62 #define bfin_read_SIC_IWR0   bfin_read_SICA_IWR0
63 #define bfin_read_SIC_IWR1   bfin_read_SICA_IWR1
64 #define bfin_read_SIC_ISR0   bfin_read_SICA_ISR0
65 #define bfin_read_SIC_ISR1   bfin_read_SICA_ISR1
66
67 #define bfin_read_SIC_IMASK(x)          bfin_read32(SICA_IMASK0 + (x << 2))
68 #define bfin_write_SIC_IMASK(x, val)    bfin_write32((SICA_IMASK0 + (x << 2)), val)
69 #define bfin_read_SICB_IMASK(x)         bfin_read32(SICB_IMASK0 + (x << 2))
70 #define bfin_write_SICB_IMASK(x, val)   bfin_write32((SICB_IMASK0 + (x << 2)), val)
71 #define bfin_read_SIC_ISR(x)            bfin_read32(SICA_ISR0 + (x << 2))
72 #define bfin_write_SIC_ISR(x, val)      bfin_write32((SICA_ISR0 + (x << 2)), val)
73 #define bfin_read_SICB_ISR(x)           bfin_read32(SICB_ISR0 + (x << 2))
74 #define bfin_write_SICB_ISR(x, val)     bfin_write32((SICB_ISR0 + (x << 2)), val)
75
76 #define BFIN_UART_NR_PORTS      1
77
78 #define OFFSET_THR              0x00    /* Transmit Holding register            */
79 #define OFFSET_RBR              0x00    /* Receive Buffer register              */
80 #define OFFSET_DLL              0x00    /* Divisor Latch (Low-Byte)             */
81 #define OFFSET_IER              0x04    /* Interrupt Enable Register            */
82 #define OFFSET_DLH              0x04    /* Divisor Latch (High-Byte)            */
83 #define OFFSET_IIR              0x08    /* Interrupt Identification Register    */
84 #define OFFSET_LCR              0x0C    /* Line Control Register                */
85 #define OFFSET_MCR              0x10    /* Modem Control Register               */
86 #define OFFSET_LSR              0x14    /* Line Status Register                 */
87 #define OFFSET_MSR              0x18    /* Modem Status Register                */
88 #define OFFSET_SCR              0x1C    /* SCR Scratch Register                 */
89 #define OFFSET_GCTL             0x24    /* Global Control Register              */
90
91 #endif                          /* _MACH_BLACKFIN_H_ */