6b97396d817f28f5f5c5842a6867e833f497d929
[linux-2.6.git] / arch / blackfin / mach-bf548 / include / mach / blackfin.h
1 /*
2  * File:         include/asm-blackfin/mach-bf548/blackfin.h
3  * Based on:
4  * Author:
5  *
6  * Created:
7  * Description:
8  *
9  * Rev:
10  *
11  * Modified:
12  *
13  *
14  * Bugs:         Enter bugs at http://blackfin.uclinux.org/
15  *
16  * This program is free software; you can redistribute it and/or modify
17  * it under the terms of the GNU General Public License as published by
18  * the Free Software Foundation; either version 2, or (at your option)
19  * any later version.
20  *
21  * This program is distributed in the hope that it will be useful,
22  * but WITHOUT ANY WARRANTY; without even the implied warranty of
23  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
24  * GNU General Public License for more details.
25  *
26  * You should have received a copy of the GNU General Public License
27  * along with this program; see the file COPYING.
28  * If not, write to the Free Software Foundation,
29  * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30  */
31
32 #ifndef _MACH_BLACKFIN_H_
33 #define _MACH_BLACKFIN_H_
34
35 #include "bf548.h"
36 #include "anomaly.h"
37
38 #ifdef CONFIG_BF542
39 #include "defBF542.h"
40 #endif
41
42 #ifdef CONFIG_BF544
43 #include "defBF544.h"
44 #endif
45
46 #ifdef CONFIG_BF547
47 #include "defBF547.h"
48 #endif
49
50 #ifdef CONFIG_BF548
51 #include "defBF548.h"
52 #endif
53
54 #ifdef CONFIG_BF549
55 #include "defBF549.h"
56 #endif
57
58 #if !defined(__ASSEMBLY__)
59 #ifdef CONFIG_BF542
60 #include "cdefBF542.h"
61 #endif
62 #ifdef CONFIG_BF544
63 #include "cdefBF544.h"
64 #endif
65 #ifdef CONFIG_BF547
66 #include "cdefBF547.h"
67 #endif
68 #ifdef CONFIG_BF548
69 #include "cdefBF548.h"
70 #endif
71 #ifdef CONFIG_BF549
72 #include "cdefBF549.h"
73 #endif
74
75 /* UART 1*/
76 #define bfin_read_UART_THR()            bfin_read_UART1_THR()
77 #define bfin_write_UART_THR(val)        bfin_write_UART1_THR(val)
78 #define bfin_read_UART_RBR()            bfin_read_UART1_RBR()
79 #define bfin_write_UART_RBR(val)        bfin_write_UART1_RBR(val)
80 #define bfin_read_UART_DLL()            bfin_read_UART1_DLL()
81 #define bfin_write_UART_DLL(val)        bfin_write_UART1_DLL(val)
82 #define bfin_read_UART_IER()            bfin_read_UART1_IER()
83 #define bfin_write_UART_IER(val)        bfin_write_UART1_IER(val)
84 #define bfin_read_UART_DLH()            bfin_read_UART1_DLH()
85 #define bfin_write_UART_DLH(val)        bfin_write_UART1_DLH(val)
86 #define bfin_read_UART_IIR()            bfin_read_UART1_IIR()
87 #define bfin_write_UART_IIR(val)        bfin_write_UART1_IIR(val)
88 #define bfin_read_UART_LCR()            bfin_read_UART1_LCR()
89 #define bfin_write_UART_LCR(val)        bfin_write_UART1_LCR(val)
90 #define bfin_read_UART_MCR()            bfin_read_UART1_MCR()
91 #define bfin_write_UART_MCR(val)        bfin_write_UART1_MCR(val)
92 #define bfin_read_UART_LSR()            bfin_read_UART1_LSR()
93 #define bfin_write_UART_LSR(val)        bfin_write_UART1_LSR(val)
94 #define bfin_read_UART_SCR()            bfin_read_UART1_SCR()
95 #define bfin_write_UART_SCR(val)        bfin_write_UART1_SCR(val)
96 #define bfin_read_UART_GCTL()           bfin_read_UART1_GCTL()
97 #define bfin_write_UART_GCTL(val)       bfin_write_UART1_GCTL(val)
98
99 #endif
100
101 /* MAP used DEFINES from BF533 to BF54x - so we don't need to change 
102  * them in the driver, kernel, etc. */
103
104 /* UART_IIR Register */
105 #define STATUS(x)       ((x << 1) & 0x06)
106 #define STATUS_P1       0x02
107 #define STATUS_P0       0x01
108
109 /* UART 0*/
110
111 /* DMA Channel */
112 #define bfin_read_CH_UART_RX()          bfin_read_CH_UART1_RX()
113 #define bfin_write_CH_UART_RX(val)      bfin_write_CH_UART1_RX(val)
114 #define bfin_read_CH_UART_TX()          bfin_read_CH_UART1_TX()
115 #define bfin_write_CH_UART_TX(val)      bfin_write_CH_UART1_TX(val)
116 #define CH_UART_RX                      CH_UART1_RX
117 #define CH_UART_TX                      CH_UART1_TX
118
119 /* System Interrupt Controller */
120 #define bfin_read_IRQ_UART_RX()         bfin_read_IRQ_UART1_RX()
121 #define bfin_write_IRQ_UART_RX(val)     bfin_write_IRQ_UART1_RX(val)
122 #define bfin_read_IRQ_UART_TX()         bfin_read_IRQ_UART1_TX()
123 #define bfin_write_IRQ_UART_TX(val)     bfin_write_IRQ_UART1_TX(val)
124 #define bfin_read_IRQ_UART_ERROR()      bfin_read_IRQ_UART1_ERROR()
125 #define bfin_write_IRQ_UART_ERROR(val)  bfin_write_IRQ_UART1_ERROR(val)
126 #define IRQ_UART_RX                     IRQ_UART1_RX
127 #define IRQ_UART_TX                     IRQ_UART1_TX
128 #define IRQ_UART_ERROR                  IRQ_UART1_ERROR
129
130 /* MMR Registers*/
131 #define bfin_read_UART_THR()            bfin_read_UART1_THR()
132 #define bfin_write_UART_THR(val)        bfin_write_UART1_THR(val)
133 #define bfin_read_UART_RBR()            bfin_read_UART1_RBR()
134 #define bfin_write_UART_RBR(val)        bfin_write_UART1_RBR(val)
135 #define bfin_read_UART_DLL()            bfin_read_UART1_DLL()
136 #define bfin_write_UART_DLL(val)        bfin_write_UART1_DLL(val)
137 #define bfin_read_UART_IER()            bfin_read_UART1_IER()
138 #define bfin_write_UART_IER(val)        bfin_write_UART1_IER(val)
139 #define bfin_read_UART_DLH()            bfin_read_UART1_DLH()
140 #define bfin_write_UART_DLH(val)        bfin_write_UART1_DLH(val)
141 #define bfin_read_UART_IIR()            bfin_read_UART1_IIR()
142 #define bfin_write_UART_IIR(val)        bfin_write_UART1_IIR(val)
143 #define bfin_read_UART_LCR()            bfin_read_UART1_LCR()
144 #define bfin_write_UART_LCR(val)        bfin_write_UART1_LCR(val)
145 #define bfin_read_UART_MCR()            bfin_read_UART1_MCR()
146 #define bfin_write_UART_MCR(val)        bfin_write_UART1_MCR(val)
147 #define bfin_read_UART_LSR()            bfin_read_UART1_LSR()
148 #define bfin_write_UART_LSR(val)        bfin_write_UART1_LSR(val)
149 #define bfin_read_UART_SCR()            bfin_read_UART1_SCR()
150 #define bfin_write_UART_SCR(val)        bfin_write_UART1_SCR(val)
151 #define bfin_read_UART_GCTL()           bfin_read_UART1_GCTL()
152 #define bfin_write_UART_GCTL(val)       bfin_write_UART1_GCTL(val)
153
154 #define BFIN_UART_THR                   UART1_THR
155 #define BFIN_UART_RBR                   UART1_RBR
156 #define BFIN_UART_DLL                   UART1_DLL
157 #define BFIN_UART_IER                   UART1_IER
158 #define BFIN_UART_DLH                   UART1_DLH
159 #define BFIN_UART_IIR                   UART1_IIR
160 #define BFIN_UART_LCR                   UART1_LCR
161 #define BFIN_UART_MCR                   UART1_MCR
162 #define BFIN_UART_LSR                   UART1_LSR
163 #define BFIN_UART_SCR                   UART1_SCR
164 #define BFIN_UART_GCTL                  UART1_GCTL
165
166 #define BFIN_UART_NR_PORTS      4
167
168 #define OFFSET_DLL              0x00    /* Divisor Latch (Low-Byte)             */
169 #define OFFSET_DLH              0x04    /* Divisor Latch (High-Byte)            */
170 #define OFFSET_GCTL             0x08    /* Global Control Register              */
171 #define OFFSET_LCR              0x0C    /* Line Control Register                */
172 #define OFFSET_MCR              0x10    /* Modem Control Register               */
173 #define OFFSET_LSR              0x14    /* Line Status Register                 */
174 #define OFFSET_MSR              0x18    /* Modem Status Register                */
175 #define OFFSET_SCR              0x1C    /* SCR Scratch Register                 */
176 #define OFFSET_IER_SET          0x20    /* Set Interrupt Enable Register        */
177 #define OFFSET_IER_CLEAR        0x24    /* Clear Interrupt Enable Register      */
178 #define OFFSET_THR              0x28    /* Transmit Holding register            */
179 #define OFFSET_RBR              0x2C    /* Receive Buffer register              */
180
181 /* PLL_DIV Masks */
182 #define CCLK_DIV1 CSEL_DIV1     /* CCLK = VCO / 1 */
183 #define CCLK_DIV2 CSEL_DIV2     /* CCLK = VCO / 2 */
184 #define CCLK_DIV4 CSEL_DIV4     /* CCLK = VCO / 4 */
185 #define CCLK_DIV8 CSEL_DIV8     /* CCLK = VCO / 8 */
186
187 #endif