Add 'discard' request handling
[linux-2.6.git] / arch / blackfin / mach-bf537 / include / mach / defBF534.h
1 /*
2  * File:         include/asm-blackfin/mach-bf537/cdefBF537.h
3  * Based on:
4  * Author:
5  *
6  * Created:
7  * Description:
8  *
9  * Rev:
10  *
11  * Modified:
12  *
13  * Bugs:         Enter bugs at http://blackfin.uclinux.org/
14  *
15  * This program is free software; you can redistribute it and/or modify
16  * it under the terms of the GNU General Public License as published by
17  * the Free Software Foundation; either version 2, or (at your option)
18  * any later version.
19  *
20  * This program is distributed in the hope that it will be useful,
21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
23  * GNU General Public License for more details.
24  *
25  * You should have received a copy of the GNU General Public License
26  * along with this program; see the file COPYING.
27  * If not, write to the Free Software Foundation,
28  * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29  */
30
31 #ifndef _DEF_BF534_H
32 #define _DEF_BF534_H
33
34 /* Include all Core registers and bit definitions */
35 #include <asm/def_LPBlackfin.h>
36
37 /************************************************************************************
38 ** System MMR Register Map
39 *************************************************************************************/
40 /* Clock and System Control     (0xFFC00000 - 0xFFC000FF)                                                               */
41 #define PLL_CTL                         0xFFC00000      /* PLL Control Register                                         */
42 #define PLL_DIV                         0xFFC00004      /* PLL Divide Register                                          */
43 #define VR_CTL                          0xFFC00008      /* Voltage Regulator Control Register           */
44 #define PLL_STAT                        0xFFC0000C      /* PLL Status Register                                          */
45 #define PLL_LOCKCNT                     0xFFC00010      /* PLL Lock Count Register                                      */
46 #define CHIPID                          0xFFC00014      /* Chip ID Register                                             */
47
48 /* System Interrupt Controller (0xFFC00100 - 0xFFC001FF)                                                        */
49 #define SWRST                           0xFFC00100      /* Software Reset Register                                      */
50 #define SYSCR                           0xFFC00104      /* System Configuration Register                        */
51 #define SIC_RVECT                       0xFFC00108      /* Interrupt Reset Vector Address Register      */
52 #define SIC_IMASK                       0xFFC0010C      /* Interrupt Mask Register                                      */
53 #define SIC_IAR0                        0xFFC00110      /* Interrupt Assignment Register 0                      */
54 #define SIC_IAR1                        0xFFC00114      /* Interrupt Assignment Register 1                      */
55 #define SIC_IAR2                        0xFFC00118      /* Interrupt Assignment Register 2                      */
56 #define SIC_IAR3                        0xFFC0011C      /* Interrupt Assignment Register 3                      */
57 #define SIC_ISR                         0xFFC00120      /* Interrupt Status Register                            */
58 #define SIC_IWR                         0xFFC00124      /* Interrupt Wakeup Register                            */
59
60 /* Watchdog Timer                       (0xFFC00200 - 0xFFC002FF)                                                               */
61 #define WDOG_CTL                        0xFFC00200      /* Watchdog Control Register                            */
62 #define WDOG_CNT                        0xFFC00204      /* Watchdog Count Register                                      */
63 #define WDOG_STAT                       0xFFC00208      /* Watchdog Status Register                                     */
64
65 /* Real Time Clock              (0xFFC00300 - 0xFFC003FF)                                                                       */
66 #define RTC_STAT                        0xFFC00300      /* RTC Status Register                                          */
67 #define RTC_ICTL                        0xFFC00304      /* RTC Interrupt Control Register                       */
68 #define RTC_ISTAT                       0xFFC00308      /* RTC Interrupt Status Register                        */
69 #define RTC_SWCNT                       0xFFC0030C      /* RTC Stopwatch Count Register                         */
70 #define RTC_ALARM                       0xFFC00310      /* RTC Alarm Time Register                                      */
71 #define RTC_FAST                        0xFFC00314      /* RTC Prescaler Enable Register                        */
72 #define RTC_PREN                        0xFFC00314      /* RTC Prescaler Enable Alternate Macro         */
73
74 /* UART0 Controller             (0xFFC00400 - 0xFFC004FF)                                                                       */
75 #define UART0_THR                       0xFFC00400      /* Transmit Holding register                            */
76 #define UART0_RBR                       0xFFC00400      /* Receive Buffer register                                      */
77 #define UART0_DLL                       0xFFC00400      /* Divisor Latch (Low-Byte)                                     */
78 #define UART0_IER                       0xFFC00404      /* Interrupt Enable Register                            */
79 #define UART0_DLH                       0xFFC00404      /* Divisor Latch (High-Byte)                            */
80 #define UART0_IIR                       0xFFC00408      /* Interrupt Identification Register            */
81 #define UART0_LCR                       0xFFC0040C      /* Line Control Register                                        */
82 #define UART0_MCR                       0xFFC00410      /* Modem Control Register                                       */
83 #define UART0_LSR                       0xFFC00414      /* Line Status Register                                         */
84 #define UART0_MSR                       0xFFC00418      /* Modem Status Register                                        */
85 #define UART0_SCR                       0xFFC0041C      /* SCR Scratch Register                                         */
86 #define UART0_GCTL                      0xFFC00424      /* Global Control Register                                      */
87
88 /* SPI Controller                       (0xFFC00500 - 0xFFC005FF)                                                               */
89 #define SPI0_REGBASE                    0xFFC00500
90 #define SPI_CTL                         0xFFC00500      /* SPI Control Register                                         */
91 #define SPI_FLG                         0xFFC00504      /* SPI Flag register                                            */
92 #define SPI_STAT                        0xFFC00508      /* SPI Status register                                          */
93 #define SPI_TDBR                        0xFFC0050C      /* SPI Transmit Data Buffer Register            */
94 #define SPI_RDBR                        0xFFC00510      /* SPI Receive Data Buffer Register                     */
95 #define SPI_BAUD                        0xFFC00514      /* SPI Baud rate Register                                       */
96 #define SPI_SHADOW                      0xFFC00518      /* SPI_RDBR Shadow Register                                     */
97
98 /* TIMER0-7 Registers           (0xFFC00600 - 0xFFC006FF)                                                               */
99 #define TIMER0_CONFIG           0xFFC00600      /* Timer 0 Configuration Register                       */
100 #define TIMER0_COUNTER          0xFFC00604      /* Timer 0 Counter Register                                     */
101 #define TIMER0_PERIOD           0xFFC00608      /* Timer 0 Period Register                                      */
102 #define TIMER0_WIDTH            0xFFC0060C      /* Timer 0 Width Register                                       */
103
104 #define TIMER1_CONFIG           0xFFC00610      /* Timer 1 Configuration Register                       */
105 #define TIMER1_COUNTER          0xFFC00614      /* Timer 1 Counter Register                             */
106 #define TIMER1_PERIOD           0xFFC00618      /* Timer 1 Period Register                              */
107 #define TIMER1_WIDTH            0xFFC0061C      /* Timer 1 Width Register                               */
108
109 #define TIMER2_CONFIG           0xFFC00620      /* Timer 2 Configuration Register                       */
110 #define TIMER2_COUNTER          0xFFC00624      /* Timer 2 Counter Register                             */
111 #define TIMER2_PERIOD           0xFFC00628      /* Timer 2 Period Register                              */
112 #define TIMER2_WIDTH            0xFFC0062C      /* Timer 2 Width Register                               */
113
114 #define TIMER3_CONFIG           0xFFC00630      /* Timer 3 Configuration Register                       */
115 #define TIMER3_COUNTER          0xFFC00634      /* Timer 3 Counter Register                                     */
116 #define TIMER3_PERIOD           0xFFC00638      /* Timer 3 Period Register                                      */
117 #define TIMER3_WIDTH            0xFFC0063C      /* Timer 3 Width Register                                       */
118
119 #define TIMER4_CONFIG           0xFFC00640      /* Timer 4 Configuration Register                       */
120 #define TIMER4_COUNTER          0xFFC00644      /* Timer 4 Counter Register                             */
121 #define TIMER4_PERIOD           0xFFC00648      /* Timer 4 Period Register                              */
122 #define TIMER4_WIDTH            0xFFC0064C      /* Timer 4 Width Register                               */
123
124 #define TIMER5_CONFIG           0xFFC00650      /* Timer 5 Configuration Register                       */
125 #define TIMER5_COUNTER          0xFFC00654      /* Timer 5 Counter Register                             */
126 #define TIMER5_PERIOD           0xFFC00658      /* Timer 5 Period Register                              */
127 #define TIMER5_WIDTH            0xFFC0065C      /* Timer 5 Width Register                               */
128
129 #define TIMER6_CONFIG           0xFFC00660      /* Timer 6 Configuration Register                       */
130 #define TIMER6_COUNTER          0xFFC00664      /* Timer 6 Counter Register                             */
131 #define TIMER6_PERIOD           0xFFC00668      /* Timer 6 Period Register                              */
132 #define TIMER6_WIDTH            0xFFC0066C      /* Timer 6 Width Register                               */
133
134 #define TIMER7_CONFIG           0xFFC00670      /* Timer 7 Configuration Register                       */
135 #define TIMER7_COUNTER          0xFFC00674      /* Timer 7 Counter Register                             */
136 #define TIMER7_PERIOD           0xFFC00678      /* Timer 7 Period Register                              */
137 #define TIMER7_WIDTH            0xFFC0067C      /* Timer 7 Width Register                               */
138
139 #define TIMER_ENABLE            0xFFC00680      /* Timer Enable Register                                        */
140 #define TIMER_DISABLE           0xFFC00684      /* Timer Disable Register                                       */
141 #define TIMER_STATUS            0xFFC00688      /* Timer Status Register                                        */
142
143 /* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF)                                                                                         */
144 #define PORTFIO                                 0xFFC00700      /* Port F I/O Pin State Specify Register                                */
145 #define PORTFIO_CLEAR                   0xFFC00704      /* Port F I/O Peripheral Interrupt Clear Register               */
146 #define PORTFIO_SET                             0xFFC00708      /* Port F I/O Peripheral Interrupt Set Register                 */
147 #define PORTFIO_TOGGLE                  0xFFC0070C      /* Port F I/O Pin State Toggle Register                                 */
148 #define PORTFIO_MASKA                   0xFFC00710      /* Port F I/O Mask State Specify Interrupt A Register   */
149 #define PORTFIO_MASKA_CLEAR             0xFFC00714      /* Port F I/O Mask Disable Interrupt A Register                 */
150 #define PORTFIO_MASKA_SET               0xFFC00718      /* Port F I/O Mask Enable Interrupt A Register                  */
151 #define PORTFIO_MASKA_TOGGLE    0xFFC0071C      /* Port F I/O Mask Toggle Enable Interrupt A Register   */
152 #define PORTFIO_MASKB                   0xFFC00720      /* Port F I/O Mask State Specify Interrupt B Register   */
153 #define PORTFIO_MASKB_CLEAR             0xFFC00724      /* Port F I/O Mask Disable Interrupt B Register                 */
154 #define PORTFIO_MASKB_SET               0xFFC00728      /* Port F I/O Mask Enable Interrupt B Register                  */
155 #define PORTFIO_MASKB_TOGGLE    0xFFC0072C      /* Port F I/O Mask Toggle Enable Interrupt B Register   */
156 #define PORTFIO_DIR                             0xFFC00730      /* Port F I/O Direction Register                                                */
157 #define PORTFIO_POLAR                   0xFFC00734      /* Port F I/O Source Polarity Register                                  */
158 #define PORTFIO_EDGE                    0xFFC00738      /* Port F I/O Source Sensitivity Register                               */
159 #define PORTFIO_BOTH                    0xFFC0073C      /* Port F I/O Set on BOTH Edges Register                                */
160 #define PORTFIO_INEN                    0xFFC00740      /* Port F I/O Input Enable Register                                     */
161
162 /* SPORT0 Controller            (0xFFC00800 - 0xFFC008FF)                                                                               */
163 #define SPORT0_TCR1                     0xFFC00800      /* SPORT0 Transmit Configuration 1 Register                     */
164 #define SPORT0_TCR2                     0xFFC00804      /* SPORT0 Transmit Configuration 2 Register                     */
165 #define SPORT0_TCLKDIV          0xFFC00808      /* SPORT0 Transmit Clock Divider                                        */
166 #define SPORT0_TFSDIV           0xFFC0080C      /* SPORT0 Transmit Frame Sync Divider                           */
167 #define SPORT0_TX                       0xFFC00810      /* SPORT0 TX Data Register                                                      */
168 #define SPORT0_RX                       0xFFC00818      /* SPORT0 RX Data Register                                                      */
169 #define SPORT0_RCR1                     0xFFC00820      /* SPORT0 Transmit Configuration 1 Register                     */
170 #define SPORT0_RCR2                     0xFFC00824      /* SPORT0 Transmit Configuration 2 Register                     */
171 #define SPORT0_RCLKDIV          0xFFC00828      /* SPORT0 Receive Clock Divider                                         */
172 #define SPORT0_RFSDIV           0xFFC0082C      /* SPORT0 Receive Frame Sync Divider                            */
173 #define SPORT0_STAT                     0xFFC00830      /* SPORT0 Status Register                                                       */
174 #define SPORT0_CHNL                     0xFFC00834      /* SPORT0 Current Channel Register                                      */
175 #define SPORT0_MCMC1            0xFFC00838      /* SPORT0 Multi-Channel Configuration Register 1        */
176 #define SPORT0_MCMC2            0xFFC0083C      /* SPORT0 Multi-Channel Configuration Register 2        */
177 #define SPORT0_MTCS0            0xFFC00840      /* SPORT0 Multi-Channel Transmit Select Register 0      */
178 #define SPORT0_MTCS1            0xFFC00844      /* SPORT0 Multi-Channel Transmit Select Register 1      */
179 #define SPORT0_MTCS2            0xFFC00848      /* SPORT0 Multi-Channel Transmit Select Register 2      */
180 #define SPORT0_MTCS3            0xFFC0084C      /* SPORT0 Multi-Channel Transmit Select Register 3      */
181 #define SPORT0_MRCS0            0xFFC00850      /* SPORT0 Multi-Channel Receive Select Register 0       */
182 #define SPORT0_MRCS1            0xFFC00854      /* SPORT0 Multi-Channel Receive Select Register 1       */
183 #define SPORT0_MRCS2            0xFFC00858      /* SPORT0 Multi-Channel Receive Select Register 2       */
184 #define SPORT0_MRCS3            0xFFC0085C      /* SPORT0 Multi-Channel Receive Select Register 3       */
185
186 /* SPORT1 Controller            (0xFFC00900 - 0xFFC009FF)                                                                               */
187 #define SPORT1_TCR1                     0xFFC00900      /* SPORT1 Transmit Configuration 1 Register                     */
188 #define SPORT1_TCR2                     0xFFC00904      /* SPORT1 Transmit Configuration 2 Register                     */
189 #define SPORT1_TCLKDIV          0xFFC00908      /* SPORT1 Transmit Clock Divider                                        */
190 #define SPORT1_TFSDIV           0xFFC0090C      /* SPORT1 Transmit Frame Sync Divider                           */
191 #define SPORT1_TX                       0xFFC00910      /* SPORT1 TX Data Register                                                      */
192 #define SPORT1_RX                       0xFFC00918      /* SPORT1 RX Data Register                                                      */
193 #define SPORT1_RCR1                     0xFFC00920      /* SPORT1 Transmit Configuration 1 Register                     */
194 #define SPORT1_RCR2                     0xFFC00924      /* SPORT1 Transmit Configuration 2 Register                     */
195 #define SPORT1_RCLKDIV          0xFFC00928      /* SPORT1 Receive Clock Divider                                         */
196 #define SPORT1_RFSDIV           0xFFC0092C      /* SPORT1 Receive Frame Sync Divider                            */
197 #define SPORT1_STAT                     0xFFC00930      /* SPORT1 Status Register                                                       */
198 #define SPORT1_CHNL                     0xFFC00934      /* SPORT1 Current Channel Register                                      */
199 #define SPORT1_MCMC1            0xFFC00938      /* SPORT1 Multi-Channel Configuration Register 1        */
200 #define SPORT1_MCMC2            0xFFC0093C      /* SPORT1 Multi-Channel Configuration Register 2        */
201 #define SPORT1_MTCS0            0xFFC00940      /* SPORT1 Multi-Channel Transmit Select Register 0      */
202 #define SPORT1_MTCS1            0xFFC00944      /* SPORT1 Multi-Channel Transmit Select Register 1      */
203 #define SPORT1_MTCS2            0xFFC00948      /* SPORT1 Multi-Channel Transmit Select Register 2      */
204 #define SPORT1_MTCS3            0xFFC0094C      /* SPORT1 Multi-Channel Transmit Select Register 3      */
205 #define SPORT1_MRCS0            0xFFC00950      /* SPORT1 Multi-Channel Receive Select Register 0       */
206 #define SPORT1_MRCS1            0xFFC00954      /* SPORT1 Multi-Channel Receive Select Register 1       */
207 #define SPORT1_MRCS2            0xFFC00958      /* SPORT1 Multi-Channel Receive Select Register 2       */
208 #define SPORT1_MRCS3            0xFFC0095C      /* SPORT1 Multi-Channel Receive Select Register 3       */
209
210 /* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF)                                                                */
211 #define EBIU_AMGCTL                     0xFFC00A00      /* Asynchronous Memory Global Control Register  */
212 #define EBIU_AMBCTL0            0xFFC00A04      /* Asynchronous Memory Bank Control Register 0  */
213 #define EBIU_AMBCTL1            0xFFC00A08      /* Asynchronous Memory Bank Control Register 1  */
214 #define EBIU_SDGCTL                     0xFFC00A10      /* SDRAM Global Control Register                                */
215 #define EBIU_SDBCTL                     0xFFC00A14      /* SDRAM Bank Control Register                                  */
216 #define EBIU_SDRRC                      0xFFC00A18      /* SDRAM Refresh Rate Control Register                  */
217 #define EBIU_SDSTAT                     0xFFC00A1C      /* SDRAM Status Register                                                */
218
219 /* DMA Traffic Control Registers                                                                                                        */
220 #define DMA_TC_PER                      0xFFC00B0C      /* Traffic Control Periods Register                     */
221 #define DMA_TC_CNT                      0xFFC00B10      /* Traffic Control Current Counts Register      */
222
223 /* Alternate deprecated register names (below) provided for backwards code compatibility */
224 #define DMA_TCPER                       0xFFC00B0C      /* Traffic Control Periods Register                     */
225 #define DMA_TCCNT                       0xFFC00B10      /* Traffic Control Current Counts Register      */
226
227 /* DMA Controller (0xFFC00C00 - 0xFFC00FFF)                                                                                                                     */
228 #define DMA0_NEXT_DESC_PTR              0xFFC00C00      /* DMA Channel 0 Next Descriptor Pointer Register               */
229 #define DMA0_START_ADDR                 0xFFC00C04      /* DMA Channel 0 Start Address Register                                 */
230 #define DMA0_CONFIG                             0xFFC00C08      /* DMA Channel 0 Configuration Register                                 */
231 #define DMA0_X_COUNT                    0xFFC00C10      /* DMA Channel 0 X Count Register                                               */
232 #define DMA0_X_MODIFY                   0xFFC00C14      /* DMA Channel 0 X Modify Register                                              */
233 #define DMA0_Y_COUNT                    0xFFC00C18      /* DMA Channel 0 Y Count Register                                               */
234 #define DMA0_Y_MODIFY                   0xFFC00C1C      /* DMA Channel 0 Y Modify Register                                              */
235 #define DMA0_CURR_DESC_PTR              0xFFC00C20      /* DMA Channel 0 Current Descriptor Pointer Register    */
236 #define DMA0_CURR_ADDR                  0xFFC00C24      /* DMA Channel 0 Current Address Register                               */
237 #define DMA0_IRQ_STATUS                 0xFFC00C28      /* DMA Channel 0 Interrupt/Status Register                              */
238 #define DMA0_PERIPHERAL_MAP             0xFFC00C2C      /* DMA Channel 0 Peripheral Map Register                                */
239 #define DMA0_CURR_X_COUNT               0xFFC00C30      /* DMA Channel 0 Current X Count Register                               */
240 #define DMA0_CURR_Y_COUNT               0xFFC00C38      /* DMA Channel 0 Current Y Count Register                               */
241
242 #define DMA1_NEXT_DESC_PTR              0xFFC00C40      /* DMA Channel 1 Next Descriptor Pointer Register               */
243 #define DMA1_START_ADDR                 0xFFC00C44      /* DMA Channel 1 Start Address Register                                 */
244 #define DMA1_CONFIG                             0xFFC00C48      /* DMA Channel 1 Configuration Register                                 */
245 #define DMA1_X_COUNT                    0xFFC00C50      /* DMA Channel 1 X Count Register                                               */
246 #define DMA1_X_MODIFY                   0xFFC00C54      /* DMA Channel 1 X Modify Register                                              */
247 #define DMA1_Y_COUNT                    0xFFC00C58      /* DMA Channel 1 Y Count Register                                               */
248 #define DMA1_Y_MODIFY                   0xFFC00C5C      /* DMA Channel 1 Y Modify Register                                              */
249 #define DMA1_CURR_DESC_PTR              0xFFC00C60      /* DMA Channel 1 Current Descriptor Pointer Register    */
250 #define DMA1_CURR_ADDR                  0xFFC00C64      /* DMA Channel 1 Current Address Register                               */
251 #define DMA1_IRQ_STATUS                 0xFFC00C68      /* DMA Channel 1 Interrupt/Status Register                              */
252 #define DMA1_PERIPHERAL_MAP             0xFFC00C6C      /* DMA Channel 1 Peripheral Map Register                                */
253 #define DMA1_CURR_X_COUNT               0xFFC00C70      /* DMA Channel 1 Current X Count Register                               */
254 #define DMA1_CURR_Y_COUNT               0xFFC00C78      /* DMA Channel 1 Current Y Count Register                               */
255
256 #define DMA2_NEXT_DESC_PTR              0xFFC00C80      /* DMA Channel 2 Next Descriptor Pointer Register               */
257 #define DMA2_START_ADDR                 0xFFC00C84      /* DMA Channel 2 Start Address Register                                 */
258 #define DMA2_CONFIG                             0xFFC00C88      /* DMA Channel 2 Configuration Register                                 */
259 #define DMA2_X_COUNT                    0xFFC00C90      /* DMA Channel 2 X Count Register                                               */
260 #define DMA2_X_MODIFY                   0xFFC00C94      /* DMA Channel 2 X Modify Register                                              */
261 #define DMA2_Y_COUNT                    0xFFC00C98      /* DMA Channel 2 Y Count Register                                               */
262 #define DMA2_Y_MODIFY                   0xFFC00C9C      /* DMA Channel 2 Y Modify Register                                              */
263 #define DMA2_CURR_DESC_PTR              0xFFC00CA0      /* DMA Channel 2 Current Descriptor Pointer Register    */
264 #define DMA2_CURR_ADDR                  0xFFC00CA4      /* DMA Channel 2 Current Address Register                               */
265 #define DMA2_IRQ_STATUS                 0xFFC00CA8      /* DMA Channel 2 Interrupt/Status Register                              */
266 #define DMA2_PERIPHERAL_MAP             0xFFC00CAC      /* DMA Channel 2 Peripheral Map Register                                */
267 #define DMA2_CURR_X_COUNT               0xFFC00CB0      /* DMA Channel 2 Current X Count Register                               */
268 #define DMA2_CURR_Y_COUNT               0xFFC00CB8      /* DMA Channel 2 Current Y Count Register                               */
269
270 #define DMA3_NEXT_DESC_PTR              0xFFC00CC0      /* DMA Channel 3 Next Descriptor Pointer Register               */
271 #define DMA3_START_ADDR                 0xFFC00CC4      /* DMA Channel 3 Start Address Register                                 */
272 #define DMA3_CONFIG                             0xFFC00CC8      /* DMA Channel 3 Configuration Register                                 */
273 #define DMA3_X_COUNT                    0xFFC00CD0      /* DMA Channel 3 X Count Register                                               */
274 #define DMA3_X_MODIFY                   0xFFC00CD4      /* DMA Channel 3 X Modify Register                                              */
275 #define DMA3_Y_COUNT                    0xFFC00CD8      /* DMA Channel 3 Y Count Register                                               */
276 #define DMA3_Y_MODIFY                   0xFFC00CDC      /* DMA Channel 3 Y Modify Register                                              */
277 #define DMA3_CURR_DESC_PTR              0xFFC00CE0      /* DMA Channel 3 Current Descriptor Pointer Register    */
278 #define DMA3_CURR_ADDR                  0xFFC00CE4      /* DMA Channel 3 Current Address Register                               */
279 #define DMA3_IRQ_STATUS                 0xFFC00CE8      /* DMA Channel 3 Interrupt/Status Register                              */
280 #define DMA3_PERIPHERAL_MAP             0xFFC00CEC      /* DMA Channel 3 Peripheral Map Register                                */
281 #define DMA3_CURR_X_COUNT               0xFFC00CF0      /* DMA Channel 3 Current X Count Register                               */
282 #define DMA3_CURR_Y_COUNT               0xFFC00CF8      /* DMA Channel 3 Current Y Count Register                               */
283
284 #define DMA4_NEXT_DESC_PTR              0xFFC00D00      /* DMA Channel 4 Next Descriptor Pointer Register               */
285 #define DMA4_START_ADDR                 0xFFC00D04      /* DMA Channel 4 Start Address Register                                 */
286 #define DMA4_CONFIG                             0xFFC00D08      /* DMA Channel 4 Configuration Register                                 */
287 #define DMA4_X_COUNT                    0xFFC00D10      /* DMA Channel 4 X Count Register                                               */
288 #define DMA4_X_MODIFY                   0xFFC00D14      /* DMA Channel 4 X Modify Register                                              */
289 #define DMA4_Y_COUNT                    0xFFC00D18      /* DMA Channel 4 Y Count Register                                               */
290 #define DMA4_Y_MODIFY                   0xFFC00D1C      /* DMA Channel 4 Y Modify Register                                              */
291 #define DMA4_CURR_DESC_PTR              0xFFC00D20      /* DMA Channel 4 Current Descriptor Pointer Register    */
292 #define DMA4_CURR_ADDR                  0xFFC00D24      /* DMA Channel 4 Current Address Register                               */
293 #define DMA4_IRQ_STATUS                 0xFFC00D28      /* DMA Channel 4 Interrupt/Status Register                              */
294 #define DMA4_PERIPHERAL_MAP             0xFFC00D2C      /* DMA Channel 4 Peripheral Map Register                                */
295 #define DMA4_CURR_X_COUNT               0xFFC00D30      /* DMA Channel 4 Current X Count Register                               */
296 #define DMA4_CURR_Y_COUNT               0xFFC00D38      /* DMA Channel 4 Current Y Count Register                               */
297
298 #define DMA5_NEXT_DESC_PTR              0xFFC00D40      /* DMA Channel 5 Next Descriptor Pointer Register               */
299 #define DMA5_START_ADDR                 0xFFC00D44      /* DMA Channel 5 Start Address Register                                 */
300 #define DMA5_CONFIG                             0xFFC00D48      /* DMA Channel 5 Configuration Register                                 */
301 #define DMA5_X_COUNT                    0xFFC00D50      /* DMA Channel 5 X Count Register                                               */
302 #define DMA5_X_MODIFY                   0xFFC00D54      /* DMA Channel 5 X Modify Register                                              */
303 #define DMA5_Y_COUNT                    0xFFC00D58      /* DMA Channel 5 Y Count Register                                               */
304 #define DMA5_Y_MODIFY                   0xFFC00D5C      /* DMA Channel 5 Y Modify Register                                              */
305 #define DMA5_CURR_DESC_PTR              0xFFC00D60      /* DMA Channel 5 Current Descriptor Pointer Register    */
306 #define DMA5_CURR_ADDR                  0xFFC00D64      /* DMA Channel 5 Current Address Register                               */
307 #define DMA5_IRQ_STATUS                 0xFFC00D68      /* DMA Channel 5 Interrupt/Status Register                              */
308 #define DMA5_PERIPHERAL_MAP             0xFFC00D6C      /* DMA Channel 5 Peripheral Map Register                                */
309 #define DMA5_CURR_X_COUNT               0xFFC00D70      /* DMA Channel 5 Current X Count Register                               */
310 #define DMA5_CURR_Y_COUNT               0xFFC00D78      /* DMA Channel 5 Current Y Count Register                               */
311
312 #define DMA6_NEXT_DESC_PTR              0xFFC00D80      /* DMA Channel 6 Next Descriptor Pointer Register               */
313 #define DMA6_START_ADDR                 0xFFC00D84      /* DMA Channel 6 Start Address Register                                 */
314 #define DMA6_CONFIG                             0xFFC00D88      /* DMA Channel 6 Configuration Register                                 */
315 #define DMA6_X_COUNT                    0xFFC00D90      /* DMA Channel 6 X Count Register                                               */
316 #define DMA6_X_MODIFY                   0xFFC00D94      /* DMA Channel 6 X Modify Register                                              */
317 #define DMA6_Y_COUNT                    0xFFC00D98      /* DMA Channel 6 Y Count Register                                               */
318 #define DMA6_Y_MODIFY                   0xFFC00D9C      /* DMA Channel 6 Y Modify Register                                              */
319 #define DMA6_CURR_DESC_PTR              0xFFC00DA0      /* DMA Channel 6 Current Descriptor Pointer Register    */
320 #define DMA6_CURR_ADDR                  0xFFC00DA4      /* DMA Channel 6 Current Address Register                               */
321 #define DMA6_IRQ_STATUS                 0xFFC00DA8      /* DMA Channel 6 Interrupt/Status Register                              */
322 #define DMA6_PERIPHERAL_MAP             0xFFC00DAC      /* DMA Channel 6 Peripheral Map Register                                */
323 #define DMA6_CURR_X_COUNT               0xFFC00DB0      /* DMA Channel 6 Current X Count Register                               */
324 #define DMA6_CURR_Y_COUNT               0xFFC00DB8      /* DMA Channel 6 Current Y Count Register                               */
325
326 #define DMA7_NEXT_DESC_PTR              0xFFC00DC0      /* DMA Channel 7 Next Descriptor Pointer Register               */
327 #define DMA7_START_ADDR                 0xFFC00DC4      /* DMA Channel 7 Start Address Register                                 */
328 #define DMA7_CONFIG                             0xFFC00DC8      /* DMA Channel 7 Configuration Register                                 */
329 #define DMA7_X_COUNT                    0xFFC00DD0      /* DMA Channel 7 X Count Register                                               */
330 #define DMA7_X_MODIFY                   0xFFC00DD4      /* DMA Channel 7 X Modify Register                                              */
331 #define DMA7_Y_COUNT                    0xFFC00DD8      /* DMA Channel 7 Y Count Register                                               */
332 #define DMA7_Y_MODIFY                   0xFFC00DDC      /* DMA Channel 7 Y Modify Register                                              */
333 #define DMA7_CURR_DESC_PTR              0xFFC00DE0      /* DMA Channel 7 Current Descriptor Pointer Register    */
334 #define DMA7_CURR_ADDR                  0xFFC00DE4      /* DMA Channel 7 Current Address Register                               */
335 #define DMA7_IRQ_STATUS                 0xFFC00DE8      /* DMA Channel 7 Interrupt/Status Register                              */
336 #define DMA7_PERIPHERAL_MAP             0xFFC00DEC      /* DMA Channel 7 Peripheral Map Register                                */
337 #define DMA7_CURR_X_COUNT               0xFFC00DF0      /* DMA Channel 7 Current X Count Register                               */
338 #define DMA7_CURR_Y_COUNT               0xFFC00DF8      /* DMA Channel 7 Current Y Count Register                               */
339
340 #define DMA8_NEXT_DESC_PTR              0xFFC00E00      /* DMA Channel 8 Next Descriptor Pointer Register               */
341 #define DMA8_START_ADDR                 0xFFC00E04      /* DMA Channel 8 Start Address Register                                 */
342 #define DMA8_CONFIG                             0xFFC00E08      /* DMA Channel 8 Configuration Register                                 */
343 #define DMA8_X_COUNT                    0xFFC00E10      /* DMA Channel 8 X Count Register                                               */
344 #define DMA8_X_MODIFY                   0xFFC00E14      /* DMA Channel 8 X Modify Register                                              */
345 #define DMA8_Y_COUNT                    0xFFC00E18      /* DMA Channel 8 Y Count Register                                               */
346 #define DMA8_Y_MODIFY                   0xFFC00E1C      /* DMA Channel 8 Y Modify Register                                              */
347 #define DMA8_CURR_DESC_PTR              0xFFC00E20      /* DMA Channel 8 Current Descriptor Pointer Register    */
348 #define DMA8_CURR_ADDR                  0xFFC00E24      /* DMA Channel 8 Current Address Register                               */
349 #define DMA8_IRQ_STATUS                 0xFFC00E28      /* DMA Channel 8 Interrupt/Status Register                              */
350 #define DMA8_PERIPHERAL_MAP             0xFFC00E2C      /* DMA Channel 8 Peripheral Map Register                                */
351 #define DMA8_CURR_X_COUNT               0xFFC00E30      /* DMA Channel 8 Current X Count Register                               */
352 #define DMA8_CURR_Y_COUNT               0xFFC00E38      /* DMA Channel 8 Current Y Count Register                               */
353
354 #define DMA9_NEXT_DESC_PTR              0xFFC00E40      /* DMA Channel 9 Next Descriptor Pointer Register               */
355 #define DMA9_START_ADDR                 0xFFC00E44      /* DMA Channel 9 Start Address Register                                 */
356 #define DMA9_CONFIG                             0xFFC00E48      /* DMA Channel 9 Configuration Register                                 */
357 #define DMA9_X_COUNT                    0xFFC00E50      /* DMA Channel 9 X Count Register                                               */
358 #define DMA9_X_MODIFY                   0xFFC00E54      /* DMA Channel 9 X Modify Register                                              */
359 #define DMA9_Y_COUNT                    0xFFC00E58      /* DMA Channel 9 Y Count Register                                               */
360 #define DMA9_Y_MODIFY                   0xFFC00E5C      /* DMA Channel 9 Y Modify Register                                              */
361 #define DMA9_CURR_DESC_PTR              0xFFC00E60      /* DMA Channel 9 Current Descriptor Pointer Register    */
362 #define DMA9_CURR_ADDR                  0xFFC00E64      /* DMA Channel 9 Current Address Register                               */
363 #define DMA9_IRQ_STATUS                 0xFFC00E68      /* DMA Channel 9 Interrupt/Status Register                              */
364 #define DMA9_PERIPHERAL_MAP             0xFFC00E6C      /* DMA Channel 9 Peripheral Map Register                                */
365 #define DMA9_CURR_X_COUNT               0xFFC00E70      /* DMA Channel 9 Current X Count Register                               */
366 #define DMA9_CURR_Y_COUNT               0xFFC00E78      /* DMA Channel 9 Current Y Count Register                               */
367
368 #define DMA10_NEXT_DESC_PTR             0xFFC00E80      /* DMA Channel 10 Next Descriptor Pointer Register              */
369 #define DMA10_START_ADDR                0xFFC00E84      /* DMA Channel 10 Start Address Register                                */
370 #define DMA10_CONFIG                    0xFFC00E88      /* DMA Channel 10 Configuration Register                                */
371 #define DMA10_X_COUNT                   0xFFC00E90      /* DMA Channel 10 X Count Register                                              */
372 #define DMA10_X_MODIFY                  0xFFC00E94      /* DMA Channel 10 X Modify Register                                             */
373 #define DMA10_Y_COUNT                   0xFFC00E98      /* DMA Channel 10 Y Count Register                                              */
374 #define DMA10_Y_MODIFY                  0xFFC00E9C      /* DMA Channel 10 Y Modify Register                                             */
375 #define DMA10_CURR_DESC_PTR             0xFFC00EA0      /* DMA Channel 10 Current Descriptor Pointer Register   */
376 #define DMA10_CURR_ADDR                 0xFFC00EA4      /* DMA Channel 10 Current Address Register                              */
377 #define DMA10_IRQ_STATUS                0xFFC00EA8      /* DMA Channel 10 Interrupt/Status Register                             */
378 #define DMA10_PERIPHERAL_MAP    0xFFC00EAC      /* DMA Channel 10 Peripheral Map Register                               */
379 #define DMA10_CURR_X_COUNT              0xFFC00EB0      /* DMA Channel 10 Current X Count Register                              */
380 #define DMA10_CURR_Y_COUNT              0xFFC00EB8      /* DMA Channel 10 Current Y Count Register                              */
381
382 #define DMA11_NEXT_DESC_PTR             0xFFC00EC0      /* DMA Channel 11 Next Descriptor Pointer Register              */
383 #define DMA11_START_ADDR                0xFFC00EC4      /* DMA Channel 11 Start Address Register                                */
384 #define DMA11_CONFIG                    0xFFC00EC8      /* DMA Channel 11 Configuration Register                                */
385 #define DMA11_X_COUNT                   0xFFC00ED0      /* DMA Channel 11 X Count Register                                              */
386 #define DMA11_X_MODIFY                  0xFFC00ED4      /* DMA Channel 11 X Modify Register                                             */
387 #define DMA11_Y_COUNT                   0xFFC00ED8      /* DMA Channel 11 Y Count Register                                              */
388 #define DMA11_Y_MODIFY                  0xFFC00EDC      /* DMA Channel 11 Y Modify Register                                             */
389 #define DMA11_CURR_DESC_PTR             0xFFC00EE0      /* DMA Channel 11 Current Descriptor Pointer Register   */
390 #define DMA11_CURR_ADDR                 0xFFC00EE4      /* DMA Channel 11 Current Address Register                              */
391 #define DMA11_IRQ_STATUS                0xFFC00EE8      /* DMA Channel 11 Interrupt/Status Register                             */
392 #define DMA11_PERIPHERAL_MAP    0xFFC00EEC      /* DMA Channel 11 Peripheral Map Register                               */
393 #define DMA11_CURR_X_COUNT              0xFFC00EF0      /* DMA Channel 11 Current X Count Register                              */
394 #define DMA11_CURR_Y_COUNT              0xFFC00EF8      /* DMA Channel 11 Current Y Count Register                              */
395
396 #define MDMA_D0_NEXT_DESC_PTR   0xFFC00F00      /* MemDMA Stream 0 Destination Next Descriptor Pointer Register         */
397 #define MDMA_D0_START_ADDR              0xFFC00F04      /* MemDMA Stream 0 Destination Start Address Register                           */
398 #define MDMA_D0_CONFIG                  0xFFC00F08      /* MemDMA Stream 0 Destination Configuration Register                           */
399 #define MDMA_D0_X_COUNT                 0xFFC00F10      /* MemDMA Stream 0 Destination X Count Register                                         */
400 #define MDMA_D0_X_MODIFY                0xFFC00F14      /* MemDMA Stream 0 Destination X Modify Register                                        */
401 #define MDMA_D0_Y_COUNT                 0xFFC00F18      /* MemDMA Stream 0 Destination Y Count Register                                         */
402 #define MDMA_D0_Y_MODIFY                0xFFC00F1C      /* MemDMA Stream 0 Destination Y Modify Register                                        */
403 #define MDMA_D0_CURR_DESC_PTR   0xFFC00F20      /* MemDMA Stream 0 Destination Current Descriptor Pointer Register      */
404 #define MDMA_D0_CURR_ADDR               0xFFC00F24      /* MemDMA Stream 0 Destination Current Address Register                         */
405 #define MDMA_D0_IRQ_STATUS              0xFFC00F28      /* MemDMA Stream 0 Destination Interrupt/Status Register                        */
406 #define MDMA_D0_PERIPHERAL_MAP  0xFFC00F2C      /* MemDMA Stream 0 Destination Peripheral Map Register                          */
407 #define MDMA_D0_CURR_X_COUNT    0xFFC00F30      /* MemDMA Stream 0 Destination Current X Count Register                         */
408 #define MDMA_D0_CURR_Y_COUNT    0xFFC00F38      /* MemDMA Stream 0 Destination Current Y Count Register                         */
409
410 #define MDMA_S0_NEXT_DESC_PTR   0xFFC00F40      /* MemDMA Stream 0 Source Next Descriptor Pointer Register                      */
411 #define MDMA_S0_START_ADDR              0xFFC00F44      /* MemDMA Stream 0 Source Start Address Register                                        */
412 #define MDMA_S0_CONFIG                  0xFFC00F48      /* MemDMA Stream 0 Source Configuration Register                                        */
413 #define MDMA_S0_X_COUNT                 0xFFC00F50      /* MemDMA Stream 0 Source X Count Register                                                      */
414 #define MDMA_S0_X_MODIFY                0xFFC00F54      /* MemDMA Stream 0 Source X Modify Register                                                     */
415 #define MDMA_S0_Y_COUNT                 0xFFC00F58      /* MemDMA Stream 0 Source Y Count Register                                                      */
416 #define MDMA_S0_Y_MODIFY                0xFFC00F5C      /* MemDMA Stream 0 Source Y Modify Register                                                     */
417 #define MDMA_S0_CURR_DESC_PTR   0xFFC00F60      /* MemDMA Stream 0 Source Current Descriptor Pointer Register           */
418 #define MDMA_S0_CURR_ADDR               0xFFC00F64      /* MemDMA Stream 0 Source Current Address Register                                      */
419 #define MDMA_S0_IRQ_STATUS              0xFFC00F68      /* MemDMA Stream 0 Source Interrupt/Status Register                                     */
420 #define MDMA_S0_PERIPHERAL_MAP  0xFFC00F6C      /* MemDMA Stream 0 Source Peripheral Map Register                                       */
421 #define MDMA_S0_CURR_X_COUNT    0xFFC00F70      /* MemDMA Stream 0 Source Current X Count Register                                      */
422 #define MDMA_S0_CURR_Y_COUNT    0xFFC00F78      /* MemDMA Stream 0 Source Current Y Count Register                                      */
423
424 #define MDMA_D1_NEXT_DESC_PTR   0xFFC00F80      /* MemDMA Stream 1 Destination Next Descriptor Pointer Register         */
425 #define MDMA_D1_START_ADDR              0xFFC00F84      /* MemDMA Stream 1 Destination Start Address Register                           */
426 #define MDMA_D1_CONFIG                  0xFFC00F88      /* MemDMA Stream 1 Destination Configuration Register                           */
427 #define MDMA_D1_X_COUNT                 0xFFC00F90      /* MemDMA Stream 1 Destination X Count Register                                         */
428 #define MDMA_D1_X_MODIFY                0xFFC00F94      /* MemDMA Stream 1 Destination X Modify Register                                        */
429 #define MDMA_D1_Y_COUNT                 0xFFC00F98      /* MemDMA Stream 1 Destination Y Count Register                                         */
430 #define MDMA_D1_Y_MODIFY                0xFFC00F9C      /* MemDMA Stream 1 Destination Y Modify Register                                        */
431 #define MDMA_D1_CURR_DESC_PTR   0xFFC00FA0      /* MemDMA Stream 1 Destination Current Descriptor Pointer Register      */
432 #define MDMA_D1_CURR_ADDR               0xFFC00FA4      /* MemDMA Stream 1 Destination Current Address Register                         */
433 #define MDMA_D1_IRQ_STATUS              0xFFC00FA8      /* MemDMA Stream 1 Destination Interrupt/Status Register                        */
434 #define MDMA_D1_PERIPHERAL_MAP  0xFFC00FAC      /* MemDMA Stream 1 Destination Peripheral Map Register                          */
435 #define MDMA_D1_CURR_X_COUNT    0xFFC00FB0      /* MemDMA Stream 1 Destination Current X Count Register                         */
436 #define MDMA_D1_CURR_Y_COUNT    0xFFC00FB8      /* MemDMA Stream 1 Destination Current Y Count Register                         */
437
438 #define MDMA_S1_NEXT_DESC_PTR   0xFFC00FC0      /* MemDMA Stream 1 Source Next Descriptor Pointer Register                      */
439 #define MDMA_S1_START_ADDR              0xFFC00FC4      /* MemDMA Stream 1 Source Start Address Register                                        */
440 #define MDMA_S1_CONFIG                  0xFFC00FC8      /* MemDMA Stream 1 Source Configuration Register                                        */
441 #define MDMA_S1_X_COUNT                 0xFFC00FD0      /* MemDMA Stream 1 Source X Count Register                                                      */
442 #define MDMA_S1_X_MODIFY                0xFFC00FD4      /* MemDMA Stream 1 Source X Modify Register                                                     */
443 #define MDMA_S1_Y_COUNT                 0xFFC00FD8      /* MemDMA Stream 1 Source Y Count Register                                                      */
444 #define MDMA_S1_Y_MODIFY                0xFFC00FDC      /* MemDMA Stream 1 Source Y Modify Register                                                     */
445 #define MDMA_S1_CURR_DESC_PTR   0xFFC00FE0      /* MemDMA Stream 1 Source Current Descriptor Pointer Register           */
446 #define MDMA_S1_CURR_ADDR               0xFFC00FE4      /* MemDMA Stream 1 Source Current Address Register                                      */
447 #define MDMA_S1_IRQ_STATUS              0xFFC00FE8      /* MemDMA Stream 1 Source Interrupt/Status Register                                     */
448 #define MDMA_S1_PERIPHERAL_MAP  0xFFC00FEC      /* MemDMA Stream 1 Source Peripheral Map Register                                       */
449 #define MDMA_S1_CURR_X_COUNT    0xFFC00FF0      /* MemDMA Stream 1 Source Current X Count Register                                      */
450 #define MDMA_S1_CURR_Y_COUNT    0xFFC00FF8      /* MemDMA Stream 1 Source Current Y Count Register                                      */
451
452 /* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF)                              */
453 #define PPI_CONTROL                     0xFFC01000      /* PPI Control Register                 */
454 #define PPI_STATUS                      0xFFC01004      /* PPI Status Register                  */
455 #define PPI_COUNT                       0xFFC01008      /* PPI Transfer Count Register  */
456 #define PPI_DELAY                       0xFFC0100C      /* PPI Delay Count Register             */
457 #define PPI_FRAME                       0xFFC01010      /* PPI Frame Length Register    */
458
459 /* Two-Wire Interface           (0xFFC01400 - 0xFFC014FF)                                                               */
460 #define TWI0_REGBASE                    0xFFC01400
461 #define TWI_CLKDIV                      0xFFC01400      /* Serial Clock Divider Register                        */
462 #define TWI_CONTROL                     0xFFC01404      /* TWI Control Register                                         */
463 #define TWI_SLAVE_CTL           0xFFC01408      /* Slave Mode Control Register                          */
464 #define TWI_SLAVE_STAT          0xFFC0140C      /* Slave Mode Status Register                           */
465 #define TWI_SLAVE_ADDR          0xFFC01410      /* Slave Mode Address Register                          */
466 #define TWI_MASTER_CTL          0xFFC01414      /* Master Mode Control Register                         */
467 #define TWI_MASTER_STAT         0xFFC01418      /* Master Mode Status Register                          */
468 #define TWI_MASTER_ADDR         0xFFC0141C      /* Master Mode Address Register                         */
469 #define TWI_INT_STAT            0xFFC01420      /* TWI Interrupt Status Register                        */
470 #define TWI_INT_MASK            0xFFC01424      /* TWI Master Interrupt Mask Register           */
471 #define TWI_FIFO_CTL            0xFFC01428      /* FIFO Control Register                                        */
472 #define TWI_FIFO_STAT           0xFFC0142C      /* FIFO Status Register                                         */
473 #define TWI_XMT_DATA8           0xFFC01480      /* FIFO Transmit Data Single Byte Register      */
474 #define TWI_XMT_DATA16          0xFFC01484      /* FIFO Transmit Data Double Byte Register      */
475 #define TWI_RCV_DATA8           0xFFC01488      /* FIFO Receive Data Single Byte Register       */
476 #define TWI_RCV_DATA16          0xFFC0148C      /* FIFO Receive Data Double Byte Register       */
477
478 /* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF)                                                                                         */
479 #define PORTGIO                                 0xFFC01500      /* Port G I/O Pin State Specify Register                                */
480 #define PORTGIO_CLEAR                   0xFFC01504      /* Port G I/O Peripheral Interrupt Clear Register               */
481 #define PORTGIO_SET                             0xFFC01508      /* Port G I/O Peripheral Interrupt Set Register                 */
482 #define PORTGIO_TOGGLE                  0xFFC0150C      /* Port G I/O Pin State Toggle Register                                 */
483 #define PORTGIO_MASKA                   0xFFC01510      /* Port G I/O Mask State Specify Interrupt A Register   */
484 #define PORTGIO_MASKA_CLEAR             0xFFC01514      /* Port G I/O Mask Disable Interrupt A Register                 */
485 #define PORTGIO_MASKA_SET               0xFFC01518      /* Port G I/O Mask Enable Interrupt A Register                  */
486 #define PORTGIO_MASKA_TOGGLE    0xFFC0151C      /* Port G I/O Mask Toggle Enable Interrupt A Register   */
487 #define PORTGIO_MASKB                   0xFFC01520      /* Port G I/O Mask State Specify Interrupt B Register   */
488 #define PORTGIO_MASKB_CLEAR             0xFFC01524      /* Port G I/O Mask Disable Interrupt B Register                 */
489 #define PORTGIO_MASKB_SET               0xFFC01528      /* Port G I/O Mask Enable Interrupt B Register                  */
490 #define PORTGIO_MASKB_TOGGLE    0xFFC0152C      /* Port G I/O Mask Toggle Enable Interrupt B Register   */
491 #define PORTGIO_DIR                             0xFFC01530      /* Port G I/O Direction Register                                                */
492 #define PORTGIO_POLAR                   0xFFC01534      /* Port G I/O Source Polarity Register                                  */
493 #define PORTGIO_EDGE                    0xFFC01538      /* Port G I/O Source Sensitivity Register                               */
494 #define PORTGIO_BOTH                    0xFFC0153C      /* Port G I/O Set on BOTH Edges Register                                */
495 #define PORTGIO_INEN                    0xFFC01540      /* Port G I/O Input Enable Register                                             */
496
497 /* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF)                                                                                         */
498 #define PORTHIO                                 0xFFC01700      /* Port H I/O Pin State Specify Register                                */
499 #define PORTHIO_CLEAR                   0xFFC01704      /* Port H I/O Peripheral Interrupt Clear Register               */
500 #define PORTHIO_SET                             0xFFC01708      /* Port H I/O Peripheral Interrupt Set Register                 */
501 #define PORTHIO_TOGGLE                  0xFFC0170C      /* Port H I/O Pin State Toggle Register                                 */
502 #define PORTHIO_MASKA                   0xFFC01710      /* Port H I/O Mask State Specify Interrupt A Register   */
503 #define PORTHIO_MASKA_CLEAR             0xFFC01714      /* Port H I/O Mask Disable Interrupt A Register                 */
504 #define PORTHIO_MASKA_SET               0xFFC01718      /* Port H I/O Mask Enable Interrupt A Register                  */
505 #define PORTHIO_MASKA_TOGGLE    0xFFC0171C      /* Port H I/O Mask Toggle Enable Interrupt A Register   */
506 #define PORTHIO_MASKB                   0xFFC01720      /* Port H I/O Mask State Specify Interrupt B Register   */
507 #define PORTHIO_MASKB_CLEAR             0xFFC01724      /* Port H I/O Mask Disable Interrupt B Register                 */
508 #define PORTHIO_MASKB_SET               0xFFC01728      /* Port H I/O Mask Enable Interrupt B Register                  */
509 #define PORTHIO_MASKB_TOGGLE    0xFFC0172C      /* Port H I/O Mask Toggle Enable Interrupt B Register   */
510 #define PORTHIO_DIR                             0xFFC01730      /* Port H I/O Direction Register                                                */
511 #define PORTHIO_POLAR                   0xFFC01734      /* Port H I/O Source Polarity Register                                  */
512 #define PORTHIO_EDGE                    0xFFC01738      /* Port H I/O Source Sensitivity Register                               */
513 #define PORTHIO_BOTH                    0xFFC0173C      /* Port H I/O Set on BOTH Edges Register                                */
514 #define PORTHIO_INEN                    0xFFC01740      /* Port H I/O Input Enable Register                                             */
515
516 /* UART1 Controller             (0xFFC02000 - 0xFFC020FF)                                                               */
517 #define UART1_THR                       0xFFC02000      /* Transmit Holding register                    */
518 #define UART1_RBR                       0xFFC02000      /* Receive Buffer register                              */
519 #define UART1_DLL                       0xFFC02000      /* Divisor Latch (Low-Byte)                             */
520 #define UART1_IER                       0xFFC02004      /* Interrupt Enable Register                    */
521 #define UART1_DLH                       0xFFC02004      /* Divisor Latch (High-Byte)                    */
522 #define UART1_IIR                       0xFFC02008      /* Interrupt Identification Register    */
523 #define UART1_LCR                       0xFFC0200C      /* Line Control Register                                */
524 #define UART1_MCR                       0xFFC02010      /* Modem Control Register                               */
525 #define UART1_LSR                       0xFFC02014      /* Line Status Register                                 */
526 #define UART1_MSR                       0xFFC02018      /* Modem Status Register                                */
527 #define UART1_SCR                       0xFFC0201C      /* SCR Scratch Register                                 */
528 #define UART1_GCTL                      0xFFC02024      /* Global Control Register                              */
529
530 /* CAN Controller               (0xFFC02A00 - 0xFFC02FFF)                                                                               */
531 /* For Mailboxes 0-15                                                                                                                                   */
532 #define CAN_MC1                         0xFFC02A00      /* Mailbox config reg 1                                                 */
533 #define CAN_MD1                         0xFFC02A04      /* Mailbox direction reg 1                                              */
534 #define CAN_TRS1                        0xFFC02A08      /* Transmit Request Set reg 1                                   */
535 #define CAN_TRR1                        0xFFC02A0C      /* Transmit Request Reset reg 1                                 */
536 #define CAN_TA1                         0xFFC02A10      /* Transmit Acknowledge reg 1                                   */
537 #define CAN_AA1                         0xFFC02A14      /* Transmit Abort Acknowledge reg 1                             */
538 #define CAN_RMP1                        0xFFC02A18      /* Receive Message Pending reg 1                                */
539 #define CAN_RML1                        0xFFC02A1C      /* Receive Message Lost reg 1                                   */
540 #define CAN_MBTIF1                      0xFFC02A20      /* Mailbox Transmit Interrupt Flag reg 1                */
541 #define CAN_MBRIF1                      0xFFC02A24      /* Mailbox Receive  Interrupt Flag reg 1                */
542 #define CAN_MBIM1                       0xFFC02A28      /* Mailbox Interrupt Mask reg 1                                 */
543 #define CAN_RFH1                        0xFFC02A2C      /* Remote Frame Handling reg 1                                  */
544 #define CAN_OPSS1                       0xFFC02A30      /* Overwrite Protection Single Shot Xmit reg 1  */
545
546 /* For Mailboxes 16-31                                                                                                                                  */
547 #define CAN_MC2                         0xFFC02A40      /* Mailbox config reg 2                                                 */
548 #define CAN_MD2                         0xFFC02A44      /* Mailbox direction reg 2                                              */
549 #define CAN_TRS2                        0xFFC02A48      /* Transmit Request Set reg 2                                   */
550 #define CAN_TRR2                        0xFFC02A4C      /* Transmit Request Reset reg 2                                 */
551 #define CAN_TA2                         0xFFC02A50      /* Transmit Acknowledge reg 2                                   */
552 #define CAN_AA2                         0xFFC02A54      /* Transmit Abort Acknowledge reg 2                             */
553 #define CAN_RMP2                        0xFFC02A58      /* Receive Message Pending reg 2                                */
554 #define CAN_RML2                        0xFFC02A5C      /* Receive Message Lost reg 2                                   */
555 #define CAN_MBTIF2                      0xFFC02A60      /* Mailbox Transmit Interrupt Flag reg 2                */
556 #define CAN_MBRIF2                      0xFFC02A64      /* Mailbox Receive  Interrupt Flag reg 2                */
557 #define CAN_MBIM2                       0xFFC02A68      /* Mailbox Interrupt Mask reg 2                                 */
558 #define CAN_RFH2                        0xFFC02A6C      /* Remote Frame Handling reg 2                                  */
559 #define CAN_OPSS2                       0xFFC02A70      /* Overwrite Protection Single Shot Xmit reg 2  */
560
561 /* CAN Configuration, Control, and Status Registers                                                                             */
562 #define CAN_CLOCK                       0xFFC02A80      /* Bit Timing Configuration register 0                  */
563 #define CAN_TIMING                      0xFFC02A84      /* Bit Timing Configuration register 1                  */
564 #define CAN_DEBUG                       0xFFC02A88      /* Debug Register                                                               */
565 #define CAN_STATUS                      0xFFC02A8C      /* Global Status Register                                               */
566 #define CAN_CEC                         0xFFC02A90      /* Error Counter Register                                               */
567 #define CAN_GIS                         0xFFC02A94      /* Global Interrupt Status Register                             */
568 #define CAN_GIM                         0xFFC02A98      /* Global Interrupt Mask Register                               */
569 #define CAN_GIF                         0xFFC02A9C      /* Global Interrupt Flag Register                               */
570 #define CAN_CONTROL                     0xFFC02AA0      /* Master Control Register                                              */
571 #define CAN_INTR                        0xFFC02AA4      /* Interrupt Pending Register                                   */
572
573 #define CAN_MBTD                        0xFFC02AAC      /* Mailbox Temporary Disable Feature                    */
574 #define CAN_EWR                         0xFFC02AB0      /* Programmable Warning Level                                   */
575 #define CAN_ESR                         0xFFC02AB4      /* Error Status Register                                                */
576 #define CAN_UCREG                       0xFFC02AC0      /* Universal Counter Register/Capture Register  */
577 #define CAN_UCCNT                       0xFFC02AC4      /* Universal Counter                                                    */
578 #define CAN_UCRC                        0xFFC02AC8      /* Universal Counter Force Reload Register              */
579 #define CAN_UCCNF                       0xFFC02ACC      /* Universal Counter Configuration Register             */
580
581 /* Mailbox Acceptance Masks                                                                                             */
582 #define CAN_AM00L                       0xFFC02B00      /* Mailbox 0 Low Acceptance Mask        */
583 #define CAN_AM00H                       0xFFC02B04      /* Mailbox 0 High Acceptance Mask       */
584 #define CAN_AM01L                       0xFFC02B08      /* Mailbox 1 Low Acceptance Mask        */
585 #define CAN_AM01H                       0xFFC02B0C      /* Mailbox 1 High Acceptance Mask       */
586 #define CAN_AM02L                       0xFFC02B10      /* Mailbox 2 Low Acceptance Mask        */
587 #define CAN_AM02H                       0xFFC02B14      /* Mailbox 2 High Acceptance Mask       */
588 #define CAN_AM03L                       0xFFC02B18      /* Mailbox 3 Low Acceptance Mask        */
589 #define CAN_AM03H                       0xFFC02B1C      /* Mailbox 3 High Acceptance Mask       */
590 #define CAN_AM04L                       0xFFC02B20      /* Mailbox 4 Low Acceptance Mask        */
591 #define CAN_AM04H                       0xFFC02B24      /* Mailbox 4 High Acceptance Mask       */
592 #define CAN_AM05L                       0xFFC02B28      /* Mailbox 5 Low Acceptance Mask        */
593 #define CAN_AM05H                       0xFFC02B2C      /* Mailbox 5 High Acceptance Mask       */
594 #define CAN_AM06L                       0xFFC02B30      /* Mailbox 6 Low Acceptance Mask        */
595 #define CAN_AM06H                       0xFFC02B34      /* Mailbox 6 High Acceptance Mask       */
596 #define CAN_AM07L                       0xFFC02B38      /* Mailbox 7 Low Acceptance Mask        */
597 #define CAN_AM07H                       0xFFC02B3C      /* Mailbox 7 High Acceptance Mask       */
598 #define CAN_AM08L                       0xFFC02B40      /* Mailbox 8 Low Acceptance Mask        */
599 #define CAN_AM08H                       0xFFC02B44      /* Mailbox 8 High Acceptance Mask       */
600 #define CAN_AM09L                       0xFFC02B48      /* Mailbox 9 Low Acceptance Mask        */
601 #define CAN_AM09H                       0xFFC02B4C      /* Mailbox 9 High Acceptance Mask       */
602 #define CAN_AM10L                       0xFFC02B50      /* Mailbox 10 Low Acceptance Mask       */
603 #define CAN_AM10H                       0xFFC02B54      /* Mailbox 10 High Acceptance Mask      */
604 #define CAN_AM11L                       0xFFC02B58      /* Mailbox 11 Low Acceptance Mask       */
605 #define CAN_AM11H                       0xFFC02B5C      /* Mailbox 11 High Acceptance Mask      */
606 #define CAN_AM12L                       0xFFC02B60      /* Mailbox 12 Low Acceptance Mask       */
607 #define CAN_AM12H                       0xFFC02B64      /* Mailbox 12 High Acceptance Mask      */
608 #define CAN_AM13L                       0xFFC02B68      /* Mailbox 13 Low Acceptance Mask       */
609 #define CAN_AM13H                       0xFFC02B6C      /* Mailbox 13 High Acceptance Mask      */
610 #define CAN_AM14L                       0xFFC02B70      /* Mailbox 14 Low Acceptance Mask       */
611 #define CAN_AM14H                       0xFFC02B74      /* Mailbox 14 High Acceptance Mask      */
612 #define CAN_AM15L                       0xFFC02B78      /* Mailbox 15 Low Acceptance Mask       */
613 #define CAN_AM15H                       0xFFC02B7C      /* Mailbox 15 High Acceptance Mask      */
614
615 #define CAN_AM16L                       0xFFC02B80      /* Mailbox 16 Low Acceptance Mask       */
616 #define CAN_AM16H                       0xFFC02B84      /* Mailbox 16 High Acceptance Mask      */
617 #define CAN_AM17L                       0xFFC02B88      /* Mailbox 17 Low Acceptance Mask       */
618 #define CAN_AM17H                       0xFFC02B8C      /* Mailbox 17 High Acceptance Mask      */
619 #define CAN_AM18L                       0xFFC02B90      /* Mailbox 18 Low Acceptance Mask       */
620 #define CAN_AM18H                       0xFFC02B94      /* Mailbox 18 High Acceptance Mask      */
621 #define CAN_AM19L                       0xFFC02B98      /* Mailbox 19 Low Acceptance Mask       */
622 #define CAN_AM19H                       0xFFC02B9C      /* Mailbox 19 High Acceptance Mask      */
623 #define CAN_AM20L                       0xFFC02BA0      /* Mailbox 20 Low Acceptance Mask       */
624 #define CAN_AM20H                       0xFFC02BA4      /* Mailbox 20 High Acceptance Mask      */
625 #define CAN_AM21L                       0xFFC02BA8      /* Mailbox 21 Low Acceptance Mask       */
626 #define CAN_AM21H                       0xFFC02BAC      /* Mailbox 21 High Acceptance Mask      */
627 #define CAN_AM22L                       0xFFC02BB0      /* Mailbox 22 Low Acceptance Mask       */
628 #define CAN_AM22H                       0xFFC02BB4      /* Mailbox 22 High Acceptance Mask      */
629 #define CAN_AM23L                       0xFFC02BB8      /* Mailbox 23 Low Acceptance Mask       */
630 #define CAN_AM23H                       0xFFC02BBC      /* Mailbox 23 High Acceptance Mask      */
631 #define CAN_AM24L                       0xFFC02BC0      /* Mailbox 24 Low Acceptance Mask       */
632 #define CAN_AM24H                       0xFFC02BC4      /* Mailbox 24 High Acceptance Mask      */
633 #define CAN_AM25L                       0xFFC02BC8      /* Mailbox 25 Low Acceptance Mask       */
634 #define CAN_AM25H                       0xFFC02BCC      /* Mailbox 25 High Acceptance Mask      */
635 #define CAN_AM26L                       0xFFC02BD0      /* Mailbox 26 Low Acceptance Mask       */
636 #define CAN_AM26H                       0xFFC02BD4      /* Mailbox 26 High Acceptance Mask      */
637 #define CAN_AM27L                       0xFFC02BD8      /* Mailbox 27 Low Acceptance Mask       */
638 #define CAN_AM27H                       0xFFC02BDC      /* Mailbox 27 High Acceptance Mask      */
639 #define CAN_AM28L                       0xFFC02BE0      /* Mailbox 28 Low Acceptance Mask       */
640 #define CAN_AM28H                       0xFFC02BE4      /* Mailbox 28 High Acceptance Mask      */
641 #define CAN_AM29L                       0xFFC02BE8      /* Mailbox 29 Low Acceptance Mask       */
642 #define CAN_AM29H                       0xFFC02BEC      /* Mailbox 29 High Acceptance Mask      */
643 #define CAN_AM30L                       0xFFC02BF0      /* Mailbox 30 Low Acceptance Mask       */
644 #define CAN_AM30H                       0xFFC02BF4      /* Mailbox 30 High Acceptance Mask      */
645 #define CAN_AM31L                       0xFFC02BF8      /* Mailbox 31 Low Acceptance Mask       */
646 #define CAN_AM31H                       0xFFC02BFC      /* Mailbox 31 High Acceptance Mask      */
647
648 /* CAN Acceptance Mask Macros                           */
649 #define CAN_AM_L(x)             (CAN_AM00L+((x)*0x8))
650 #define CAN_AM_H(x)             (CAN_AM00H+((x)*0x8))
651
652 /* Mailbox Registers                                                                                                                            */
653 #define CAN_MB00_DATA0          0xFFC02C00      /* Mailbox 0 Data Word 0 [15:0] Register        */
654 #define CAN_MB00_DATA1          0xFFC02C04      /* Mailbox 0 Data Word 1 [31:16] Register       */
655 #define CAN_MB00_DATA2          0xFFC02C08      /* Mailbox 0 Data Word 2 [47:32] Register       */
656 #define CAN_MB00_DATA3          0xFFC02C0C      /* Mailbox 0 Data Word 3 [63:48] Register       */
657 #define CAN_MB00_LENGTH         0xFFC02C10      /* Mailbox 0 Data Length Code Register          */
658 #define CAN_MB00_TIMESTAMP      0xFFC02C14      /* Mailbox 0 Time Stamp Value Register          */
659 #define CAN_MB00_ID0            0xFFC02C18      /* Mailbox 0 Identifier Low Register            */
660 #define CAN_MB00_ID1            0xFFC02C1C      /* Mailbox 0 Identifier High Register           */
661
662 #define CAN_MB01_DATA0          0xFFC02C20      /* Mailbox 1 Data Word 0 [15:0] Register        */
663 #define CAN_MB01_DATA1          0xFFC02C24      /* Mailbox 1 Data Word 1 [31:16] Register       */
664 #define CAN_MB01_DATA2          0xFFC02C28      /* Mailbox 1 Data Word 2 [47:32] Register       */
665 #define CAN_MB01_DATA3          0xFFC02C2C      /* Mailbox 1 Data Word 3 [63:48] Register       */
666 #define CAN_MB01_LENGTH         0xFFC02C30      /* Mailbox 1 Data Length Code Register          */
667 #define CAN_MB01_TIMESTAMP      0xFFC02C34      /* Mailbox 1 Time Stamp Value Register          */
668 #define CAN_MB01_ID0            0xFFC02C38      /* Mailbox 1 Identifier Low Register            */
669 #define CAN_MB01_ID1            0xFFC02C3C      /* Mailbox 1 Identifier High Register           */
670
671 #define CAN_MB02_DATA0          0xFFC02C40      /* Mailbox 2 Data Word 0 [15:0] Register        */
672 #define CAN_MB02_DATA1          0xFFC02C44      /* Mailbox 2 Data Word 1 [31:16] Register       */
673 #define CAN_MB02_DATA2          0xFFC02C48      /* Mailbox 2 Data Word 2 [47:32] Register       */
674 #define CAN_MB02_DATA3          0xFFC02C4C      /* Mailbox 2 Data Word 3 [63:48] Register       */
675 #define CAN_MB02_LENGTH         0xFFC02C50      /* Mailbox 2 Data Length Code Register          */
676 #define CAN_MB02_TIMESTAMP      0xFFC02C54      /* Mailbox 2 Time Stamp Value Register          */
677 #define CAN_MB02_ID0            0xFFC02C58      /* Mailbox 2 Identifier Low Register            */
678 #define CAN_MB02_ID1            0xFFC02C5C      /* Mailbox 2 Identifier High Register           */
679
680 #define CAN_MB03_DATA0          0xFFC02C60      /* Mailbox 3 Data Word 0 [15:0] Register        */
681 #define CAN_MB03_DATA1          0xFFC02C64      /* Mailbox 3 Data Word 1 [31:16] Register       */
682 #define CAN_MB03_DATA2          0xFFC02C68      /* Mailbox 3 Data Word 2 [47:32] Register       */
683 #define CAN_MB03_DATA3          0xFFC02C6C      /* Mailbox 3 Data Word 3 [63:48] Register       */
684 #define CAN_MB03_LENGTH         0xFFC02C70      /* Mailbox 3 Data Length Code Register          */
685 #define CAN_MB03_TIMESTAMP      0xFFC02C74      /* Mailbox 3 Time Stamp Value Register          */
686 #define CAN_MB03_ID0            0xFFC02C78      /* Mailbox 3 Identifier Low Register            */
687 #define CAN_MB03_ID1            0xFFC02C7C      /* Mailbox 3 Identifier High Register           */
688
689 #define CAN_MB04_DATA0          0xFFC02C80      /* Mailbox 4 Data Word 0 [15:0] Register        */
690 #define CAN_MB04_DATA1          0xFFC02C84      /* Mailbox 4 Data Word 1 [31:16] Register       */
691 #define CAN_MB04_DATA2          0xFFC02C88      /* Mailbox 4 Data Word 2 [47:32] Register       */
692 #define CAN_MB04_DATA3          0xFFC02C8C      /* Mailbox 4 Data Word 3 [63:48] Register       */
693 #define CAN_MB04_LENGTH         0xFFC02C90      /* Mailbox 4 Data Length Code Register          */
694 #define CAN_MB04_TIMESTAMP      0xFFC02C94      /* Mailbox 4 Time Stamp Value Register          */
695 #define CAN_MB04_ID0            0xFFC02C98      /* Mailbox 4 Identifier Low Register            */
696 #define CAN_MB04_ID1            0xFFC02C9C      /* Mailbox 4 Identifier High Register           */
697
698 #define CAN_MB05_DATA0          0xFFC02CA0      /* Mailbox 5 Data Word 0 [15:0] Register        */
699 #define CAN_MB05_DATA1          0xFFC02CA4      /* Mailbox 5 Data Word 1 [31:16] Register       */
700 #define CAN_MB05_DATA2          0xFFC02CA8      /* Mailbox 5 Data Word 2 [47:32] Register       */
701 #define CAN_MB05_DATA3          0xFFC02CAC      /* Mailbox 5 Data Word 3 [63:48] Register       */
702 #define CAN_MB05_LENGTH         0xFFC02CB0      /* Mailbox 5 Data Length Code Register          */
703 #define CAN_MB05_TIMESTAMP      0xFFC02CB4      /* Mailbox 5 Time Stamp Value Register          */
704 #define CAN_MB05_ID0            0xFFC02CB8      /* Mailbox 5 Identifier Low Register            */
705 #define CAN_MB05_ID1            0xFFC02CBC      /* Mailbox 5 Identifier High Register           */
706
707 #define CAN_MB06_DATA0          0xFFC02CC0      /* Mailbox 6 Data Word 0 [15:0] Register        */
708 #define CAN_MB06_DATA1          0xFFC02CC4      /* Mailbox 6 Data Word 1 [31:16] Register       */
709 #define CAN_MB06_DATA2          0xFFC02CC8      /* Mailbox 6 Data Word 2 [47:32] Register       */
710 #define CAN_MB06_DATA3          0xFFC02CCC      /* Mailbox 6 Data Word 3 [63:48] Register       */
711 #define CAN_MB06_LENGTH         0xFFC02CD0      /* Mailbox 6 Data Length Code Register          */
712 #define CAN_MB06_TIMESTAMP      0xFFC02CD4      /* Mailbox 6 Time Stamp Value Register          */
713 #define CAN_MB06_ID0            0xFFC02CD8      /* Mailbox 6 Identifier Low Register            */
714 #define CAN_MB06_ID1            0xFFC02CDC      /* Mailbox 6 Identifier High Register           */
715
716 #define CAN_MB07_DATA0          0xFFC02CE0      /* Mailbox 7 Data Word 0 [15:0] Register        */
717 #define CAN_MB07_DATA1          0xFFC02CE4      /* Mailbox 7 Data Word 1 [31:16] Register       */
718 #define CAN_MB07_DATA2          0xFFC02CE8      /* Mailbox 7 Data Word 2 [47:32] Register       */
719 #define CAN_MB07_DATA3          0xFFC02CEC      /* Mailbox 7 Data Word 3 [63:48] Register       */
720 #define CAN_MB07_LENGTH         0xFFC02CF0      /* Mailbox 7 Data Length Code Register          */
721 #define CAN_MB07_TIMESTAMP      0xFFC02CF4      /* Mailbox 7 Time Stamp Value Register          */
722 #define CAN_MB07_ID0            0xFFC02CF8      /* Mailbox 7 Identifier Low Register            */
723 #define CAN_MB07_ID1            0xFFC02CFC      /* Mailbox 7 Identifier High Register           */
724
725 #define CAN_MB08_DATA0          0xFFC02D00      /* Mailbox 8 Data Word 0 [15:0] Register        */
726 #define CAN_MB08_DATA1          0xFFC02D04      /* Mailbox 8 Data Word 1 [31:16] Register       */
727 #define CAN_MB08_DATA2          0xFFC02D08      /* Mailbox 8 Data Word 2 [47:32] Register       */
728 #define CAN_MB08_DATA3          0xFFC02D0C      /* Mailbox 8 Data Word 3 [63:48] Register       */
729 #define CAN_MB08_LENGTH         0xFFC02D10      /* Mailbox 8 Data Length Code Register          */
730 #define CAN_MB08_TIMESTAMP      0xFFC02D14      /* Mailbox 8 Time Stamp Value Register          */
731 #define CAN_MB08_ID0            0xFFC02D18      /* Mailbox 8 Identifier Low Register            */
732 #define CAN_MB08_ID1            0xFFC02D1C      /* Mailbox 8 Identifier High Register           */
733
734 #define CAN_MB09_DATA0          0xFFC02D20      /* Mailbox 9 Data Word 0 [15:0] Register        */
735 #define CAN_MB09_DATA1          0xFFC02D24      /* Mailbox 9 Data Word 1 [31:16] Register       */
736 #define CAN_MB09_DATA2          0xFFC02D28      /* Mailbox 9 Data Word 2 [47:32] Register       */
737 #define CAN_MB09_DATA3          0xFFC02D2C      /* Mailbox 9 Data Word 3 [63:48] Register       */
738 #define CAN_MB09_LENGTH         0xFFC02D30      /* Mailbox 9 Data Length Code Register          */
739 #define CAN_MB09_TIMESTAMP      0xFFC02D34      /* Mailbox 9 Time Stamp Value Register          */
740 #define CAN_MB09_ID0            0xFFC02D38      /* Mailbox 9 Identifier Low Register            */
741 #define CAN_MB09_ID1            0xFFC02D3C      /* Mailbox 9 Identifier High Register           */
742
743 #define CAN_MB10_DATA0          0xFFC02D40      /* Mailbox 10 Data Word 0 [15:0] Register       */
744 #define CAN_MB10_DATA1          0xFFC02D44      /* Mailbox 10 Data Word 1 [31:16] Register      */
745 #define CAN_MB10_DATA2          0xFFC02D48      /* Mailbox 10 Data Word 2 [47:32] Register      */
746 #define CAN_MB10_DATA3          0xFFC02D4C      /* Mailbox 10 Data Word 3 [63:48] Register      */
747 #define CAN_MB10_LENGTH         0xFFC02D50      /* Mailbox 10 Data Length Code Register         */
748 #define CAN_MB10_TIMESTAMP      0xFFC02D54      /* Mailbox 10 Time Stamp Value Register         */
749 #define CAN_MB10_ID0            0xFFC02D58      /* Mailbox 10 Identifier Low Register           */
750 #define CAN_MB10_ID1            0xFFC02D5C      /* Mailbox 10 Identifier High Register          */
751
752 #define CAN_MB11_DATA0          0xFFC02D60      /* Mailbox 11 Data Word 0 [15:0] Register       */
753 #define CAN_MB11_DATA1          0xFFC02D64      /* Mailbox 11 Data Word 1 [31:16] Register      */
754 #define CAN_MB11_DATA2          0xFFC02D68      /* Mailbox 11 Data Word 2 [47:32] Register      */
755 #define CAN_MB11_DATA3          0xFFC02D6C      /* Mailbox 11 Data Word 3 [63:48] Register      */
756 #define CAN_MB11_LENGTH         0xFFC02D70      /* Mailbox 11 Data Length Code Register         */
757 #define CAN_MB11_TIMESTAMP      0xFFC02D74      /* Mailbox 11 Time Stamp Value Register         */
758 #define CAN_MB11_ID0            0xFFC02D78      /* Mailbox 11 Identifier Low Register           */
759 #define CAN_MB11_ID1            0xFFC02D7C      /* Mailbox 11 Identifier High Register          */
760
761 #define CAN_MB12_DATA0          0xFFC02D80      /* Mailbox 12 Data Word 0 [15:0] Register       */
762 #define CAN_MB12_DATA1          0xFFC02D84      /* Mailbox 12 Data Word 1 [31:16] Register      */
763 #define CAN_MB12_DATA2          0xFFC02D88      /* Mailbox 12 Data Word 2 [47:32] Register      */
764 #define CAN_MB12_DATA3          0xFFC02D8C      /* Mailbox 12 Data Word 3 [63:48] Register      */
765 #define CAN_MB12_LENGTH         0xFFC02D90      /* Mailbox 12 Data Length Code Register         */
766 #define CAN_MB12_TIMESTAMP      0xFFC02D94      /* Mailbox 12 Time Stamp Value Register         */
767 #define CAN_MB12_ID0            0xFFC02D98      /* Mailbox 12 Identifier Low Register           */
768 #define CAN_MB12_ID1            0xFFC02D9C      /* Mailbox 12 Identifier High Register          */
769
770 #define CAN_MB13_DATA0          0xFFC02DA0      /* Mailbox 13 Data Word 0 [15:0] Register       */
771 #define CAN_MB13_DATA1          0xFFC02DA4      /* Mailbox 13 Data Word 1 [31:16] Register      */
772 #define CAN_MB13_DATA2          0xFFC02DA8      /* Mailbox 13 Data Word 2 [47:32] Register      */
773 #define CAN_MB13_DATA3          0xFFC02DAC      /* Mailbox 13 Data Word 3 [63:48] Register      */
774 #define CAN_MB13_LENGTH         0xFFC02DB0      /* Mailbox 13 Data Length Code Register         */
775 #define CAN_MB13_TIMESTAMP      0xFFC02DB4      /* Mailbox 13 Time Stamp Value Register         */
776 #define CAN_MB13_ID0            0xFFC02DB8      /* Mailbox 13 Identifier Low Register           */
777 #define CAN_MB13_ID1            0xFFC02DBC      /* Mailbox 13 Identifier High Register          */
778
779 #define CAN_MB14_DATA0          0xFFC02DC0      /* Mailbox 14 Data Word 0 [15:0] Register       */
780 #define CAN_MB14_DATA1          0xFFC02DC4      /* Mailbox 14 Data Word 1 [31:16] Register      */
781 #define CAN_MB14_DATA2          0xFFC02DC8      /* Mailbox 14 Data Word 2 [47:32] Register      */
782 #define CAN_MB14_DATA3          0xFFC02DCC      /* Mailbox 14 Data Word 3 [63:48] Register      */
783 #define CAN_MB14_LENGTH         0xFFC02DD0      /* Mailbox 14 Data Length Code Register         */
784 #define CAN_MB14_TIMESTAMP      0xFFC02DD4      /* Mailbox 14 Time Stamp Value Register         */
785 #define CAN_MB14_ID0            0xFFC02DD8      /* Mailbox 14 Identifier Low Register           */
786 #define CAN_MB14_ID1            0xFFC02DDC      /* Mailbox 14 Identifier High Register          */
787
788 #define CAN_MB15_DATA0          0xFFC02DE0      /* Mailbox 15 Data Word 0 [15:0] Register       */
789 #define CAN_MB15_DATA1          0xFFC02DE4      /* Mailbox 15 Data Word 1 [31:16] Register      */
790 #define CAN_MB15_DATA2          0xFFC02DE8      /* Mailbox 15 Data Word 2 [47:32] Register      */
791 #define CAN_MB15_DATA3          0xFFC02DEC      /* Mailbox 15 Data Word 3 [63:48] Register      */
792 #define CAN_MB15_LENGTH         0xFFC02DF0      /* Mailbox 15 Data Length Code Register         */
793 #define CAN_MB15_TIMESTAMP      0xFFC02DF4      /* Mailbox 15 Time Stamp Value Register         */
794 #define CAN_MB15_ID0            0xFFC02DF8      /* Mailbox 15 Identifier Low Register           */
795 #define CAN_MB15_ID1            0xFFC02DFC      /* Mailbox 15 Identifier High Register          */
796
797 #define CAN_MB16_DATA0          0xFFC02E00      /* Mailbox 16 Data Word 0 [15:0] Register       */
798 #define CAN_MB16_DATA1          0xFFC02E04      /* Mailbox 16 Data Word 1 [31:16] Register      */
799 #define CAN_MB16_DATA2          0xFFC02E08      /* Mailbox 16 Data Word 2 [47:32] Register      */
800 #define CAN_MB16_DATA3          0xFFC02E0C      /* Mailbox 16 Data Word 3 [63:48] Register      */
801 #define CAN_MB16_LENGTH         0xFFC02E10      /* Mailbox 16 Data Length Code Register         */
802 #define CAN_MB16_TIMESTAMP      0xFFC02E14      /* Mailbox 16 Time Stamp Value Register         */
803 #define CAN_MB16_ID0            0xFFC02E18      /* Mailbox 16 Identifier Low Register           */
804 #define CAN_MB16_ID1            0xFFC02E1C      /* Mailbox 16 Identifier High Register          */
805
806 #define CAN_MB17_DATA0          0xFFC02E20      /* Mailbox 17 Data Word 0 [15:0] Register       */
807 #define CAN_MB17_DATA1          0xFFC02E24      /* Mailbox 17 Data Word 1 [31:16] Register      */
808 #define CAN_MB17_DATA2          0xFFC02E28      /* Mailbox 17 Data Word 2 [47:32] Register      */
809 #define CAN_MB17_DATA3          0xFFC02E2C      /* Mailbox 17 Data Word 3 [63:48] Register      */
810 #define CAN_MB17_LENGTH         0xFFC02E30      /* Mailbox 17 Data Length Code Register         */
811 #define CAN_MB17_TIMESTAMP      0xFFC02E34      /* Mailbox 17 Time Stamp Value Register         */
812 #define CAN_MB17_ID0            0xFFC02E38      /* Mailbox 17 Identifier Low Register           */
813 #define CAN_MB17_ID1            0xFFC02E3C      /* Mailbox 17 Identifier High Register          */
814
815 #define CAN_MB18_DATA0          0xFFC02E40      /* Mailbox 18 Data Word 0 [15:0] Register       */
816 #define CAN_MB18_DATA1          0xFFC02E44      /* Mailbox 18 Data Word 1 [31:16] Register      */
817 #define CAN_MB18_DATA2          0xFFC02E48      /* Mailbox 18 Data Word 2 [47:32] Register      */
818 #define CAN_MB18_DATA3          0xFFC02E4C      /* Mailbox 18 Data Word 3 [63:48] Register      */
819 #define CAN_MB18_LENGTH         0xFFC02E50      /* Mailbox 18 Data Length Code Register         */
820 #define CAN_MB18_TIMESTAMP      0xFFC02E54      /* Mailbox 18 Time Stamp Value Register         */
821 #define CAN_MB18_ID0            0xFFC02E58      /* Mailbox 18 Identifier Low Register           */
822 #define CAN_MB18_ID1            0xFFC02E5C      /* Mailbox 18 Identifier High Register          */
823
824 #define CAN_MB19_DATA0          0xFFC02E60      /* Mailbox 19 Data Word 0 [15:0] Register       */
825 #define CAN_MB19_DATA1          0xFFC02E64      /* Mailbox 19 Data Word 1 [31:16] Register      */
826 #define CAN_MB19_DATA2          0xFFC02E68      /* Mailbox 19 Data Word 2 [47:32] Register      */
827 #define CAN_MB19_DATA3          0xFFC02E6C      /* Mailbox 19 Data Word 3 [63:48] Register      */
828 #define CAN_MB19_LENGTH         0xFFC02E70      /* Mailbox 19 Data Length Code Register         */
829 #define CAN_MB19_TIMESTAMP      0xFFC02E74      /* Mailbox 19 Time Stamp Value Register         */
830 #define CAN_MB19_ID0            0xFFC02E78      /* Mailbox 19 Identifier Low Register           */
831 #define CAN_MB19_ID1            0xFFC02E7C      /* Mailbox 19 Identifier High Register          */
832
833 #define CAN_MB20_DATA0          0xFFC02E80      /* Mailbox 20 Data Word 0 [15:0] Register       */
834 #define CAN_MB20_DATA1          0xFFC02E84      /* Mailbox 20 Data Word 1 [31:16] Register      */
835 #define CAN_MB20_DATA2          0xFFC02E88      /* Mailbox 20 Data Word 2 [47:32] Register      */
836 #define CAN_MB20_DATA3          0xFFC02E8C      /* Mailbox 20 Data Word 3 [63:48] Register      */
837 #define CAN_MB20_LENGTH         0xFFC02E90      /* Mailbox 20 Data Length Code Register         */
838 #define CAN_MB20_TIMESTAMP      0xFFC02E94      /* Mailbox 20 Time Stamp Value Register         */
839 #define CAN_MB20_ID0            0xFFC02E98      /* Mailbox 20 Identifier Low Register           */
840 #define CAN_MB20_ID1            0xFFC02E9C      /* Mailbox 20 Identifier High Register          */
841
842 #define CAN_MB21_DATA0          0xFFC02EA0      /* Mailbox 21 Data Word 0 [15:0] Register       */
843 #define CAN_MB21_DATA1          0xFFC02EA4      /* Mailbox 21 Data Word 1 [31:16] Register      */
844 #define CAN_MB21_DATA2          0xFFC02EA8      /* Mailbox 21 Data Word 2 [47:32] Register      */
845 #define CAN_MB21_DATA3          0xFFC02EAC      /* Mailbox 21 Data Word 3 [63:48] Register      */
846 #define CAN_MB21_LENGTH         0xFFC02EB0      /* Mailbox 21 Data Length Code Register         */
847 #define CAN_MB21_TIMESTAMP      0xFFC02EB4      /* Mailbox 21 Time Stamp Value Register         */
848 #define CAN_MB21_ID0            0xFFC02EB8      /* Mailbox 21 Identifier Low Register           */
849 #define CAN_MB21_ID1            0xFFC02EBC      /* Mailbox 21 Identifier High Register          */
850
851 #define CAN_MB22_DATA0          0xFFC02EC0      /* Mailbox 22 Data Word 0 [15:0] Register       */
852 #define CAN_MB22_DATA1          0xFFC02EC4      /* Mailbox 22 Data Word 1 [31:16] Register      */
853 #define CAN_MB22_DATA2          0xFFC02EC8      /* Mailbox 22 Data Word 2 [47:32] Register      */
854 #define CAN_MB22_DATA3          0xFFC02ECC      /* Mailbox 22 Data Word 3 [63:48] Register      */
855 #define CAN_MB22_LENGTH         0xFFC02ED0      /* Mailbox 22 Data Length Code Register         */
856 #define CAN_MB22_TIMESTAMP      0xFFC02ED4      /* Mailbox 22 Time Stamp Value Register         */
857 #define CAN_MB22_ID0            0xFFC02ED8      /* Mailbox 22 Identifier Low Register           */
858 #define CAN_MB22_ID1            0xFFC02EDC      /* Mailbox 22 Identifier High Register          */
859
860 #define CAN_MB23_DATA0          0xFFC02EE0      /* Mailbox 23 Data Word 0 [15:0] Register       */
861 #define CAN_MB23_DATA1          0xFFC02EE4      /* Mailbox 23 Data Word 1 [31:16] Register      */
862 #define CAN_MB23_DATA2          0xFFC02EE8      /* Mailbox 23 Data Word 2 [47:32] Register      */
863 #define CAN_MB23_DATA3          0xFFC02EEC      /* Mailbox 23 Data Word 3 [63:48] Register      */
864 #define CAN_MB23_LENGTH         0xFFC02EF0      /* Mailbox 23 Data Length Code Register         */
865 #define CAN_MB23_TIMESTAMP      0xFFC02EF4      /* Mailbox 23 Time Stamp Value Register         */
866 #define CAN_MB23_ID0            0xFFC02EF8      /* Mailbox 23 Identifier Low Register           */
867 #define CAN_MB23_ID1            0xFFC02EFC      /* Mailbox 23 Identifier High Register          */
868
869 #define CAN_MB24_DATA0          0xFFC02F00      /* Mailbox 24 Data Word 0 [15:0] Register       */
870 #define CAN_MB24_DATA1          0xFFC02F04      /* Mailbox 24 Data Word 1 [31:16] Register      */
871 #define CAN_MB24_DATA2          0xFFC02F08      /* Mailbox 24 Data Word 2 [47:32] Register      */
872 #define CAN_MB24_DATA3          0xFFC02F0C      /* Mailbox 24 Data Word 3 [63:48] Register      */
873 #define CAN_MB24_LENGTH         0xFFC02F10      /* Mailbox 24 Data Length Code Register         */
874 #define CAN_MB24_TIMESTAMP      0xFFC02F14      /* Mailbox 24 Time Stamp Value Register         */
875 #define CAN_MB24_ID0            0xFFC02F18      /* Mailbox 24 Identifier Low Register           */
876 #define CAN_MB24_ID1            0xFFC02F1C      /* Mailbox 24 Identifier High Register          */
877
878 #define CAN_MB25_DATA0          0xFFC02F20      /* Mailbox 25 Data Word 0 [15:0] Register       */
879 #define CAN_MB25_DATA1          0xFFC02F24      /* Mailbox 25 Data Word 1 [31:16] Register      */
880 #define CAN_MB25_DATA2          0xFFC02F28      /* Mailbox 25 Data Word 2 [47:32] Register      */
881 #define CAN_MB25_DATA3          0xFFC02F2C      /* Mailbox 25 Data Word 3 [63:48] Register      */
882 #define CAN_MB25_LENGTH         0xFFC02F30      /* Mailbox 25 Data Length Code Register         */
883 #define CAN_MB25_TIMESTAMP      0xFFC02F34      /* Mailbox 25 Time Stamp Value Register         */
884 #define CAN_MB25_ID0            0xFFC02F38      /* Mailbox 25 Identifier Low Register           */
885 #define CAN_MB25_ID1            0xFFC02F3C      /* Mailbox 25 Identifier High Register          */
886
887 #define CAN_MB26_DATA0          0xFFC02F40      /* Mailbox 26 Data Word 0 [15:0] Register       */
888 #define CAN_MB26_DATA1          0xFFC02F44      /* Mailbox 26 Data Word 1 [31:16] Register      */
889 #define CAN_MB26_DATA2          0xFFC02F48      /* Mailbox 26 Data Word 2 [47:32] Register      */
890 #define CAN_MB26_DATA3          0xFFC02F4C      /* Mailbox 26 Data Word 3 [63:48] Register      */
891 #define CAN_MB26_LENGTH         0xFFC02F50      /* Mailbox 26 Data Length Code Register         */
892 #define CAN_MB26_TIMESTAMP      0xFFC02F54      /* Mailbox 26 Time Stamp Value Register         */
893 #define CAN_MB26_ID0            0xFFC02F58      /* Mailbox 26 Identifier Low Register           */
894 #define CAN_MB26_ID1            0xFFC02F5C      /* Mailbox 26 Identifier High Register          */
895
896 #define CAN_MB27_DATA0          0xFFC02F60      /* Mailbox 27 Data Word 0 [15:0] Register       */
897 #define CAN_MB27_DATA1          0xFFC02F64      /* Mailbox 27 Data Word 1 [31:16] Register      */
898 #define CAN_MB27_DATA2          0xFFC02F68      /* Mailbox 27 Data Word 2 [47:32] Register      */
899 #define CAN_MB27_DATA3          0xFFC02F6C      /* Mailbox 27 Data Word 3 [63:48] Register      */
900 #define CAN_MB27_LENGTH         0xFFC02F70      /* Mailbox 27 Data Length Code Register         */
901 #define CAN_MB27_TIMESTAMP      0xFFC02F74      /* Mailbox 27 Time Stamp Value Register         */
902 #define CAN_MB27_ID0            0xFFC02F78      /* Mailbox 27 Identifier Low Register           */
903 #define CAN_MB27_ID1            0xFFC02F7C      /* Mailbox 27 Identifier High Register          */
904
905 #define CAN_MB28_DATA0          0xFFC02F80      /* Mailbox 28 Data Word 0 [15:0] Register       */
906 #define CAN_MB28_DATA1          0xFFC02F84      /* Mailbox 28 Data Word 1 [31:16] Register      */
907 #define CAN_MB28_DATA2          0xFFC02F88      /* Mailbox 28 Data Word 2 [47:32] Register      */
908 #define CAN_MB28_DATA3          0xFFC02F8C      /* Mailbox 28 Data Word 3 [63:48] Register      */
909 #define CAN_MB28_LENGTH         0xFFC02F90      /* Mailbox 28 Data Length Code Register         */
910 #define CAN_MB28_TIMESTAMP      0xFFC02F94      /* Mailbox 28 Time Stamp Value Register         */
911 #define CAN_MB28_ID0            0xFFC02F98      /* Mailbox 28 Identifier Low Register           */
912 #define CAN_MB28_ID1            0xFFC02F9C      /* Mailbox 28 Identifier High Register          */
913
914 #define CAN_MB29_DATA0          0xFFC02FA0      /* Mailbox 29 Data Word 0 [15:0] Register       */
915 #define CAN_MB29_DATA1          0xFFC02FA4      /* Mailbox 29 Data Word 1 [31:16] Register      */
916 #define CAN_MB29_DATA2          0xFFC02FA8      /* Mailbox 29 Data Word 2 [47:32] Register      */
917 #define CAN_MB29_DATA3          0xFFC02FAC      /* Mailbox 29 Data Word 3 [63:48] Register      */
918 #define CAN_MB29_LENGTH         0xFFC02FB0      /* Mailbox 29 Data Length Code Register         */
919 #define CAN_MB29_TIMESTAMP      0xFFC02FB4      /* Mailbox 29 Time Stamp Value Register         */
920 #define CAN_MB29_ID0            0xFFC02FB8      /* Mailbox 29 Identifier Low Register           */
921 #define CAN_MB29_ID1            0xFFC02FBC      /* Mailbox 29 Identifier High Register          */
922
923 #define CAN_MB30_DATA0          0xFFC02FC0      /* Mailbox 30 Data Word 0 [15:0] Register       */
924 #define CAN_MB30_DATA1          0xFFC02FC4      /* Mailbox 30 Data Word 1 [31:16] Register      */
925 #define CAN_MB30_DATA2          0xFFC02FC8      /* Mailbox 30 Data Word 2 [47:32] Register      */
926 #define CAN_MB30_DATA3          0xFFC02FCC      /* Mailbox 30 Data Word 3 [63:48] Register      */
927 #define CAN_MB30_LENGTH         0xFFC02FD0      /* Mailbox 30 Data Length Code Register         */
928 #define CAN_MB30_TIMESTAMP      0xFFC02FD4      /* Mailbox 30 Time Stamp Value Register         */
929 #define CAN_MB30_ID0            0xFFC02FD8      /* Mailbox 30 Identifier Low Register           */
930 #define CAN_MB30_ID1            0xFFC02FDC      /* Mailbox 30 Identifier High Register          */
931
932 #define CAN_MB31_DATA0          0xFFC02FE0      /* Mailbox 31 Data Word 0 [15:0] Register       */
933 #define CAN_MB31_DATA1          0xFFC02FE4      /* Mailbox 31 Data Word 1 [31:16] Register      */
934 #define CAN_MB31_DATA2          0xFFC02FE8      /* Mailbox 31 Data Word 2 [47:32] Register      */
935 #define CAN_MB31_DATA3          0xFFC02FEC      /* Mailbox 31 Data Word 3 [63:48] Register      */
936 #define CAN_MB31_LENGTH         0xFFC02FF0      /* Mailbox 31 Data Length Code Register         */
937 #define CAN_MB31_TIMESTAMP      0xFFC02FF4      /* Mailbox 31 Time Stamp Value Register         */
938 #define CAN_MB31_ID0            0xFFC02FF8      /* Mailbox 31 Identifier Low Register           */
939 #define CAN_MB31_ID1            0xFFC02FFC      /* Mailbox 31 Identifier High Register          */
940
941 /* CAN Mailbox Area Macros                              */
942 #define CAN_MB_ID1(x)           (CAN_MB00_ID1+((x)*0x20))
943 #define CAN_MB_ID0(x)           (CAN_MB00_ID0+((x)*0x20))
944 #define CAN_MB_TIMESTAMP(x)     (CAN_MB00_TIMESTAMP+((x)*0x20))
945 #define CAN_MB_LENGTH(x)        (CAN_MB00_LENGTH+((x)*0x20))
946 #define CAN_MB_DATA3(x)         (CAN_MB00_DATA3+((x)*0x20))
947 #define CAN_MB_DATA2(x)         (CAN_MB00_DATA2+((x)*0x20))
948 #define CAN_MB_DATA1(x)         (CAN_MB00_DATA1+((x)*0x20))
949 #define CAN_MB_DATA0(x)         (CAN_MB00_DATA0+((x)*0x20))
950
951 /* Pin Control Registers        (0xFFC03200 - 0xFFC032FF)                                                                                       */
952 #define PORTF_FER                       0xFFC03200      /* Port F Function Enable Register (Alternate/Flag*)    */
953 #define PORTG_FER                       0xFFC03204      /* Port G Function Enable Register (Alternate/Flag*)    */
954 #define PORTH_FER                       0xFFC03208      /* Port H Function Enable Register (Alternate/Flag*)    */
955 #define BFIN_PORT_MUX                   0xFFC0320C      /* Port Multiplexer Control Register                                    */
956
957 /* Handshake MDMA Registers     (0xFFC03300 - 0xFFC033FF)                                                                               */
958 #define HMDMA0_CONTROL          0xFFC03300      /* Handshake MDMA0 Control Register                                     */
959 #define HMDMA0_ECINIT           0xFFC03304      /* HMDMA0 Initial Edge Count Register                           */
960 #define HMDMA0_BCINIT           0xFFC03308      /* HMDMA0 Initial Block Count Register                          */
961 #define HMDMA0_ECURGENT         0xFFC0330C      /* HMDMA0 Urgent Edge Count Threshhold Register         */
962 #define HMDMA0_ECOVERFLOW       0xFFC03310      /* HMDMA0 Edge Count Overflow Interrupt Register        */
963 #define HMDMA0_ECOUNT           0xFFC03314      /* HMDMA0 Current Edge Count Register                           */
964 #define HMDMA0_BCOUNT           0xFFC03318      /* HMDMA0 Current Block Count Register                          */
965
966 #define HMDMA1_CONTROL          0xFFC03340      /* Handshake MDMA1 Control Register                                     */
967 #define HMDMA1_ECINIT           0xFFC03344      /* HMDMA1 Initial Edge Count Register                           */
968 #define HMDMA1_BCINIT           0xFFC03348      /* HMDMA1 Initial Block Count Register                          */
969 #define HMDMA1_ECURGENT         0xFFC0334C      /* HMDMA1 Urgent Edge Count Threshhold Register         */
970 #define HMDMA1_ECOVERFLOW       0xFFC03350      /* HMDMA1 Edge Count Overflow Interrupt Register        */
971 #define HMDMA1_ECOUNT           0xFFC03354      /* HMDMA1 Current Edge Count Register                           */
972 #define HMDMA1_BCOUNT           0xFFC03358      /* HMDMA1 Current Block Count Register                          */
973
974 /***********************************************************************************
975 ** System MMR Register Bits And Macros
976 **
977 ** Disclaimer:  All macros are intended to make C and Assembly code more readable.
978 **                              Use these macros carefully, as any that do left shifts for field
979 **                              depositing will result in the lower order bits being destroyed.  Any
980 **                              macro that shifts left to properly position the bit-field should be
981 **                              used as part of an OR to initialize a register and NOT as a dynamic
982 **                              modifier UNLESS the lower order bits are saved and ORed back in when
983 **                              the macro is used.
984 *************************************************************************************/
985 /*
986 ** ********************* PLL AND RESET MASKS ****************************************/
987 /* PLL_CTL Masks                                                                                                                                        */
988 #define DF                              0x0001  /* 0: PLL = CLKIN, 1: PLL = CLKIN/2                                     */
989 #define PLL_OFF                 0x0002  /* PLL Not Powered                                                                      */
990 #define STOPCK                  0x0008  /* Core Clock Off                                                                       */
991 #define PDWN                    0x0020  /* Enter Deep Sleep Mode                                                        */
992 #define IN_DELAY                0x0040  /* Add 200ps Delay To EBIU Input Latches                        */
993 #define OUT_DELAY               0x0080  /* Add 200ps Delay To EBIU Output Signals                       */
994 #define BYPASS                  0x0100  /* Bypass the PLL                                                                       */
995 #define MSEL                    0x7E00  /* Multiplier Select For CCLK/VCO Factors                       */
996 /* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits)                       */
997 #define SET_MSEL(x)             (((x)&0x3F) << 0x9)     /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL         */
998
999 /* PLL_DIV Masks                                                                                                                */
1000 #define SSEL                    0x000F  /* System Select                                                */
1001 #define CSEL                    0x0030  /* Core Select                                                  */
1002 #define CSEL_DIV1               0x0000  /*              CCLK = VCO / 1                                  */
1003 #define CSEL_DIV2               0x0010  /*              CCLK = VCO / 2                                  */
1004 #define CSEL_DIV4               0x0020  /*              CCLK = VCO / 4                                  */
1005 #define CSEL_DIV8               0x0030  /*              CCLK = VCO / 8                                  */
1006 /* PLL_DIV Macros                                                                                                               */
1007 #define SET_SSEL(x)             ((x)&0xF)       /* Set SSEL = 0-15 --> SCLK = VCO/SSEL  */
1008
1009 /* VR_CTL Masks                                                                                                                                 */
1010 #define FREQ                    0x0003  /* Switching Oscillator Frequency For Regulator */
1011 #define HIBERNATE               0x0000  /*              Powerdown/Bypass On-Board Regulation    */
1012 #define FREQ_333                0x0001  /*              Switching Frequency Is 333 kHz                  */
1013 #define FREQ_667                0x0002  /*              Switching Frequency Is 667 kHz                  */
1014 #define FREQ_1000               0x0003  /*              Switching Frequency Is 1 MHz                    */
1015
1016 #define GAIN                    0x000C  /* Voltage Level Gain   */
1017 #define GAIN_5                  0x0000  /*              GAIN = 5                */
1018 #define GAIN_10                 0x0004  /*              GAIN = 10               */
1019 #define GAIN_20                 0x0008  /*              GAIN = 20               */
1020 #define GAIN_50                 0x000C  /*              GAIN = 50               */
1021
1022 #define VLEV                    0x00F0  /* Internal Voltage Level                                       */
1023 #define VLEV_085                0x0060  /*              VLEV = 0.85 V (-5% - +10% Accuracy)     */
1024 #define VLEV_090                0x0070  /*              VLEV = 0.90 V (-5% - +10% Accuracy)     */
1025 #define VLEV_095                0x0080  /*              VLEV = 0.95 V (-5% - +10% Accuracy)     */
1026 #define VLEV_100                0x0090  /*              VLEV = 1.00 V (-5% - +10% Accuracy)     */
1027 #define VLEV_105                0x00A0  /*              VLEV = 1.05 V (-5% - +10% Accuracy)     */
1028 #define VLEV_110                0x00B0  /*              VLEV = 1.10 V (-5% - +10% Accuracy)     */
1029 #define VLEV_115                0x00C0  /*              VLEV = 1.15 V (-5% - +10% Accuracy)     */
1030 #define VLEV_120                0x00D0  /*              VLEV = 1.20 V (-5% - +10% Accuracy)     */
1031 #define VLEV_125                0x00E0  /*              VLEV = 1.25 V (-5% - +10% Accuracy)     */
1032 #define VLEV_130                0x00F0  /*              VLEV = 1.30 V (-5% - +10% Accuracy)     */
1033
1034 #define WAKE                    0x0100  /* Enable RTC/Reset Wakeup From Hibernate       */
1035 #define CANWE                   0x0200  /* Enable CAN Wakeup From Hibernate                     */
1036 #define PHYWE                   0x0400  /* Enable PHY Wakeup From Hibernate                     */
1037 #define CLKBUFOE                0x4000  /* CLKIN Buffer Output Enable */
1038 #define PHYCLKOE                CLKBUFOE        /* Alternative legacy name for the above */
1039 #define SCKELOW         0x8000  /* Enable Drive CKE Low During Reset            */
1040
1041 /* PLL_STAT Masks                                                                                                                                       */
1042 #define ACTIVE_PLLENABLED       0x0001  /* Processor In Active Mode With PLL Enabled    */
1043 #define FULL_ON                         0x0002  /* Processor In Full On Mode                                    */
1044 #define ACTIVE_PLLDISABLED      0x0004  /* Processor In Active Mode With PLL Disabled   */
1045 #define PLL_LOCKED                      0x0020  /* PLL_LOCKCNT Has Been Reached                                 */
1046
1047 /* CHIPID Masks */
1048 #define CHIPID_VERSION         0xF0000000
1049 #define CHIPID_FAMILY          0x0FFFF000
1050 #define CHIPID_MANUFACTURE     0x00000FFE
1051
1052 /* SWRST Masks                                                                                                                                          */
1053 #define SYSTEM_RESET            0x0007  /* Initiates A System Software Reset                    */
1054 #define DOUBLE_FAULT            0x0008  /* Core Double Fault Causes Reset                               */
1055 #define RESET_DOUBLE            0x2000  /* SW Reset Generated By Core Double-Fault              */
1056 #define RESET_WDOG                      0x4000  /* SW Reset Generated By Watchdog Timer                 */
1057 #define RESET_SOFTWARE          0x8000  /* SW Reset Occurred Since Last Read Of SWRST   */
1058
1059 /* SYSCR Masks                                                                                                                                                          */
1060 #define BMODE                           0x0007  /* Boot Mode - Latched During HW Reset From Mode Pins   */
1061 #define NOBOOT                          0x0010  /* Execute From L1 or ASYNC Bank 0 When BMODE = 0               */
1062
1063 /* *************  SYSTEM INTERRUPT CONTROLLER MASKS *************************************/
1064
1065 /* SIC_IAR0 Macros                                                                                                                      */
1066 #define P0_IVG(x)               (((x)&0xF)-7)   /* Peripheral #0 assigned IVG #x        */
1067 #define P1_IVG(x)               (((x)&0xF)-7) << 0x4    /* Peripheral #1 assigned IVG #x        */
1068 #define P2_IVG(x)               (((x)&0xF)-7) << 0x8    /* Peripheral #2 assigned IVG #x        */
1069 #define P3_IVG(x)               (((x)&0xF)-7) << 0xC    /* Peripheral #3 assigned IVG #x        */
1070 #define P4_IVG(x)               (((x)&0xF)-7) << 0x10   /* Peripheral #4 assigned IVG #x        */
1071 #define P5_IVG(x)               (((x)&0xF)-7) << 0x14   /* Peripheral #5 assigned IVG #x        */
1072 #define P6_IVG(x)               (((x)&0xF)-7) << 0x18   /* Peripheral #6 assigned IVG #x        */
1073 #define P7_IVG(x)               (((x)&0xF)-7) << 0x1C   /* Peripheral #7 assigned IVG #x        */
1074
1075 /* SIC_IAR1 Macros                                                                                                                      */
1076 #define P8_IVG(x)               (((x)&0xF)-7)   /* Peripheral #8 assigned IVG #x        */
1077 #define P9_IVG(x)               (((x)&0xF)-7) << 0x4    /* Peripheral #9 assigned IVG #x        */
1078 #define P10_IVG(x)              (((x)&0xF)-7) << 0x8    /* Peripheral #10 assigned IVG #x       */
1079 #define P11_IVG(x)              (((x)&0xF)-7) << 0xC    /* Peripheral #11 assigned IVG #x       */
1080 #define P12_IVG(x)              (((x)&0xF)-7) << 0x10   /* Peripheral #12 assigned IVG #x       */
1081 #define P13_IVG(x)              (((x)&0xF)-7) << 0x14   /* Peripheral #13 assigned IVG #x       */
1082 #define P14_IVG(x)              (((x)&0xF)-7) << 0x18   /* Peripheral #14 assigned IVG #x       */
1083 #define P15_IVG(x)              (((x)&0xF)-7) << 0x1C   /* Peripheral #15 assigned IVG #x       */
1084
1085 /* SIC_IAR2 Macros                                                                                                                      */
1086 #define P16_IVG(x)              (((x)&0xF)-7)   /* Peripheral #16 assigned IVG #x       */
1087 #define P17_IVG(x)              (((x)&0xF)-7) << 0x4    /* Peripheral #17 assigned IVG #x       */
1088 #define P18_IVG(x)              (((x)&0xF)-7) << 0x8    /* Peripheral #18 assigned IVG #x       */
1089 #define P19_IVG(x)              (((x)&0xF)-7) << 0xC    /* Peripheral #19 assigned IVG #x       */
1090 #define P20_IVG(x)              (((x)&0xF)-7) << 0x10   /* Peripheral #20 assigned IVG #x       */
1091 #define P21_IVG(x)              (((x)&0xF)-7) << 0x14   /* Peripheral #21 assigned IVG #x       */
1092 #define P22_IVG(x)              (((x)&0xF)-7) << 0x18   /* Peripheral #22 assigned IVG #x       */
1093 #define P23_IVG(x)              (((x)&0xF)-7) << 0x1C   /* Peripheral #23 assigned IVG #x       */
1094
1095 /* SIC_IAR3 Macros                                                                                                                      */
1096 #define P24_IVG(x)              (((x)&0xF)-7)   /* Peripheral #24 assigned IVG #x       */
1097 #define P25_IVG(x)              (((x)&0xF)-7) << 0x4    /* Peripheral #25 assigned IVG #x       */
1098 #define P26_IVG(x)              (((x)&0xF)-7) << 0x8    /* Peripheral #26 assigned IVG #x       */
1099 #define P27_IVG(x)              (((x)&0xF)-7) << 0xC    /* Peripheral #27 assigned IVG #x       */
1100 #define P28_IVG(x)              (((x)&0xF)-7) << 0x10   /* Peripheral #28 assigned IVG #x       */
1101 #define P29_IVG(x)              (((x)&0xF)-7) << 0x14   /* Peripheral #29 assigned IVG #x       */
1102 #define P30_IVG(x)              (((x)&0xF)-7) << 0x18   /* Peripheral #30 assigned IVG #x       */
1103 #define P31_IVG(x)              (((x)&0xF)-7) << 0x1C   /* Peripheral #31 assigned IVG #x       */
1104
1105 /* SIC_IMASK Masks                                                                                                                                              */
1106 #define SIC_UNMASK_ALL  0x00000000      /* Unmask all peripheral interrupts     */
1107 #define SIC_MASK_ALL    0xFFFFFFFF      /* Mask all peripheral interrupts       */
1108 #define SIC_MASK(x)             (1 << ((x)&0x1F))       /* Mask Peripheral #x interrupt         */
1109 #define SIC_UNMASK(x)   (0xFFFFFFFF ^ (1 << ((x)&0x1F)))        /* Unmask Peripheral #x interrupt       */
1110
1111 /* SIC_IWR Masks                                                                                                                                                */
1112 #define IWR_DISABLE_ALL 0x00000000      /* Wakeup Disable all peripherals       */
1113 #define IWR_ENABLE_ALL  0xFFFFFFFF      /* Wakeup Enable all peripherals        */
1114 #define IWR_ENABLE(x)   (1 << ((x)&0x1F))       /* Wakeup Enable Peripheral #x          */
1115 #define IWR_DISABLE(x)  (0xFFFFFFFF ^ (1 << ((x)&0x1F)))        /* Wakeup Disable Peripheral #x         */
1116
1117 /* ************** UART CONTROLLER MASKS *************************/
1118 /* UARTx_LCR Masks                                                                                              */
1119 #define WLS(x)          (((x)-5) & 0x03)        /* Word Length Select   */
1120 #define STB                     0x04    /* Stop Bits                    */
1121 #define PEN                     0x08    /* Parity Enable                */
1122 #define EPS                     0x10    /* Even Parity Select   */
1123 #define STP                     0x20    /* Stick Parity                 */
1124 #define SB                      0x40    /* Set Break                    */
1125 #define DLAB            0x80    /* Divisor Latch Access */
1126
1127 /* UARTx_MCR Mask                                                                               */
1128 #define LOOP_ENA                0x10    /* Loopback Mode Enable         */
1129 #define LOOP_ENA_P      0x04
1130 /* UARTx_LSR Masks                                                                              */
1131 #define DR                      0x01    /* Data Ready                           */
1132 #define OE                      0x02    /* Overrun Error                        */
1133 #define PE                      0x04    /* Parity Error                         */
1134 #define FE                      0x08    /* Framing Error                        */
1135 #define BI                      0x10    /* Break Interrupt                      */
1136 #define THRE            0x20    /* THR Empty                            */
1137 #define TEMT            0x40    /* TSR and UART_THR Empty       */
1138
1139 /* UARTx_IER Masks                                                                                                                      */
1140 #define ERBFI           0x01    /* Enable Receive Buffer Full Interrupt         */
1141 #define ETBEI           0x02    /* Enable Transmit Buffer Empty Interrupt       */
1142 #define ELSI            0x04    /* Enable RX Status Interrupt                           */
1143
1144 /* UARTx_IIR Masks                                                                                                              */
1145 #define NINT            0x01    /* Pending Interrupt                                    */
1146 #define IIR_TX_READY    0x02    /* UART_THR empty                               */
1147 #define IIR_RX_READY    0x04    /* Receive data ready                           */
1148 #define IIR_LINE_CHANGE 0x06    /* Receive line status                          */
1149 #define IIR_STATUS      0x06
1150
1151 /* UARTx_GCTL Masks                                                                                                     */
1152 #define UCEN            0x01    /* Enable UARTx Clocks                          */
1153 #define IREN            0x02    /* Enable IrDA Mode                                     */
1154 #define TPOLC           0x04    /* IrDA TX Polarity Change                      */
1155 #define RPOLC           0x08    /* IrDA RX Polarity Change                      */
1156 #define FPE                     0x10    /* Force Parity Error On Transmit       */
1157 #define FFE                     0x20    /* Force Framing Error On Transmit      */
1158
1159 /* ***********  SERIAL PERIPHERAL INTERFACE (SPI) MASKS  ****************************/
1160 /* SPI_CTL Masks                                                                                                                                        */
1161 #define TIMOD           0x0003  /* Transfer Initiate Mode                                                       */
1162 #define RDBR_CORE       0x0000  /*              RDBR Read Initiates, IRQ When RDBR Full         */
1163 #define TDBR_CORE       0x0001  /*              TDBR Write Initiates, IRQ When TDBR Empty       */
1164 #define RDBR_DMA        0x0002  /*              DMA Read, DMA Until FIFO Empty                          */
1165 #define TDBR_DMA        0x0003  /*              DMA Write, DMA Until FIFO Full                          */
1166 #define SZ                      0x0004  /* Send Zero (When TDBR Empty, Send Zero/Last*)         */
1167 #define GM                      0x0008  /* Get More (When RDBR Full, Overwrite/Discard*)        */
1168 #define PSSE            0x0010  /* Slave-Select Input Enable                                            */
1169 #define EMISO           0x0020  /* Enable MISO As Output                                                        */
1170 #define SIZE            0x0100  /* Size of Words (16/8* Bits)                                           */
1171 #define LSBF            0x0200  /* LSB First                                                                            */
1172 #define CPHA            0x0400  /* Clock Phase                                                                          */
1173 #define CPOL            0x0800  /* Clock Polarity                                                                       */
1174 #define MSTR            0x1000  /* Master/Slave*                                                                        */
1175 #define WOM                     0x2000  /* Write Open Drain Master                                                      */
1176 #define SPE                     0x4000  /* SPI Enable                                                                           */
1177
1178 /* SPI_FLG Masks                                                                                                                                        */
1179 #define FLS1            0x0002  /* Enables SPI_FLOUT1 as SPI Slave-Select Output        */
1180 #define FLS2            0x0004  /* Enables SPI_FLOUT2 as SPI Slave-Select Output        */
1181 #define FLS3            0x0008  /* Enables SPI_FLOUT3 as SPI Slave-Select Output        */
1182 #define FLS4            0x0010  /* Enables SPI_FLOUT4 as SPI Slave-Select Output        */
1183 #define FLS5            0x0020  /* Enables SPI_FLOUT5 as SPI Slave-Select Output        */
1184 #define FLS6            0x0040  /* Enables SPI_FLOUT6 as SPI Slave-Select Output        */
1185 #define FLS7            0x0080  /* Enables SPI_FLOUT7 as SPI Slave-Select Output        */
1186 #define FLG1            0xFDFF  /* Activates SPI_FLOUT1                                                         */
1187 #define FLG2            0xFBFF  /* Activates SPI_FLOUT2                                                         */
1188 #define FLG3            0xF7FF  /* Activates SPI_FLOUT3                                                         */
1189 #define FLG4            0xEFFF  /* Activates SPI_FLOUT4                                                         */
1190 #define FLG5            0xDFFF  /* Activates SPI_FLOUT5                                                         */
1191 #define FLG6            0xBFFF  /* Activates SPI_FLOUT6                                                         */
1192 #define FLG7            0x7FFF  /* Activates SPI_FLOUT7                                                         */
1193
1194 /* SPI_STAT Masks                                                                                                                                                               */
1195 #define SPIF            0x0001  /* SPI Finished (Single-Word Transfer Complete)                                 */
1196 #define MODF            0x0002  /* Mode Fault Error (Another Device Tried To Become Master)             */
1197 #define TXE                     0x0004  /* Transmission Error (Data Sent With No New Data In TDBR)              */
1198 #define TXS                     0x0008  /* SPI_TDBR Data Buffer Status (Full/Empty*)                                    */
1199 #define RBSY            0x0010  /* Receive Error (Data Received With RDBR Full)                                 */
1200 #define RXS                     0x0020  /* SPI_RDBR Data Buffer Status (Full/Empty*)                                    */
1201 #define TXCOL           0x0040  /* Transmit Collision Error (Corrupt Data May Have Been Sent)   */
1202
1203 /*  ****************  GENERAL PURPOSE TIMER MASKS  **********************/
1204 /* TIMER_ENABLE Masks                                                                                                   */
1205 #define TIMEN0                  0x0001  /* Enable Timer 0                                       */
1206 #define TIMEN1                  0x0002  /* Enable Timer 1                                       */
1207 #define TIMEN2                  0x0004  /* Enable Timer 2                                       */
1208 #define TIMEN3                  0x0008  /* Enable Timer 3                                       */
1209 #define TIMEN4                  0x0010  /* Enable Timer 4                                       */
1210 #define TIMEN5                  0x0020  /* Enable Timer 5                                       */
1211 #define TIMEN6                  0x0040  /* Enable Timer 6                                       */
1212 #define TIMEN7                  0x0080  /* Enable Timer 7                                       */
1213
1214 /* TIMER_DISABLE Masks                                                                                                  */
1215 #define TIMDIS0                 TIMEN0  /* Disable Timer 0                                      */
1216 #define TIMDIS1                 TIMEN1  /* Disable Timer 1                                      */
1217 #define TIMDIS2                 TIMEN2  /* Disable Timer 2                                      */
1218 #define TIMDIS3                 TIMEN3  /* Disable Timer 3                                      */
1219 #define TIMDIS4                 TIMEN4  /* Disable Timer 4                                      */
1220 #define TIMDIS5                 TIMEN5  /* Disable Timer 5                                      */
1221 #define TIMDIS6                 TIMEN6  /* Disable Timer 6                                      */
1222 #define TIMDIS7                 TIMEN7  /* Disable Timer 7                                      */
1223
1224 /* TIMER_STATUS Masks                                                                                                   */
1225 #define TIMIL0                  0x00000001      /* Timer 0 Interrupt                            */
1226 #define TIMIL1                  0x00000002      /* Timer 1 Interrupt                            */
1227 #define TIMIL2                  0x00000004      /* Timer 2 Interrupt                            */
1228 #define TIMIL3                  0x00000008      /* Timer 3 Interrupt                            */
1229 #define TOVF_ERR0               0x00000010      /* Timer 0 Counter Overflow                     */
1230 #define TOVF_ERR1               0x00000020      /* Timer 1 Counter Overflow                     */
1231 #define TOVF_ERR2               0x00000040      /* Timer 2 Counter Overflow                     */
1232 #define TOVF_ERR3               0x00000080      /* Timer 3 Counter Overflow                     */
1233 #define TRUN0                   0x00001000      /* Timer 0 Slave Enable Status          */
1234 #define TRUN1                   0x00002000      /* Timer 1 Slave Enable Status          */
1235 #define TRUN2                   0x00004000      /* Timer 2 Slave Enable Status          */
1236 #define TRUN3                   0x00008000      /* Timer 3 Slave Enable Status          */
1237 #define TIMIL4                  0x00010000      /* Timer 4 Interrupt                            */
1238 #define TIMIL5                  0x00020000      /* Timer 5 Interrupt                            */
1239 #define TIMIL6                  0x00040000      /* Timer 6 Interrupt                            */
1240 #define TIMIL7                  0x00080000      /* Timer 7 Interrupt                            */
1241 #define TOVF_ERR4               0x00100000      /* Timer 4 Counter Overflow                     */
1242 #define TOVF_ERR5               0x00200000      /* Timer 5 Counter Overflow                     */
1243 #define TOVF_ERR6               0x00400000      /* Timer 6 Counter Overflow                     */
1244 #define TOVF_ERR7               0x00800000      /* Timer 7 Counter Overflow                     */
1245 #define TRUN4                   0x10000000      /* Timer 4 Slave Enable Status          */
1246 #define TRUN5                   0x20000000      /* Timer 5 Slave Enable Status          */
1247 #define TRUN6                   0x40000000      /* Timer 6 Slave Enable Status          */
1248 #define TRUN7                   0x80000000      /* Timer 7 Slave Enable Status          */
1249
1250 /* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
1251 #define TOVL_ERR0 TOVF_ERR0
1252 #define TOVL_ERR1 TOVF_ERR1
1253 #define TOVL_ERR2 TOVF_ERR2
1254 #define TOVL_ERR3 TOVF_ERR3
1255 #define TOVL_ERR4 TOVF_ERR4
1256 #define TOVL_ERR5 TOVF_ERR5
1257 #define TOVL_ERR6 TOVF_ERR6
1258 #define TOVL_ERR7 TOVF_ERR7
1259 /* TIMERx_CONFIG Masks                                                                                                  */
1260 #define PWM_OUT                 0x0001  /* Pulse-Width Modulation Output Mode   */
1261 #define WDTH_CAP                0x0002  /* Width Capture Input Mode                             */
1262 #define EXT_CLK                 0x0003  /* External Clock Mode                                  */
1263 #define PULSE_HI                0x0004  /* Action Pulse (Positive/Negative*)    */
1264 #define PERIOD_CNT              0x0008  /* Period Count                                                 */
1265 #define IRQ_ENA                 0x0010  /* Interrupt Request Enable                             */
1266 #define TIN_SEL                 0x0020  /* Timer Input Select                                   */
1267 #define OUT_DIS                 0x0040  /* Output Pad Disable                                   */
1268 #define CLK_SEL                 0x0080  /* Timer Clock Select                                   */
1269 #define TOGGLE_HI               0x0100  /* PWM_OUT PULSE_HI Toggle Mode                 */
1270 #define EMU_RUN                 0x0200  /* Emulation Behavior Select                    */
1271 #define ERR_TYP                 0xC000  /* Error Type                                                   */
1272
1273 /* ******************   GPIO PORTS F, G, H MASKS  ***********************/
1274 /*  General Purpose IO (0xFFC00700 - 0xFFC007FF)  Masks                                 */
1275 /* Port F Masks                                                                                                                 */
1276 #define PF0             0x0001
1277 #define PF1             0x0002
1278 #define PF2             0x0004
1279 #define PF3             0x0008
1280 #define PF4             0x0010
1281 #define PF5             0x0020
1282 #define PF6             0x0040
1283 #define PF7             0x0080
1284 #define PF8             0x0100
1285 #define PF9             0x0200
1286 #define PF10    0x0400
1287 #define PF11    0x0800
1288 #define PF12    0x1000
1289 #define PF13    0x2000
1290 #define PF14    0x4000
1291 #define PF15    0x8000
1292
1293 /* Port G Masks                                                                                                                 */
1294 #define PG0             0x0001
1295 #define PG1             0x0002
1296 #define PG2             0x0004
1297 #define PG3             0x0008
1298 #define PG4             0x0010
1299 #define PG5             0x0020
1300 #define PG6             0x0040
1301 #define PG7             0x0080
1302 #define PG8             0x0100
1303 #define PG9             0x0200
1304 #define PG10    0x0400
1305 #define PG11    0x0800
1306 #define PG12    0x1000
1307 #define PG13    0x2000
1308 #define PG14    0x4000
1309 #define PG15    0x8000
1310
1311 /* Port H Masks                                                                                                                 */
1312 #define PH0             0x0001
1313 #define PH1             0x0002
1314 #define PH2             0x0004
1315 #define PH3             0x0008
1316 #define PH4             0x0010
1317 #define PH5             0x0020
1318 #define PH6             0x0040
1319 #define PH7             0x0080
1320 #define PH8             0x0100
1321 #define PH9             0x0200
1322 #define PH10    0x0400
1323 #define PH11    0x0800
1324 #define PH12    0x1000
1325 #define PH13    0x2000
1326 #define PH14    0x4000
1327 #define PH15    0x8000
1328
1329 /* *******************  SERIAL PORT MASKS  **************************************/
1330 /* SPORTx_TCR1 Masks                                                                                                                    */
1331 #define TSPEN           0x0001  /* Transmit Enable                                                              */
1332 #define ITCLK           0x0002  /* Internal Transmit Clock Select                               */
1333 #define DTYPE_NORM      0x0004  /* Data Format Normal                                                   */
1334 #define DTYPE_ULAW      0x0008  /* Compand Using u-Law                                                  */
1335 #define DTYPE_ALAW      0x000C  /* Compand Using A-Law                                                  */
1336 #define TLSBIT          0x0010  /* Transmit Bit Order                                                   */
1337 #define ITFS            0x0200  /* Internal Transmit Frame Sync Select                  */
1338 #define TFSR            0x0400  /* Transmit Frame Sync Required Select                  */
1339 #define DITFS           0x0800  /* Data-Independent Transmit Frame Sync Select  */
1340 #define LTFS            0x1000  /* Low Transmit Frame Sync Select                               */
1341 #define LATFS           0x2000  /* Late Transmit Frame Sync Select                              */
1342 #define TCKFE           0x4000  /* Clock Falling Edge Select                                    */
1343
1344 /* SPORTx_TCR2 Masks and Macro                                                                                                  */
1345 #define SLEN(x)         ((x)&0x1F)      /* SPORT TX Word Length (2 - 31)                                */
1346 #define TXSE            0x0100  /* TX Secondary Enable                                                  */
1347 #define TSFSE           0x0200  /* Transmit Stereo Frame Sync Enable                    */
1348 #define TRFST           0x0400  /* Left/Right Order (1 = Right Channel 1st)             */
1349
1350 /* SPORTx_RCR1 Masks                                                                                                                    */
1351 #define RSPEN           0x0001  /* Receive Enable                                                               */
1352 #define IRCLK           0x0002  /* Internal Receive Clock Select                                */
1353 #define DTYPE_NORM      0x0004  /* Data Format Normal                                                   */
1354 #define DTYPE_ULAW      0x0008  /* Compand Using u-Law                                                  */
1355 #define DTYPE_ALAW      0x000C  /* Compand Using A-Law                                                  */
1356 #define RLSBIT          0x0010  /* Receive Bit Order                                                    */
1357 #define IRFS            0x0200  /* Internal Receive Frame Sync Select                   */
1358 #define RFSR            0x0400  /* Receive Frame Sync Required Select                   */
1359 #define LRFS            0x1000  /* Low Receive Frame Sync Select                                */
1360 #define LARFS           0x2000  /* Late Receive Frame Sync Select                               */
1361 #define RCKFE           0x4000  /* Clock Falling Edge Select                                    */
1362
1363 /* SPORTx_RCR2 Masks                                                                                                                    */
1364 #define SLEN(x)         ((x)&0x1F)      /* SPORT RX Word Length (2 - 31)                                */
1365 #define RXSE            0x0100  /* RX Secondary Enable                                                  */
1366 #define RSFSE           0x0200  /* RX Stereo Frame Sync Enable                                  */
1367 #define RRFST           0x0400  /* Right-First Data Order                                               */
1368
1369 /* SPORTx_STAT Masks                                                                                                                    */
1370 #define RXNE            0x0001  /* Receive FIFO Not Empty Status                                */
1371 #define RUVF            0x0002  /* Sticky Receive Underflow Status                              */
1372 #define ROVF            0x0004  /* Sticky Receive Overflow Status                               */
1373 #define TXF                     0x0008  /* Transmit FIFO Full Status                                    */
1374 #define TUVF            0x0010  /* Sticky Transmit Underflow Status                             */
1375 #define TOVF            0x0020  /* Sticky Transmit Overflow Status                              */
1376 #define TXHRE           0x0040  /* Transmit Hold Register Empty                                 */
1377
1378 /* SPORTx_MCMC1 Macros                                                                                                                  */
1379 #define SP_WOFF(x)              ((x) & 0x3FF)   /* Multichannel Window Offset Field                     */
1380
1381 /* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits                                            */
1382 #define SP_WSIZE(x)     (((((x)>>0x3)-1)&0xF) << 0xC)   /* Multichannel Window Size = (x/8)-1   */
1383
1384 /* SPORTx_MCMC2 Masks                                                                                                                   */
1385 #define REC_BYPASS      0x0000  /* Bypass Mode (No Clock Recovery)                              */
1386 #define REC_2FROM4      0x0002  /* Recover 2 MHz Clock from 4 MHz Clock                 */
1387 #define REC_8FROM16     0x0003  /* Recover 8 MHz Clock from 16 MHz Clock                */
1388 #define MCDTXPE         0x0004  /* Multichannel DMA Transmit Packing                    */
1389 #define MCDRXPE         0x0008  /* Multichannel DMA Receive Packing                             */
1390 #define MCMEN           0x0010  /* Multichannel Frame Mode Enable                               */
1391 #define FSDR            0x0080  /* Multichannel Frame Sync to Data Relationship */
1392 #define MFD_0           0x0000  /* Multichannel Frame Delay = 0                                 */
1393 #define MFD_1           0x1000  /* Multichannel Frame Delay = 1                                 */
1394 #define MFD_2           0x2000  /* Multichannel Frame Delay = 2                                 */
1395 #define MFD_3           0x3000  /* Multichannel Frame Delay = 3                                 */
1396 #define MFD_4           0x4000  /* Multichannel Frame Delay = 4                                 */
1397 #define MFD_5           0x5000  /* Multichannel Frame Delay = 5                                 */
1398 #define MFD_6           0x6000  /* Multichannel Frame Delay = 6                                 */
1399 #define MFD_7           0x7000  /* Multichannel Frame Delay = 7                                 */
1400 #define MFD_8           0x8000  /* Multichannel Frame Delay = 8                                 */
1401 #define MFD_9           0x9000  /* Multichannel Frame Delay = 9                                 */
1402 #define MFD_10          0xA000  /* Multichannel Frame Delay = 10                                */
1403 #define MFD_11          0xB000  /* Multichannel Frame Delay = 11                                */
1404 #define MFD_12          0xC000  /* Multichannel Frame Delay = 12                                */
1405 #define MFD_13          0xD000  /* Multichannel Frame Delay = 13                                */
1406 #define MFD_14          0xE000  /* Multichannel Frame Delay = 14                                */
1407 #define MFD_15          0xF000  /* Multichannel Frame Delay = 15                                */
1408
1409 /* *********************  ASYNCHRONOUS MEMORY CONTROLLER MASKS  *************************/
1410 /* EBIU_AMGCTL Masks                                                                                                                                    */
1411 #define AMCKEN                  0x0001  /* Enable CLKOUT                                                                        */
1412 #define AMBEN_NONE              0x0000  /* All Banks Disabled                                                           */
1413 #define AMBEN_B0                0x0002  /* Enable Async Memory Bank 0 only                                      */
1414 #define AMBEN_B0_B1             0x0004  /* Enable Async Memory Banks 0 & 1 only                         */
1415 #define AMBEN_B0_B1_B2  0x0006  /* Enable Async Memory Banks 0, 1, and 2                        */
1416 #define AMBEN_ALL               0x0008  /* Enable Async Memory Banks (all) 0, 1, 2, and 3       */
1417
1418 /* EBIU_AMBCTL0 Masks                                                                                                                                   */
1419 #define B0RDYEN                 0x00000001      /* Bank 0 (B0) RDY Enable                                                   */
1420 #define B0RDYPOL                0x00000002      /* B0 RDY Active High                                                               */
1421 #define B0TT_1                  0x00000004      /* B0 Transition Time (Read to Write) = 1 cycle             */
1422 #define B0TT_2                  0x00000008      /* B0 Transition Time (Read to Write) = 2 cycles    */
1423 #define B0TT_3                  0x0000000C      /* B0 Transition Time (Read to Write) = 3 cycles    */
1424 #define B0TT_4                  0x00000000      /* B0 Transition Time (Read to Write) = 4 cycles    */
1425 #define B0ST_1                  0x00000010      /* B0 Setup Time (AOE to Read/Write) = 1 cycle              */
1426 #define B0ST_2                  0x00000020      /* B0 Setup Time (AOE to Read/Write) = 2 cycles             */
1427 #define B0ST_3                  0x00000030      /* B0 Setup Time (AOE to Read/Write) = 3 cycles             */
1428 #define B0ST_4                  0x00000000      /* B0 Setup Time (AOE to Read/Write) = 4 cycles             */
1429 #define B0HT_1                  0x00000040      /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle             */
1430 #define B0HT_2                  0x00000080      /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles    */
1431 #define B0HT_3                  0x000000C0      /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles    */
1432 #define B0HT_0                  0x00000000      /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles    */
1433 #define B0RAT_1                 0x00000100      /* B0 Read Access Time = 1 cycle                                    */
1434 #define B0RAT_2                 0x00000200      /* B0 Read Access Time = 2 cycles                                   */
1435 #define B0RAT_3                 0x00000300      /* B0 Read Access Time = 3 cycles                                   */
1436 #define B0RAT_4                 0x00000400      /* B0 Read Access Time = 4 cycles                                   */
1437 #define B0RAT_5                 0x00000500      /* B0 Read Access Time = 5 cycles                                   */
1438 #define B0RAT_6                 0x00000600      /* B0 Read Access Time = 6 cycles                                   */
1439 #define B0RAT_7                 0x00000700      /* B0 Read Access Time = 7 cycles                                   */
1440 #define B0RAT_8                 0x00000800      /* B0 Read Access Time = 8 cycles                                   */
1441 #define B0RAT_9                 0x00000900      /* B0 Read Access Time = 9 cycles                                   */
1442 #define B0RAT_10                0x00000A00      /* B0 Read Access Time = 10 cycles                                  */
1443 #define B0RAT_11                0x00000B00      /* B0 Read Access Time = 11 cycles                                  */
1444 #define B0RAT_12                0x00000C00      /* B0 Read Access Time = 12 cycles                                  */
1445 #define B0RAT_13                0x00000D00      /* B0 Read Access Time = 13 cycles                                  */
1446 #define B0RAT_14                0x00000E00      /* B0 Read Access Time = 14 cycles                                  */
1447 #define B0RAT_15                0x00000F00      /* B0 Read Access Time = 15 cycles                                  */
1448 #define B0WAT_1                 0x00001000      /* B0 Write Access Time = 1 cycle                                   */
1449 #define B0WAT_2                 0x00002000      /* B0 Write Access Time = 2 cycles                                  */
1450 #define B0WAT_3                 0x00003000      /* B0 Write Access Time = 3 cycles                                  */
1451 #define B0WAT_4                 0x00004000      /* B0 Write Access Time = 4 cycles                                  */
1452 #define B0WAT_5                 0x00005000      /* B0 Write Access Time = 5 cycles                                  */
1453 #define B0WAT_6                 0x00006000      /* B0 Write Access Time = 6 cycles                                  */
1454 #define B0WAT_7                 0x00007000      /* B0 Write Access Time = 7 cycles                                  */
1455 #define B0WAT_8                 0x00008000      /* B0 Write Access Time = 8 cycles                                  */
1456 #define B0WAT_9                 0x00009000      /* B0 Write Access Time = 9 cycles                                  */
1457 #define B0WAT_10                0x0000A000      /* B0 Write Access Time = 10 cycles                                 */
1458 #define B0WAT_11                0x0000B000      /* B0 Write Access Time = 11 cycles                                 */
1459 #define B0WAT_12                0x0000C000      /* B0 Write Access Time = 12 cycles                                 */
1460 #define B0WAT_13                0x0000D000      /* B0 Write Access Time = 13 cycles                                 */
1461 #define B0WAT_14                0x0000E000      /* B0 Write Access Time = 14 cycles                                 */
1462 #define B0WAT_15                0x0000F000      /* B0 Write Access Time = 15 cycles                                 */
1463
1464 #define B1RDYEN                 0x00010000      /* Bank 1 (B1) RDY Enable                           */
1465 #define B1RDYPOL                0x00020000      /* B1 RDY Active High                               */
1466 #define B1TT_1                  0x00040000      /* B1 Transition Time (Read to Write) = 1 cycle     */
1467 #define B1TT_2                  0x00080000      /* B1 Transition Time (Read to Write) = 2 cycles    */
1468 #define B1TT_3                  0x000C0000      /* B1 Transition Time (Read to Write) = 3 cycles    */
1469 #define B1TT_4                  0x00000000      /* B1 Transition Time (Read to Write) = 4 cycles    */
1470 #define B1ST_1                  0x00100000      /* B1 Setup Time (AOE to Read/Write) = 1 cycle      */
1471 #define B1ST_2                  0x00200000      /* B1 Setup Time (AOE to Read/Write) = 2 cycles     */
1472 #define B1ST_3                  0x00300000      /* B1 Setup Time (AOE to Read/Write) = 3 cycles     */
1473 #define B1ST_4                  0x00000000      /* B1 Setup Time (AOE to Read/Write) = 4 cycles     */
1474 #define B1HT_1                  0x00400000      /* B1 Hold Time (~Read/Write to ~AOE) = 1 cycle     */
1475 #define B1HT_2                  0x00800000      /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles    */
1476 #define B1HT_3                  0x00C00000      /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles    */
1477 #define B1HT_0                  0x00000000      /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles    */
1478 #define B1RAT_1                 0x01000000      /* B1 Read Access Time = 1 cycle                                    */
1479 #define B1RAT_2                 0x02000000      /* B1 Read Access Time = 2 cycles                                   */
1480 #define B1RAT_3                 0x03000000      /* B1 Read Access Time = 3 cycles                                   */
1481 #define B1RAT_4                 0x04000000      /* B1 Read Access Time = 4 cycles                                   */
1482 #define B1RAT_5                 0x05000000      /* B1 Read Access Time = 5 cycles                                   */
1483 #define B1RAT_6                 0x06000000      /* B1 Read Access Time = 6 cycles                                   */
1484 #define B1RAT_7                 0x07000000      /* B1 Read Access Time = 7 cycles                                   */
1485 #define B1RAT_8                 0x08000000      /* B1 Read Access Time = 8 cycles                                   */
1486 #define B1RAT_9                 0x09000000      /* B1 Read Access Time = 9 cycles                                   */
1487 #define B1RAT_10                0x0A000000      /* B1 Read Access Time = 10 cycles                                  */
1488 #define B1RAT_11                0x0B000000      /* B1 Read Access Time = 11 cycles                                  */
1489 #define B1RAT_12                0x0C000000      /* B1 Read Access Time = 12 cycles                                  */
1490 #define B1RAT_13                0x0D000000      /* B1 Read Access Time = 13 cycles                                  */
1491 #define B1RAT_14                0x0E000000      /* B1 Read Access Time = 14 cycles                                  */
1492 #define B1RAT_15                0x0F000000      /* B1 Read Access Time = 15 cycles                                  */
1493 #define B1WAT_1                 0x10000000      /* B1 Write Access Time = 1 cycle                                   */
1494 #define B1WAT_2                 0x20000000      /* B1 Write Access Time = 2 cycles                                  */
1495 #define B1WAT_3                 0x30000000      /* B1 Write Access Time = 3 cycles                                  */
1496 #define B1WAT_4                 0x40000000      /* B1 Write Access Time = 4 cycles                                  */
1497 #define B1WAT_5                 0x50000000      /* B1 Write Access Time = 5 cycles                                  */
1498 #define B1WAT_6                 0x60000000      /* B1 Write Access Time = 6 cycles                                  */
1499 #define B1WAT_7                 0x70000000      /* B1 Write Access Time = 7 cycles                                  */
1500 #define B1WAT_8                 0x80000000      /* B1 Write Access Time = 8 cycles                                  */
1501 #define B1WAT_9                 0x90000000      /* B1 Write Access Time = 9 cycles                                  */
1502 #define B1WAT_10                0xA0000000      /* B1 Write Access Time = 10 cycles                                 */
1503 #define B1WAT_11                0xB0000000      /* B1 Write Access Time = 11 cycles                                 */
1504 #define B1WAT_12                0xC0000000      /* B1 Write Access Time = 12 cycles                                 */
1505 #define B1WAT_13                0xD0000000      /* B1 Write Access Time = 13 cycles                                 */
1506 #define B1WAT_14                0xE0000000      /* B1 Write Access Time = 14 cycles                                 */
1507 #define B1WAT_15                0xF0000000      /* B1 Write Access Time = 15 cycles                                 */
1508
1509 /* EBIU_AMBCTL1 Masks                                                                                                                                   */
1510 #define B2RDYEN                 0x00000001      /* Bank 2 (B2) RDY Enable                                                   */
1511 #define B2RDYPOL                0x00000002      /* B2 RDY Active High                                                               */
1512 #define B2TT_1                  0x00000004      /* B2 Transition Time (Read to Write) = 1 cycle             */
1513 #define B2TT_2                  0x00000008      /* B2 Transition Time (Read to Write) = 2 cycles    */
1514 #define B2TT_3                  0x0000000C      /* B2 Transition Time (Read to Write) = 3 cycles    */
1515 #define B2TT_4                  0x00000000      /* B2 Transition Time (Read to Write) = 4 cycles    */
1516 #define B2ST_1                  0x00000010      /* B2 Setup Time (AOE to Read/Write) = 1 cycle              */
1517 #define B2ST_2                  0x00000020      /* B2 Setup Time (AOE to Read/Write) = 2 cycles             */
1518 #define B2ST_3                  0x00000030      /* B2 Setup Time (AOE to Read/Write) = 3 cycles             */
1519 #define B2ST_4                  0x00000000      /* B2 Setup Time (AOE to Read/Write) = 4 cycles             */
1520 #define B2HT_1                  0x00000040      /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle             */
1521 #define B2HT_2                  0x00000080      /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles    */
1522 #define B2HT_3                  0x000000C0      /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles    */
1523 #define B2HT_0                  0x00000000      /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles    */
1524 #define B2RAT_1                 0x00000100      /* B2 Read Access Time = 1 cycle                                    */
1525 #define B2RAT_2                 0x00000200      /* B2 Read Access Time = 2 cycles                                   */
1526 #define B2RAT_3                 0x00000300      /* B2 Read Access Time = 3 cycles                                   */
1527 #define B2RAT_4                 0x00000400      /* B2 Read Access Time = 4 cycles                                   */
1528 #define B2RAT_5                 0x00000500      /* B2 Read Access Time = 5 cycles                                   */
1529 #define B2RAT_6                 0x00000600      /* B2 Read Access Time = 6 cycles                                   */
1530 #define B2RAT_7                 0x00000700      /* B2 Read Access Time = 7 cycles                                   */
1531 #define B2RAT_8                 0x00000800      /* B2 Read Access Time = 8 cycles                                   */
1532 #define B2RAT_9                 0x00000900      /* B2 Read Access Time = 9 cycles                                   */
1533 #define B2RAT_10                0x00000A00      /* B2 Read Access Time = 10 cycles                                  */
1534 #define B2RAT_11                0x00000B00      /* B2 Read Access Time = 11 cycles                                  */
1535 #define B2RAT_12                0x00000C00      /* B2 Read Access Time = 12 cycles                                  */
1536 #define B2RAT_13                0x00000D00      /* B2 Read Access Time = 13 cycles                                  */
1537 #define B2RAT_14                0x00000E00      /* B2 Read Access Time = 14 cycles                                  */
1538 #define B2RAT_15                0x00000F00      /* B2 Read Access Time = 15 cycles                                  */
1539 #define B2WAT_1                 0x00001000      /* B2 Write Access Time = 1 cycle                                   */
1540 #define B2WAT_2                 0x00002000      /* B2 Write Access Time = 2 cycles                                  */
1541 #define B2WAT_3                 0x00003000      /* B2 Write Access Time = 3 cycles                                  */
1542 #define B2WAT_4                 0x00004000      /* B2 Write Access Time = 4 cycles                                  */
1543 #define B2WAT_5                 0x00005000      /* B2 Write Access Time = 5 cycles                                  */
1544 #define B2WAT_6                 0x00006000      /* B2 Write Access Time = 6 cycles                                  */
1545 #define B2WAT_7                 0x00007000      /* B2 Write Access Time = 7 cycles                                  */
1546 #define B2WAT_8                 0x00008000      /* B2 Write Access Time = 8 cycles                                  */
1547 #define B2WAT_9                 0x00009000      /* B2 Write Access Time = 9 cycles                                  */
1548 #define B2WAT_10                0x0000A000      /* B2 Write Access Time = 10 cycles                                 */
1549 #define B2WAT_11                0x0000B000      /* B2 Write Access Time = 11 cycles                                 */
1550 #define B2WAT_12                0x0000C000      /* B2 Write Access Time = 12 cycles                                 */
1551 #define B2WAT_13                0x0000D000      /* B2 Write Access Time = 13 cycles                                 */
1552 #define B2WAT_14                0x0000E000      /* B2 Write Access Time = 14 cycles                                 */
1553 #define B2WAT_15                0x0000F000      /* B2 Write Access Time = 15 cycles                                 */
1554
1555 #define B3RDYEN                 0x00010000      /* Bank 3 (B3) RDY Enable                                                   */
1556 #define B3RDYPOL                0x00020000      /* B3 RDY Active High                                                               */
1557 #define B3TT_1                  0x00040000      /* B3 Transition Time (Read to Write) = 1 cycle             */
1558 #define B3TT_2                  0x00080000      /* B3 Transition Time (Read to Write) = 2 cycles    */
1559 #define B3TT_3                  0x000C0000      /* B3 Transition Time (Read to Write) = 3 cycles    */
1560 #define B3TT_4                  0x00000000      /* B3 Transition Time (Read to Write) = 4 cycles    */
1561 #define B3ST_1                  0x00100000      /* B3 Setup Time (AOE to Read/Write) = 1 cycle              */
1562 #define B3ST_2                  0x00200000      /* B3 Setup Time (AOE to Read/Write) = 2 cycles             */
1563 #define B3ST_3                  0x00300000      /* B3 Setup Time (AOE to Read/Write) = 3 cycles             */
1564 #define B3ST_4                  0x00000000      /* B3 Setup Time (AOE to Read/Write) = 4 cycles             */
1565 #define B3HT_1                  0x00400000      /* B3 Hold Time (~Read/Write to ~AOE) = 1 cycle             */
1566 #define B3HT_2                  0x00800000      /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles    */
1567 #define B3HT_3                  0x00C00000      /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles    */
1568 #define B3HT_0                  0x00000000      /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles    */
1569 #define B3RAT_1                 0x01000000      /* B3 Read Access Time = 1 cycle                                    */
1570 #define B3RAT_2                 0x02000000      /* B3 Read Access Time = 2 cycles                                   */
1571 #define B3RAT_3                 0x03000000      /* B3 Read Access Time = 3 cycles                                   */
1572 #define B3RAT_4                 0x04000000      /* B3 Read Access Time = 4 cycles                                   */
1573 #define B3RAT_5                 0x05000000      /* B3 Read Access Time = 5 cycles                                   */
1574 #define B3RAT_6                 0x06000000      /* B3 Read Access Time = 6 cycles                                   */
1575 #define B3RAT_7                 0x07000000      /* B3 Read Access Time = 7 cycles                                   */
1576 #define B3RAT_8                 0x08000000      /* B3 Read Access Time = 8 cycles                                   */
1577 #define B3RAT_9                 0x09000000      /* B3 Read Access Time = 9 cycles                                   */
1578 #define B3RAT_10                0x0A000000      /* B3 Read Access Time = 10 cycles                                  */
1579 #define B3RAT_11                0x0B000000      /* B3 Read Access Time = 11 cycles                                  */
1580 #define B3RAT_12                0x0C000000      /* B3 Read Access Time = 12 cycles                                  */
1581 #define B3RAT_13                0x0D000000      /* B3 Read Access Time = 13 cycles                                  */
1582 #define B3RAT_14                0x0E000000      /* B3 Read Access Time = 14 cycles                                  */
1583 #define B3RAT_15                0x0F000000      /* B3 Read Access Time = 15 cycles                                  */
1584 #define B3WAT_1                 0x10000000      /* B3 Write Access Time = 1 cycle                                   */
1585 #define B3WAT_2                 0x20000000      /* B3 Write Access Time = 2 cycles                                  */
1586 #define B3WAT_3                 0x30000000      /* B3 Write Access Time = 3 cycles                                  */
1587 #define B3WAT_4                 0x40000000      /* B3 Write Access Time = 4 cycles                                  */
1588 #define B3WAT_5                 0x50000000      /* B3 Write Access Time = 5 cycles                                  */
1589 #define B3WAT_6                 0x60000000      /* B3 Write Access Time = 6 cycles                                  */
1590 #define B3WAT_7                 0x70000000      /* B3 Write Access Time = 7 cycles                                  */
1591 #define B3WAT_8                 0x80000000      /* B3 Write Access Time = 8 cycles                                  */
1592 #define B3WAT_9                 0x90000000      /* B3 Write Access Time = 9 cycles                                  */
1593 #define B3WAT_10                0xA0000000      /* B3 Write Access Time = 10 cycles                                 */
1594 #define B3WAT_11                0xB0000000      /* B3 Write Access Time = 11 cycles                                 */
1595 #define B3WAT_12                0xC0000000      /* B3 Write Access Time = 12 cycles                                 */
1596 #define B3WAT_13                0xD0000000      /* B3 Write Access Time = 13 cycles                                 */
1597 #define B3WAT_14                0xE0000000      /* B3 Write Access Time = 14 cycles                                 */
1598 #define B3WAT_15                0xF0000000      /* B3 Write Access Time = 15 cycles                                 */
1599
1600 /* **********************  SDRAM CONTROLLER MASKS  **********************************************/
1601 /* EBIU_SDGCTL Masks                                                                                                                                                    */
1602 #define SCTLE                   0x00000001      /* Enable SDRAM Signals                                                                         */
1603 #define CL_2                    0x00000008      /* SDRAM CAS Latency = 2 cycles                                                         */
1604 #define CL_3                    0x0000000C      /* SDRAM CAS Latency = 3 cycles                                                         */
1605 #define PASR_ALL                0x00000000      /* All 4 SDRAM Banks Refreshed In Self-Refresh                          */
1606 #define PASR_B0_B1              0x00000010      /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh            */
1607 #define PASR_B0                 0x00000020      /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh                       */
1608 #define TRAS_1                  0x00000040      /* SDRAM tRAS = 1 cycle                                                                         */
1609 #define TRAS_2                  0x00000080      /* SDRAM tRAS = 2 cycles                                                                        */
1610 #define TRAS_3                  0x000000C0      /* SDRAM tRAS = 3 cycles                                                                        */
1611 #define TRAS_4                  0x00000100      /* SDRAM tRAS = 4 cycles                                                                        */
1612 #define TRAS_5                  0x00000140      /* SDRAM tRAS = 5 cycles                                                                        */
1613 #define TRAS_6                  0x00000180      /* SDRAM tRAS = 6 cycles                                                                        */
1614 #define TRAS_7                  0x000001C0      /* SDRAM tRAS = 7 cycles                                                                        */
1615 #define TRAS_8                  0x00000200      /* SDRAM tRAS = 8 cycles                                                                        */
1616 #define TRAS_9                  0x00000240      /* SDRAM tRAS = 9 cycles                                                                        */
1617 #define TRAS_10                 0x00000280      /* SDRAM tRAS = 10 cycles                                                                       */
1618 #define TRAS_11                 0x000002C0      /* SDRAM tRAS = 11 cycles                                                                       */
1619 #define TRAS_12                 0x00000300      /* SDRAM tRAS = 12 cycles                                                                       */
1620 #define TRAS_13                 0x00000340      /* SDRAM tRAS = 13 cycles                                                                       */
1621 #define TRAS_14                 0x00000380      /* SDRAM tRAS = 14 cycles                                                                       */
1622 #define TRAS_15                 0x000003C0      /* SDRAM tRAS = 15 cycles                                                                       */
1623 #define TRP_1                   0x00000800      /* SDRAM tRP = 1 cycle                                                                          */
1624 #define TRP_2                   0x00001000      /* SDRAM tRP = 2 cycles                                                                         */
1625 #define TRP_3                   0x00001800      /* SDRAM tRP = 3 cycles                                                                         */
1626 #define TRP_4                   0x00002000      /* SDRAM tRP = 4 cycles                                                                         */
1627 #define TRP_5                   0x00002800      /* SDRAM tRP = 5 cycles                                                                         */
1628 #define TRP_6                   0x00003000      /* SDRAM tRP = 6 cycles                                                                         */
1629 #define TRP_7                   0x00003800      /* SDRAM tRP = 7 cycles                                                                         */
1630 #define TRCD_1                  0x00008000      /* SDRAM tRCD = 1 cycle                                                                         */
1631 #define TRCD_2                  0x00010000      /* SDRAM tRCD = 2 cycles                                                                        */
1632 #define TRCD_3                  0x00018000      /* SDRAM tRCD = 3 cycles                                                                        */
1633 #define TRCD_4                  0x00020000      /* SDRAM tRCD = 4 cycles                                                                        */
1634 #define TRCD_5                  0x00028000      /* SDRAM tRCD = 5 cycles                                                                        */
1635 #define TRCD_6                  0x00030000      /* SDRAM tRCD = 6 cycles                                                                        */
1636 #define TRCD_7                  0x00038000      /* SDRAM tRCD = 7 cycles                                                                        */
1637 #define TWR_1                   0x00080000      /* SDRAM tWR = 1 cycle                                                                          */
1638 #define TWR_2                   0x00100000      /* SDRAM tWR = 2 cycles                                                                         */
1639 #define TWR_3                   0x00180000      /* SDRAM tWR = 3 cycles                                                                         */
1640 #define PUPSD                   0x00200000      /* Power-Up Start Delay (15 SCLK Cycles Delay)                          */
1641 #define PSM                             0x00400000      /* Power-Up Sequence (Mode Register Before/After* Refresh)      */
1642 #define PSS                             0x00800000      /* Enable Power-Up Sequence on Next SDRAM Access                        */
1643 #define SRFS                    0x01000000      /* Enable SDRAM Self-Refresh Mode                                                       */
1644 #define EBUFE                   0x02000000      /* Enable External Buffering Timing                                                     */
1645 #define FBBRW                   0x04000000      /* Enable Fast Back-To-Back Read To Write                                       */
1646 #define EMREN                   0x10000000      /* Extended Mode Register Enable                                                        */
1647 #define TCSR                    0x20000000      /* Temp-Compensated Self-Refresh Value (85/45* Deg C)           */
1648 #define CDDBG                   0x40000000      /* Tristate SDRAM Controls During Bus Grant                                     */
1649
1650 /* EBIU_SDBCTL Masks                                                                                                                                            */
1651 #define EBE                             0x0001  /* Enable SDRAM External Bank                                                   */
1652 #define EBSZ_16                 0x0000  /* SDRAM External Bank Size = 16MB                                              */
1653 #define EBSZ_32                 0x0002  /* SDRAM External Bank Size = 32MB                                              */
1654 #define EBSZ_64                 0x0004  /* SDRAM External Bank Size = 64MB                                              */
1655 #define EBSZ_128                0x0006  /* SDRAM External Bank Size = 128MB                                             */
1656 #define EBSZ_256                0x0008          /* SDRAM External Bank Size = 256MB     */
1657 #define EBSZ_512                0x000A          /* SDRAM External Bank Size = 512MB             */
1658 #define EBCAW_8                 0x0000  /* SDRAM External Bank Column Address Width = 8 Bits    */
1659 #define EBCAW_9                 0x0010  /* SDRAM External Bank Column Address Width = 9 Bits    */
1660 #define EBCAW_10                0x0020  /* SDRAM External Bank Column Address Width = 10 Bits   */
1661 #define EBCAW_11                0x0030  /* SDRAM External Bank Column Address Width = 11 Bits   */
1662
1663 /* EBIU_SDSTAT Masks                                                                                                            */
1664 #define SDCI                    0x0001  /* SDRAM Controller Idle                                */
1665 #define SDSRA                   0x0002  /* SDRAM Self-Refresh Active                    */
1666 #define SDPUA                   0x0004  /* SDRAM Power-Up Active                                */
1667 #define SDRS                    0x0008  /* SDRAM Will Power-Up On Next Access   */
1668 #define SDEASE                  0x0010  /* SDRAM EAB Sticky Error Status                */
1669 #define BGSTAT                  0x0020  /* Bus Grant Status                                             */
1670
1671 /* **************************  DMA CONTROLLER MASKS  ********************************/
1672 /* DMAx_CONFIG, MDMA_yy_CONFIG Masks                                                                                            */
1673 #define DMAEN                   0x0001  /* DMA Channel Enable                                                   */
1674 #define WNR                             0x0002  /* Channel Direction (W/R*)                                             */
1675 #define WDSIZE_8                0x0000  /* Transfer Word Size = 8                                               */
1676 #define WDSIZE_16               0x0004  /* Transfer Word Size = 16                                              */
1677 #define WDSIZE_32               0x0008  /* Transfer Word Size = 32                                              */
1678 #define DMA2D                   0x0010  /* DMA Mode (2D/1D*)                                                    */
1679 #define RESTART                 0x0020  /* DMA Buffer Clear                                                             */
1680 #define DI_SEL                  0x0040  /* Data Interrupt Timing Select                                 */
1681 #define DI_EN                   0x0080  /* Data Interrupt Enable                                                */
1682 #define NDSIZE_0                0x0000  /* Next Descriptor Size = 0 (Stop/Autobuffer)   */
1683 #define NDSIZE_1                0x0100  /* Next Descriptor Size = 1                                             */
1684 #define NDSIZE_2                0x0200  /* Next Descriptor Size = 2                                             */
1685 #define NDSIZE_3                0x0300  /* Next Descriptor Size = 3                                             */
1686 #define NDSIZE_4                0x0400  /* Next Descriptor Size = 4                                             */
1687 #define NDSIZE_5                0x0500  /* Next Descriptor Size = 5                                             */
1688 #define NDSIZE_6                0x0600  /* Next Descriptor Size = 6                                             */
1689 #define NDSIZE_7                0x0700  /* Next Descriptor Size = 7                                             */
1690 #define NDSIZE_8                0x0800  /* Next Descriptor Size = 8                                             */
1691 #define NDSIZE_9                0x0900  /* Next Descriptor Size = 9                                             */
1692 #define NDSIZE                  0x0900  /* Next Descriptor Size */
1693
1694 #define DMAFLOW                 0x7000  /* Flow Control */
1695 #define DMAFLOW_STOP            0x0000  /* Stop Mode */
1696 #define DMAFLOW_AUTO            0x1000  /* Autobuffer Mode */
1697 #define DMAFLOW_ARRAY           0x4000  /* Descriptor Array Mode */
1698 #define DMAFLOW_SMALL           0x6000  /* Small Model Descriptor List Mode */
1699 #define DMAFLOW_LARGE           0x7000  /* Large Model Descriptor List Mode */
1700
1701 /* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks                                                            */
1702 #define CTYPE                   0x0040  /* DMA Channel Type Indicator (Memory/Peripheral*)      */
1703 #define PMAP                    0xF000  /* Peripheral Mapped To This Channel                            */
1704 #define PMAP_PPI                0x0000  /*              PPI Port DMA                                                            */
1705 #define PMAP_EMACRX             0x1000  /*              Ethernet Receive DMA                                            */
1706 #define PMAP_EMACTX             0x2000  /*              Ethernet Transmit DMA                                           */
1707 #define PMAP_SPORT0RX   0x3000  /*              SPORT0 Receive DMA                                                      */
1708 #define PMAP_SPORT0TX   0x4000  /*              SPORT0 Transmit DMA                                                     */
1709 #define PMAP_SPORT1RX   0x5000  /*              SPORT1 Receive DMA                                                      */
1710 #define PMAP_SPORT1TX   0x6000  /*              SPORT1 Transmit DMA                                                     */
1711 #define PMAP_SPI                0x7000  /*              SPI Port DMA                                                            */
1712 #define PMAP_UART0RX    0x8000  /*              UART0 Port Receive DMA                                          */
1713 #define PMAP_UART0TX    0x9000  /*              UART0 Port Transmit DMA                                         */
1714 #define PMAP_UART1RX    0xA000  /*              UART1 Port Receive DMA                                          */
1715 #define PMAP_UART1TX    0xB000  /*              UART1 Port Transmit DMA                                         */
1716
1717 /* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks                                            */
1718 #define DMA_DONE                0x0001  /* DMA Completion Interrupt Status      */
1719 #define DMA_ERR                 0x0002  /* DMA Error Interrupt Status           */
1720 #define DFETCH                  0x0004  /* DMA Descriptor Fetch Indicator       */
1721 #define DMA_RUN                 0x0008  /* DMA Channel Running Indicator        */
1722
1723 /*  ************  PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/
1724 /*  PPI_CONTROL Masks                                                                                                   */
1725 #define PORT_EN                 0x0001  /* PPI Port Enable                                      */
1726 #define PORT_DIR                0x0002  /* PPI Port Direction                           */
1727 #define XFR_TYPE                0x000C  /* PPI Transfer Type                            */
1728 #define PORT_CFG                0x0030  /* PPI Port Configuration                       */
1729 #define FLD_SEL                 0x0040  /* PPI Active Field Select                      */
1730 #define PACK_EN                 0x0080  /* PPI Packing Mode                                     */
1731 #define DMA32                   0x0100  /* PPI 32-bit DMA Enable                        */
1732 #define SKIP_EN                 0x0200  /* PPI Skip Element Enable                      */
1733 #define SKIP_EO                 0x0400  /* PPI Skip Even/Odd Elements           */
1734 #define DLENGTH         0x3800  /* PPI Data Length  */
1735 #define DLEN_8                  0x0000  /* Data Length = 8 Bits                         */
1736 #define DLEN_10                 0x0800  /* Data Length = 10 Bits                        */
1737 #define DLEN_11                 0x1000  /* Data Length = 11 Bits                        */
1738 #define DLEN_12                 0x1800  /* Data Length = 12 Bits                        */
1739 #define DLEN_13                 0x2000  /* Data Length = 13 Bits                        */
1740 #define DLEN_14                 0x2800  /* Data Length = 14 Bits                        */
1741 #define DLEN_15                 0x3000  /* Data Length = 15 Bits                        */
1742 #define DLEN_16                 0x3800  /* Data Length = 16 Bits                        */
1743 #define POLC                    0x4000  /* PPI Clock Polarity                           */
1744 #define POLS                    0x8000  /* PPI Frame Sync Polarity                      */
1745
1746 /* PPI_STATUS Masks                                                                                                             */
1747 #define FLD                             0x0400  /* Field Indicator                                      */
1748 #define FT_ERR                  0x0800  /* Frame Track Error                            */
1749 #define OVR                             0x1000  /* FIFO Overflow Error                          */
1750 #define UNDR                    0x2000  /* FIFO Underrun Error                          */
1751 #define ERR_DET                 0x4000  /* Error Detected Indicator                     */
1752 #define ERR_NCOR                0x8000  /* Error Not Corrected Indicator        */
1753
1754 /*  ********************  TWO-WIRE INTERFACE (TWI) MASKS  ***********************/
1755 /* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y);  )                                */
1756 #define CLKLOW(x)       ((x) & 0xFF)    /* Periods Clock Is Held Low                    */
1757 #define CLKHI(y)        (((y)&0xFF)<<0x8)       /* Periods Before New Clock Low                 */
1758
1759 /* TWI_PRESCALE Masks                                                                                                                   */
1760 #define PRESCALE        0x007F  /* SCLKs Per Internal Time Reference (10MHz)    */
1761 #define TWI_ENA         0x0080  /* TWI Enable                                                                   */
1762 #define SCCB            0x0200  /* SCCB Compatibility Enable                                    */
1763
1764 /* TWI_SLAVE_CTRL Masks                                                                                                                 */
1765 #define SEN                     0x0001  /* Slave Enable                                                                 */
1766 #define SADD_LEN        0x0002  /* Slave Address Length                                                 */
1767 #define STDVAL          0x0004  /* Slave Transmit Data Valid                                    */
1768 #define NAK                     0x0008  /* NAK/ACK* Generated At Conclusion Of Transfer */
1769 #define GEN                     0x0010  /* General Call Adrress Matching Enabled                */
1770
1771 /* TWI_SLAVE_STAT Masks                                                                                                                 */
1772 #define SDIR            0x0001  /* Slave Transfer Direction (Transmit/Receive*) */
1773 #define GCALL           0x0002  /* General Call Indicator                                               */
1774
1775 /* TWI_MASTER_CTRL Masks                                                                                                        */
1776 #define MEN                     0x0001  /* Master Mode Enable                                           */
1777 #define MADD_LEN        0x0002  /* Master Address Length                                        */
1778 #define MDIR            0x0004  /* Master Transmit Direction (RX/TX*)           */
1779 #define FAST            0x0008  /* Use Fast Mode Timing Specs                           */
1780 #define STOP            0x0010  /* Issue Stop Condition                                         */
1781 #define RSTART          0x0020  /* Repeat Start or Stop* At End Of Transfer     */
1782 #define DCNT            0x3FC0  /* Data Bytes To Transfer                                       */
1783 #define SDAOVR          0x4000  /* Serial Data Override                                         */
1784 #define SCLOVR          0x8000  /* Serial Clock Override                                        */
1785
1786 /* TWI_MASTER_STAT Masks                                                                                                                */
1787 #define MPROG           0x0001  /* Master Transfer In Progress                                  */
1788 #define LOSTARB         0x0002  /* Lost Arbitration Indicator (Xfer Aborted)    */
1789 #define ANAK            0x0004  /* Address Not Acknowledged                                             */
1790 #define DNAK            0x0008  /* Data Not Acknowledged                                                */
1791 #define BUFRDERR        0x0010  /* Buffer Read Error                                                    */
1792 #define BUFWRERR        0x0020  /* Buffer Write Error                                                   */
1793 #define SDASEN          0x0040  /* Serial Data Sense                                                    */
1794 #define SCLSEN          0x0080  /* Serial Clock Sense                                                   */
1795 #define BUSBUSY         0x0100  /* Bus Busy Indicator                                                   */
1796
1797 /* TWI_INT_SRC and TWI_INT_ENABLE Masks                                         */
1798 #define SINIT           0x0001  /* Slave Transfer Initiated     */
1799 #define SCOMP           0x0002  /* Slave Transfer Complete      */
1800 #define SERR            0x0004  /* Slave Transfer Error         */
1801 #define SOVF            0x0008  /* Slave Overflow                       */
1802 #define MCOMP           0x0010  /* Master Transfer Complete     */
1803 #define MERR            0x0020  /* Master Transfer Error        */
1804 #define XMTSERV         0x0040  /* Transmit FIFO Service        */
1805 #define RCVSERV         0x0080  /* Receive FIFO Service         */
1806
1807 /* TWI_FIFO_CTRL Masks                                                                                          */
1808 #define XMTFLUSH        0x0001  /* Transmit Buffer Flush                        */
1809 #define RCVFLUSH        0x0002  /* Receive Buffer Flush                         */
1810 #define XMTINTLEN       0x0004  /* Transmit Buffer Interrupt Length     */
1811 #define RCVINTLEN       0x0008  /* Receive Buffer Interrupt Length      */
1812
1813 /* TWI_FIFO_STAT Masks                                                                                                                  */
1814 #define XMTSTAT         0x0003  /* Transmit FIFO Status                                                 */
1815 #define XMT_EMPTY       0x0000  /*              Transmit FIFO Empty                                        &nbs