Blackfin: drop unused MMR defines that only cause bad code to be written
[linux-2.6.git] / arch / blackfin / mach-bf537 / include / mach / blackfin.h
1 /*
2  * File:         include/asm-blackfin/mach-bf537/blackfin.h
3  * Based on:
4  * Author:
5  *
6  * Created:
7  * Description:
8  *
9  * Rev:
10  *
11  * Modified:
12  *
13  *
14  * Bugs:         Enter bugs at http://blackfin.uclinux.org/
15  *
16  * This program is free software; you can redistribute it and/or modify
17  * it under the terms of the GNU General Public License as published by
18  * the Free Software Foundation; either version 2, or (at your option)
19  * any later version.
20  *
21  * This program is distributed in the hope that it will be useful,
22  * but WITHOUT ANY WARRANTY; without even the implied warranty of
23  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
24  * GNU General Public License for more details.
25  *
26  * You should have received a copy of the GNU General Public License
27  * along with this program; see the file COPYING.
28  * If not, write to the Free Software Foundation,
29  * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30  */
31
32 #ifndef _MACH_BLACKFIN_H_
33 #define _MACH_BLACKFIN_H_
34
35 #define BF537_FAMILY
36
37 #include "bf537.h"
38 #include "defBF534.h"
39 #include "anomaly.h"
40
41 #if defined(CONFIG_BF537) || defined(CONFIG_BF536)
42 #include "defBF537.h"
43 #endif
44
45 #if !defined(__ASSEMBLY__)
46 #include "cdefBF534.h"
47
48 #if defined(CONFIG_BF537) || defined(CONFIG_BF536)
49 #include "cdefBF537.h"
50 #endif
51 #endif
52
53 #define BFIN_UART_NR_PORTS      2
54
55 #define OFFSET_THR              0x00    /* Transmit Holding register            */
56 #define OFFSET_RBR              0x00    /* Receive Buffer register              */
57 #define OFFSET_DLL              0x00    /* Divisor Latch (Low-Byte)             */
58 #define OFFSET_IER              0x04    /* Interrupt Enable Register            */
59 #define OFFSET_DLH              0x04    /* Divisor Latch (High-Byte)            */
60 #define OFFSET_IIR              0x08    /* Interrupt Identification Register    */
61 #define OFFSET_LCR              0x0C    /* Line Control Register                */
62 #define OFFSET_MCR              0x10    /* Modem Control Register               */
63 #define OFFSET_LSR              0x14    /* Line Status Register                 */
64 #define OFFSET_MSR              0x18    /* Modem Status Register                */
65 #define OFFSET_SCR              0x1C    /* SCR Scratch Register                 */
66 #define OFFSET_GCTL             0x24    /* Global Control Register              */
67
68 /* PLL_DIV Masks                                                                                                        */
69 #define CCLK_DIV1 CSEL_DIV1     /*          CCLK = VCO / 1                                  */
70 #define CCLK_DIV2 CSEL_DIV2     /*          CCLK = VCO / 2                                  */
71 #define CCLK_DIV4 CSEL_DIV4     /*          CCLK = VCO / 4                                  */
72 #define CCLK_DIV8 CSEL_DIV8     /*          CCLK = VCO / 8                                  */
73
74 #endif