Add "run_scheduled_work()" workqueue function
[linux-2.6.git] / arch / avr32 / mach-at32ap / at32ap7000.c
1 /*
2  * Copyright (C) 2005-2006 Atmel Corporation
3  *
4  * This program is free software; you can redistribute it and/or modify
5  * it under the terms of the GNU General Public License version 2 as
6  * published by the Free Software Foundation.
7  */
8 #include <linux/clk.h>
9 #include <linux/init.h>
10 #include <linux/platform_device.h>
11
12 #include <asm/io.h>
13
14 #include <asm/arch/board.h>
15 #include <asm/arch/portmux.h>
16 #include <asm/arch/sm.h>
17
18 #include "clock.h"
19 #include "pio.h"
20 #include "sm.h"
21
22 #define PBMEM(base)                                     \
23         {                                               \
24                 .start          = base,                 \
25                 .end            = base + 0x3ff,         \
26                 .flags          = IORESOURCE_MEM,       \
27         }
28 #define IRQ(num)                                        \
29         {                                               \
30                 .start          = num,                  \
31                 .end            = num,                  \
32                 .flags          = IORESOURCE_IRQ,       \
33         }
34 #define NAMED_IRQ(num, _name)                           \
35         {                                               \
36                 .start          = num,                  \
37                 .end            = num,                  \
38                 .name           = _name,                \
39                 .flags          = IORESOURCE_IRQ,       \
40         }
41
42 #define DEFINE_DEV(_name, _id)                                  \
43 static struct platform_device _name##_id##_device = {           \
44         .name           = #_name,                               \
45         .id             = _id,                                  \
46         .resource       = _name##_id##_resource,                \
47         .num_resources  = ARRAY_SIZE(_name##_id##_resource),    \
48 }
49 #define DEFINE_DEV_DATA(_name, _id)                             \
50 static struct platform_device _name##_id##_device = {           \
51         .name           = #_name,                               \
52         .id             = _id,                                  \
53         .dev            = {                                     \
54                 .platform_data  = &_name##_id##_data,           \
55         },                                                      \
56         .resource       = _name##_id##_resource,                \
57         .num_resources  = ARRAY_SIZE(_name##_id##_resource),    \
58 }
59
60 #define DEV_CLK(_name, devname, bus, _index)                    \
61 static struct clk devname##_##_name = {                         \
62         .name           = #_name,                               \
63         .dev            = &devname##_device.dev,                \
64         .parent         = &bus##_clk,                           \
65         .mode           = bus##_clk_mode,                       \
66         .get_rate       = bus##_clk_get_rate,                   \
67         .index          = _index,                               \
68 }
69
70 enum {
71         PIOA,
72         PIOB,
73         PIOC,
74         PIOD,
75 };
76
77 enum {
78         FUNC_A,
79         FUNC_B,
80 };
81
82 unsigned long at32ap7000_osc_rates[3] = {
83         [0] = 32768,
84         /* FIXME: these are ATSTK1002-specific */
85         [1] = 20000000,
86         [2] = 12000000,
87 };
88
89 static unsigned long osc_get_rate(struct clk *clk)
90 {
91         return at32ap7000_osc_rates[clk->index];
92 }
93
94 static unsigned long pll_get_rate(struct clk *clk, unsigned long control)
95 {
96         unsigned long div, mul, rate;
97
98         if (!(control & SM_BIT(PLLEN)))
99                 return 0;
100
101         div = SM_BFEXT(PLLDIV, control) + 1;
102         mul = SM_BFEXT(PLLMUL, control) + 1;
103
104         rate = clk->parent->get_rate(clk->parent);
105         rate = (rate + div / 2) / div;
106         rate *= mul;
107
108         return rate;
109 }
110
111 static unsigned long pll0_get_rate(struct clk *clk)
112 {
113         u32 control;
114
115         control = sm_readl(&system_manager, PM_PLL0);
116
117         return pll_get_rate(clk, control);
118 }
119
120 static unsigned long pll1_get_rate(struct clk *clk)
121 {
122         u32 control;
123
124         control = sm_readl(&system_manager, PM_PLL1);
125
126         return pll_get_rate(clk, control);
127 }
128
129 /*
130  * The AT32AP7000 has five primary clock sources: One 32kHz
131  * oscillator, two crystal oscillators and two PLLs.
132  */
133 static struct clk osc32k = {
134         .name           = "osc32k",
135         .get_rate       = osc_get_rate,
136         .users          = 1,
137         .index          = 0,
138 };
139 static struct clk osc0 = {
140         .name           = "osc0",
141         .get_rate       = osc_get_rate,
142         .users          = 1,
143         .index          = 1,
144 };
145 static struct clk osc1 = {
146         .name           = "osc1",
147         .get_rate       = osc_get_rate,
148         .index          = 2,
149 };
150 static struct clk pll0 = {
151         .name           = "pll0",
152         .get_rate       = pll0_get_rate,
153         .parent         = &osc0,
154 };
155 static struct clk pll1 = {
156         .name           = "pll1",
157         .get_rate       = pll1_get_rate,
158         .parent         = &osc0,
159 };
160
161 /*
162  * The main clock can be either osc0 or pll0.  The boot loader may
163  * have chosen one for us, so we don't really know which one until we
164  * have a look at the SM.
165  */
166 static struct clk *main_clock;
167
168 /*
169  * Synchronous clocks are generated from the main clock. The clocks
170  * must satisfy the constraint
171  *   fCPU >= fHSB >= fPB
172  * i.e. each clock must not be faster than its parent.
173  */
174 static unsigned long bus_clk_get_rate(struct clk *clk, unsigned int shift)
175 {
176         return main_clock->get_rate(main_clock) >> shift;
177 };
178
179 static void cpu_clk_mode(struct clk *clk, int enabled)
180 {
181         struct at32_sm *sm = &system_manager;
182         unsigned long flags;
183         u32 mask;
184
185         spin_lock_irqsave(&sm->lock, flags);
186         mask = sm_readl(sm, PM_CPU_MASK);
187         if (enabled)
188                 mask |= 1 << clk->index;
189         else
190                 mask &= ~(1 << clk->index);
191         sm_writel(sm, PM_CPU_MASK, mask);
192         spin_unlock_irqrestore(&sm->lock, flags);
193 }
194
195 static unsigned long cpu_clk_get_rate(struct clk *clk)
196 {
197         unsigned long cksel, shift = 0;
198
199         cksel = sm_readl(&system_manager, PM_CKSEL);
200         if (cksel & SM_BIT(CPUDIV))
201                 shift = SM_BFEXT(CPUSEL, cksel) + 1;
202
203         return bus_clk_get_rate(clk, shift);
204 }
205
206 static void hsb_clk_mode(struct clk *clk, int enabled)
207 {
208         struct at32_sm *sm = &system_manager;
209         unsigned long flags;
210         u32 mask;
211
212         spin_lock_irqsave(&sm->lock, flags);
213         mask = sm_readl(sm, PM_HSB_MASK);
214         if (enabled)
215                 mask |= 1 << clk->index;
216         else
217                 mask &= ~(1 << clk->index);
218         sm_writel(sm, PM_HSB_MASK, mask);
219         spin_unlock_irqrestore(&sm->lock, flags);
220 }
221
222 static unsigned long hsb_clk_get_rate(struct clk *clk)
223 {
224         unsigned long cksel, shift = 0;
225
226         cksel = sm_readl(&system_manager, PM_CKSEL);
227         if (cksel & SM_BIT(HSBDIV))
228                 shift = SM_BFEXT(HSBSEL, cksel) + 1;
229
230         return bus_clk_get_rate(clk, shift);
231 }
232
233 static void pba_clk_mode(struct clk *clk, int enabled)
234 {
235         struct at32_sm *sm = &system_manager;
236         unsigned long flags;
237         u32 mask;
238
239         spin_lock_irqsave(&sm->lock, flags);
240         mask = sm_readl(sm, PM_PBA_MASK);
241         if (enabled)
242                 mask |= 1 << clk->index;
243         else
244                 mask &= ~(1 << clk->index);
245         sm_writel(sm, PM_PBA_MASK, mask);
246         spin_unlock_irqrestore(&sm->lock, flags);
247 }
248
249 static unsigned long pba_clk_get_rate(struct clk *clk)
250 {
251         unsigned long cksel, shift = 0;
252
253         cksel = sm_readl(&system_manager, PM_CKSEL);
254         if (cksel & SM_BIT(PBADIV))
255                 shift = SM_BFEXT(PBASEL, cksel) + 1;
256
257         return bus_clk_get_rate(clk, shift);
258 }
259
260 static void pbb_clk_mode(struct clk *clk, int enabled)
261 {
262         struct at32_sm *sm = &system_manager;
263         unsigned long flags;
264         u32 mask;
265
266         spin_lock_irqsave(&sm->lock, flags);
267         mask = sm_readl(sm, PM_PBB_MASK);
268         if (enabled)
269                 mask |= 1 << clk->index;
270         else
271                 mask &= ~(1 << clk->index);
272         sm_writel(sm, PM_PBB_MASK, mask);
273         spin_unlock_irqrestore(&sm->lock, flags);
274 }
275
276 static unsigned long pbb_clk_get_rate(struct clk *clk)
277 {
278         unsigned long cksel, shift = 0;
279
280         cksel = sm_readl(&system_manager, PM_CKSEL);
281         if (cksel & SM_BIT(PBBDIV))
282                 shift = SM_BFEXT(PBBSEL, cksel) + 1;
283
284         return bus_clk_get_rate(clk, shift);
285 }
286
287 static struct clk cpu_clk = {
288         .name           = "cpu",
289         .get_rate       = cpu_clk_get_rate,
290         .users          = 1,
291 };
292 static struct clk hsb_clk = {
293         .name           = "hsb",
294         .parent         = &cpu_clk,
295         .get_rate       = hsb_clk_get_rate,
296 };
297 static struct clk pba_clk = {
298         .name           = "pba",
299         .parent         = &hsb_clk,
300         .mode           = hsb_clk_mode,
301         .get_rate       = pba_clk_get_rate,
302         .index          = 1,
303 };
304 static struct clk pbb_clk = {
305         .name           = "pbb",
306         .parent         = &hsb_clk,
307         .mode           = hsb_clk_mode,
308         .get_rate       = pbb_clk_get_rate,
309         .users          = 1,
310         .index          = 2,
311 };
312
313 /* --------------------------------------------------------------------
314  *  Generic Clock operations
315  * -------------------------------------------------------------------- */
316
317 static void genclk_mode(struct clk *clk, int enabled)
318 {
319         u32 control;
320
321         BUG_ON(clk->index > 7);
322
323         control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index);
324         if (enabled)
325                 control |= SM_BIT(CEN);
326         else
327                 control &= ~SM_BIT(CEN);
328         sm_writel(&system_manager, PM_GCCTRL + 4 * clk->index, control);
329 }
330
331 static unsigned long genclk_get_rate(struct clk *clk)
332 {
333         u32 control;
334         unsigned long div = 1;
335
336         BUG_ON(clk->index > 7);
337
338         if (!clk->parent)
339                 return 0;
340
341         control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index);
342         if (control & SM_BIT(DIVEN))
343                 div = 2 * (SM_BFEXT(DIV, control) + 1);
344
345         return clk->parent->get_rate(clk->parent) / div;
346 }
347
348 static long genclk_set_rate(struct clk *clk, unsigned long rate, int apply)
349 {
350         u32 control;
351         unsigned long parent_rate, actual_rate, div;
352
353         BUG_ON(clk->index > 7);
354
355         if (!clk->parent)
356                 return 0;
357
358         parent_rate = clk->parent->get_rate(clk->parent);
359         control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index);
360
361         if (rate > 3 * parent_rate / 4) {
362                 actual_rate = parent_rate;
363                 control &= ~SM_BIT(DIVEN);
364         } else {
365                 div = (parent_rate + rate) / (2 * rate) - 1;
366                 control = SM_BFINS(DIV, div, control) | SM_BIT(DIVEN);
367                 actual_rate = parent_rate / (2 * (div + 1));
368         }
369
370         printk("clk %s: new rate %lu (actual rate %lu)\n",
371                clk->name, rate, actual_rate);
372
373         if (apply)
374                 sm_writel(&system_manager, PM_GCCTRL + 4 * clk->index,
375                           control);
376
377         return actual_rate;
378 }
379
380 int genclk_set_parent(struct clk *clk, struct clk *parent)
381 {
382         u32 control;
383
384         BUG_ON(clk->index > 7);
385
386         printk("clk %s: new parent %s (was %s)\n",
387                clk->name, parent->name,
388                clk->parent ? clk->parent->name : "(null)");
389
390         control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index);
391
392         if (parent == &osc1 || parent == &pll1)
393                 control |= SM_BIT(OSCSEL);
394         else if (parent == &osc0 || parent == &pll0)
395                 control &= ~SM_BIT(OSCSEL);
396         else
397                 return -EINVAL;
398
399         if (parent == &pll0 || parent == &pll1)
400                 control |= SM_BIT(PLLSEL);
401         else
402                 control &= ~SM_BIT(PLLSEL);
403
404         sm_writel(&system_manager, PM_GCCTRL + 4 * clk->index, control);
405         clk->parent = parent;
406
407         return 0;
408 }
409
410 /* --------------------------------------------------------------------
411  *  System peripherals
412  * -------------------------------------------------------------------- */
413 static struct resource sm_resource[] = {
414         PBMEM(0xfff00000),
415         NAMED_IRQ(19, "eim"),
416         NAMED_IRQ(20, "pm"),
417         NAMED_IRQ(21, "rtc"),
418 };
419 struct platform_device at32_sm_device = {
420         .name           = "sm",
421         .id             = 0,
422         .resource       = sm_resource,
423         .num_resources  = ARRAY_SIZE(sm_resource),
424 };
425 DEV_CLK(pclk, at32_sm, pbb, 0);
426
427 static struct resource intc0_resource[] = {
428         PBMEM(0xfff00400),
429 };
430 struct platform_device at32_intc0_device = {
431         .name           = "intc",
432         .id             = 0,
433         .resource       = intc0_resource,
434         .num_resources  = ARRAY_SIZE(intc0_resource),
435 };
436 DEV_CLK(pclk, at32_intc0, pbb, 1);
437
438 static struct clk ebi_clk = {
439         .name           = "ebi",
440         .parent         = &hsb_clk,
441         .mode           = hsb_clk_mode,
442         .get_rate       = hsb_clk_get_rate,
443         .users          = 1,
444 };
445 static struct clk hramc_clk = {
446         .name           = "hramc",
447         .parent         = &hsb_clk,
448         .mode           = hsb_clk_mode,
449         .get_rate       = hsb_clk_get_rate,
450         .users          = 1,
451 };
452
453 static struct resource smc0_resource[] = {
454         PBMEM(0xfff03400),
455 };
456 DEFINE_DEV(smc, 0);
457 DEV_CLK(pclk, smc0, pbb, 13);
458 DEV_CLK(mck, smc0, hsb, 0);
459
460 static struct platform_device pdc_device = {
461         .name           = "pdc",
462         .id             = 0,
463 };
464 DEV_CLK(hclk, pdc, hsb, 4);
465 DEV_CLK(pclk, pdc, pba, 16);
466
467 static struct clk pico_clk = {
468         .name           = "pico",
469         .parent         = &cpu_clk,
470         .mode           = cpu_clk_mode,
471         .get_rate       = cpu_clk_get_rate,
472         .users          = 1,
473 };
474
475 /* --------------------------------------------------------------------
476  *  PIO
477  * -------------------------------------------------------------------- */
478
479 static struct resource pio0_resource[] = {
480         PBMEM(0xffe02800),
481         IRQ(13),
482 };
483 DEFINE_DEV(pio, 0);
484 DEV_CLK(mck, pio0, pba, 10);
485
486 static struct resource pio1_resource[] = {
487         PBMEM(0xffe02c00),
488         IRQ(14),
489 };
490 DEFINE_DEV(pio, 1);
491 DEV_CLK(mck, pio1, pba, 11);
492
493 static struct resource pio2_resource[] = {
494         PBMEM(0xffe03000),
495         IRQ(15),
496 };
497 DEFINE_DEV(pio, 2);
498 DEV_CLK(mck, pio2, pba, 12);
499
500 static struct resource pio3_resource[] = {
501         PBMEM(0xffe03400),
502         IRQ(16),
503 };
504 DEFINE_DEV(pio, 3);
505 DEV_CLK(mck, pio3, pba, 13);
506
507 void __init at32_add_system_devices(void)
508 {
509         system_manager.eim_first_irq = NR_INTERNAL_IRQS;
510
511         platform_device_register(&at32_sm_device);
512         platform_device_register(&at32_intc0_device);
513         platform_device_register(&smc0_device);
514         platform_device_register(&pdc_device);
515
516         platform_device_register(&pio0_device);
517         platform_device_register(&pio1_device);
518         platform_device_register(&pio2_device);
519         platform_device_register(&pio3_device);
520 }
521
522 /* --------------------------------------------------------------------
523  *  USART
524  * -------------------------------------------------------------------- */
525
526 static struct atmel_uart_data atmel_usart0_data = {
527         .use_dma_tx     = 1,
528         .use_dma_rx     = 1,
529 };
530 static struct resource atmel_usart0_resource[] = {
531         PBMEM(0xffe00c00),
532         IRQ(7),
533 };
534 DEFINE_DEV_DATA(atmel_usart, 0);
535 DEV_CLK(usart, atmel_usart0, pba, 4);
536
537 static struct atmel_uart_data atmel_usart1_data = {
538         .use_dma_tx     = 1,
539         .use_dma_rx     = 1,
540 };
541 static struct resource atmel_usart1_resource[] = {
542         PBMEM(0xffe01000),
543         IRQ(7),
544 };
545 DEFINE_DEV_DATA(atmel_usart, 1);
546 DEV_CLK(usart, atmel_usart1, pba, 4);
547
548 static struct atmel_uart_data atmel_usart2_data = {
549         .use_dma_tx     = 1,
550         .use_dma_rx     = 1,
551 };
552 static struct resource atmel_usart2_resource[] = {
553         PBMEM(0xffe01400),
554         IRQ(8),
555 };
556 DEFINE_DEV_DATA(atmel_usart, 2);
557 DEV_CLK(usart, atmel_usart2, pba, 5);
558
559 static struct atmel_uart_data atmel_usart3_data = {
560         .use_dma_tx     = 1,
561         .use_dma_rx     = 1,
562 };
563 static struct resource atmel_usart3_resource[] = {
564         PBMEM(0xffe01800),
565         IRQ(9),
566 };
567 DEFINE_DEV_DATA(atmel_usart, 3);
568 DEV_CLK(usart, atmel_usart3, pba, 6);
569
570 static inline void configure_usart0_pins(void)
571 {
572         portmux_set_func(PIOA,  8, FUNC_B);     /* RXD  */
573         portmux_set_func(PIOA,  9, FUNC_B);     /* TXD  */
574 }
575
576 static inline void configure_usart1_pins(void)
577 {
578         portmux_set_func(PIOA, 17, FUNC_A);     /* RXD  */
579         portmux_set_func(PIOA, 18, FUNC_A);     /* TXD  */
580 }
581
582 static inline void configure_usart2_pins(void)
583 {
584         portmux_set_func(PIOB, 26, FUNC_B);     /* RXD  */
585         portmux_set_func(PIOB, 27, FUNC_B);     /* TXD  */
586 }
587
588 static inline void configure_usart3_pins(void)
589 {
590         portmux_set_func(PIOB, 18, FUNC_B);     /* RXD  */
591         portmux_set_func(PIOB, 17, FUNC_B);     /* TXD  */
592 }
593
594 static struct platform_device *at32_usarts[4];
595
596 void __init at32_map_usart(unsigned int hw_id, unsigned int line)
597 {
598         struct platform_device *pdev;
599
600         switch (hw_id) {
601         case 0:
602                 pdev = &atmel_usart0_device;
603                 configure_usart0_pins();
604                 break;
605         case 1:
606                 pdev = &atmel_usart1_device;
607                 configure_usart1_pins();
608                 break;
609         case 2:
610                 pdev = &atmel_usart2_device;
611                 configure_usart2_pins();
612                 break;
613         case 3:
614                 pdev = &atmel_usart3_device;
615                 configure_usart3_pins();
616                 break;
617         default:
618                 return;
619         }
620
621         if (PXSEG(pdev->resource[0].start) == P4SEG) {
622                 /* Addresses in the P4 segment are permanently mapped 1:1 */
623                 struct atmel_uart_data *data = pdev->dev.platform_data;
624                 data->regs = (void __iomem *)pdev->resource[0].start;
625         }
626
627         pdev->id = line;
628         at32_usarts[line] = pdev;
629 }
630
631 struct platform_device *__init at32_add_device_usart(unsigned int id)
632 {
633         platform_device_register(at32_usarts[id]);
634         return at32_usarts[id];
635 }
636
637 struct platform_device *atmel_default_console_device;
638
639 void __init at32_setup_serial_console(unsigned int usart_id)
640 {
641         atmel_default_console_device = at32_usarts[usart_id];
642 }
643
644 /* --------------------------------------------------------------------
645  *  Ethernet
646  * -------------------------------------------------------------------- */
647
648 static struct eth_platform_data macb0_data;
649 static struct resource macb0_resource[] = {
650         PBMEM(0xfff01800),
651         IRQ(25),
652 };
653 DEFINE_DEV_DATA(macb, 0);
654 DEV_CLK(hclk, macb0, hsb, 8);
655 DEV_CLK(pclk, macb0, pbb, 6);
656
657 struct platform_device *__init
658 at32_add_device_eth(unsigned int id, struct eth_platform_data *data)
659 {
660         struct platform_device *pdev;
661
662         switch (id) {
663         case 0:
664                 pdev = &macb0_device;
665
666                 portmux_set_func(PIOC,  3, FUNC_A);     /* TXD0 */
667                 portmux_set_func(PIOC,  4, FUNC_A);     /* TXD1 */
668                 portmux_set_func(PIOC,  7, FUNC_A);     /* TXEN */
669                 portmux_set_func(PIOC,  8, FUNC_A);     /* TXCK */
670                 portmux_set_func(PIOC,  9, FUNC_A);     /* RXD0 */
671                 portmux_set_func(PIOC, 10, FUNC_A);     /* RXD1 */
672                 portmux_set_func(PIOC, 13, FUNC_A);     /* RXER */
673                 portmux_set_func(PIOC, 15, FUNC_A);     /* RXDV */
674                 portmux_set_func(PIOC, 16, FUNC_A);     /* MDC  */
675                 portmux_set_func(PIOC, 17, FUNC_A);     /* MDIO */
676
677                 if (!data->is_rmii) {
678                         portmux_set_func(PIOC,  0, FUNC_A);     /* COL  */
679                         portmux_set_func(PIOC,  1, FUNC_A);     /* CRS  */
680                         portmux_set_func(PIOC,  2, FUNC_A);     /* TXER */
681                         portmux_set_func(PIOC,  5, FUNC_A);     /* TXD2 */
682                         portmux_set_func(PIOC,  6, FUNC_A);     /* TXD3 */
683                         portmux_set_func(PIOC, 11, FUNC_A);     /* RXD2 */
684                         portmux_set_func(PIOC, 12, FUNC_A);     /* RXD3 */
685                         portmux_set_func(PIOC, 14, FUNC_A);     /* RXCK */
686                         portmux_set_func(PIOC, 18, FUNC_A);     /* SPD  */
687                 }
688                 break;
689
690         default:
691                 return NULL;
692         }
693
694         memcpy(pdev->dev.platform_data, data, sizeof(struct eth_platform_data));
695         platform_device_register(pdev);
696
697         return pdev;
698 }
699
700 /* --------------------------------------------------------------------
701  *  SPI
702  * -------------------------------------------------------------------- */
703 static struct resource spi0_resource[] = {
704         PBMEM(0xffe00000),
705         IRQ(3),
706 };
707 DEFINE_DEV(spi, 0);
708 DEV_CLK(mck, spi0, pba, 0);
709
710 struct platform_device *__init at32_add_device_spi(unsigned int id)
711 {
712         struct platform_device *pdev;
713
714         switch (id) {
715         case 0:
716                 pdev = &spi0_device;
717                 portmux_set_func(PIOA,  0, FUNC_A);     /* MISO  */
718                 portmux_set_func(PIOA,  1, FUNC_A);     /* MOSI  */
719                 portmux_set_func(PIOA,  2, FUNC_A);     /* SCK   */
720                 portmux_set_func(PIOA,  3, FUNC_A);     /* NPCS0 */
721                 portmux_set_func(PIOA,  4, FUNC_A);     /* NPCS1 */
722                 portmux_set_func(PIOA,  5, FUNC_A);     /* NPCS2 */
723                 break;
724
725         default:
726                 return NULL;
727         }
728
729         platform_device_register(pdev);
730         return pdev;
731 }
732
733 /* --------------------------------------------------------------------
734  *  LCDC
735  * -------------------------------------------------------------------- */
736 static struct lcdc_platform_data lcdc0_data;
737 static struct resource lcdc0_resource[] = {
738         {
739                 .start          = 0xff000000,
740                 .end            = 0xff000fff,
741                 .flags          = IORESOURCE_MEM,
742         },
743         IRQ(1),
744 };
745 DEFINE_DEV_DATA(lcdc, 0);
746 DEV_CLK(hclk, lcdc0, hsb, 7);
747 static struct clk lcdc0_pixclk = {
748         .name           = "pixclk",
749         .dev            = &lcdc0_device.dev,
750         .mode           = genclk_mode,
751         .get_rate       = genclk_get_rate,
752         .set_rate       = genclk_set_rate,
753         .set_parent     = genclk_set_parent,
754         .index          = 7,
755 };
756
757 struct platform_device *__init
758 at32_add_device_lcdc(unsigned int id, struct lcdc_platform_data *data)
759 {
760         struct platform_device *pdev;
761
762         switch (id) {
763         case 0:
764                 pdev = &lcdc0_device;
765                 portmux_set_func(PIOC, 19, FUNC_A);     /* CC     */
766                 portmux_set_func(PIOC, 20, FUNC_A);     /* HSYNC  */
767                 portmux_set_func(PIOC, 21, FUNC_A);     /* PCLK   */
768                 portmux_set_func(PIOC, 22, FUNC_A);     /* VSYNC  */
769                 portmux_set_func(PIOC, 23, FUNC_A);     /* DVAL   */
770                 portmux_set_func(PIOC, 24, FUNC_A);     /* MODE   */
771                 portmux_set_func(PIOC, 25, FUNC_A);     /* PWR    */
772                 portmux_set_func(PIOC, 26, FUNC_A);     /* DATA0  */
773                 portmux_set_func(PIOC, 27, FUNC_A);     /* DATA1  */
774                 portmux_set_func(PIOC, 28, FUNC_A);     /* DATA2  */
775                 portmux_set_func(PIOC, 29, FUNC_A);     /* DATA3  */
776                 portmux_set_func(PIOC, 30, FUNC_A);     /* DATA4  */
777                 portmux_set_func(PIOC, 31, FUNC_A);     /* DATA5  */
778                 portmux_set_func(PIOD,  0, FUNC_A);     /* DATA6  */
779                 portmux_set_func(PIOD,  1, FUNC_A);     /* DATA7  */
780                 portmux_set_func(PIOD,  2, FUNC_A);     /* DATA8  */
781                 portmux_set_func(PIOD,  3, FUNC_A);     /* DATA9  */
782                 portmux_set_func(PIOD,  4, FUNC_A);     /* DATA10 */
783                 portmux_set_func(PIOD,  5, FUNC_A);     /* DATA11 */
784                 portmux_set_func(PIOD,  6, FUNC_A);     /* DATA12 */
785                 portmux_set_func(PIOD,  7, FUNC_A);     /* DATA13 */
786                 portmux_set_func(PIOD,  8, FUNC_A);     /* DATA14 */
787                 portmux_set_func(PIOD,  9, FUNC_A);     /* DATA15 */
788                 portmux_set_func(PIOD, 10, FUNC_A);     /* DATA16 */
789                 portmux_set_func(PIOD, 11, FUNC_A);     /* DATA17 */
790                 portmux_set_func(PIOD, 12, FUNC_A);     /* DATA18 */
791                 portmux_set_func(PIOD, 13, FUNC_A);     /* DATA19 */
792                 portmux_set_func(PIOD, 14, FUNC_A);     /* DATA20 */
793                 portmux_set_func(PIOD, 15, FUNC_A);     /* DATA21 */
794                 portmux_set_func(PIOD, 16, FUNC_A);     /* DATA22 */
795                 portmux_set_func(PIOD, 17, FUNC_A);     /* DATA23 */
796
797                 clk_set_parent(&lcdc0_pixclk, &pll0);
798                 clk_set_rate(&lcdc0_pixclk, clk_get_rate(&pll0));
799                 break;
800
801         default:
802                 return NULL;
803         }
804
805         memcpy(pdev->dev.platform_data, data,
806                sizeof(struct lcdc_platform_data));
807
808         platform_device_register(pdev);
809         return pdev;
810 }
811
812 struct clk *at32_clock_list[] = {
813         &osc32k,
814         &osc0,
815         &osc1,
816         &pll0,
817         &pll1,
818         &cpu_clk,
819         &hsb_clk,
820         &pba_clk,
821         &pbb_clk,
822         &at32_sm_pclk,
823         &at32_intc0_pclk,
824         &ebi_clk,
825         &hramc_clk,
826         &smc0_pclk,
827         &smc0_mck,
828         &pdc_hclk,
829         &pdc_pclk,
830         &pico_clk,
831         &pio0_mck,
832         &pio1_mck,
833         &pio2_mck,
834         &pio3_mck,
835         &atmel_usart0_usart,
836         &atmel_usart1_usart,
837         &atmel_usart2_usart,
838         &atmel_usart3_usart,
839         &macb0_hclk,
840         &macb0_pclk,
841         &spi0_mck,
842         &lcdc0_hclk,
843         &lcdc0_pixclk,
844 };
845 unsigned int at32_nr_clocks = ARRAY_SIZE(at32_clock_list);
846
847 void __init at32_portmux_init(void)
848 {
849         at32_init_pio(&pio0_device);
850         at32_init_pio(&pio1_device);
851         at32_init_pio(&pio2_device);
852         at32_init_pio(&pio3_device);
853 }
854
855 void __init at32_clock_init(void)
856 {
857         struct at32_sm *sm = &system_manager;
858         u32 cpu_mask = 0, hsb_mask = 0, pba_mask = 0, pbb_mask = 0;
859         int i;
860
861         if (sm_readl(sm, PM_MCCTRL) & SM_BIT(PLLSEL))
862                 main_clock = &pll0;
863         else
864                 main_clock = &osc0;
865
866         if (sm_readl(sm, PM_PLL0) & SM_BIT(PLLOSC))
867                 pll0.parent = &osc1;
868         if (sm_readl(sm, PM_PLL1) & SM_BIT(PLLOSC))
869                 pll1.parent = &osc1;
870
871         /*
872          * Turn on all clocks that have at least one user already, and
873          * turn off everything else. We only do this for module
874          * clocks, and even though it isn't particularly pretty to
875          * check the address of the mode function, it should do the
876          * trick...
877          */
878         for (i = 0; i < ARRAY_SIZE(at32_clock_list); i++) {
879                 struct clk *clk = at32_clock_list[i];
880
881                 if (clk->mode == &cpu_clk_mode)
882                         cpu_mask |= 1 << clk->index;
883                 else if (clk->mode == &hsb_clk_mode)
884                         hsb_mask |= 1 << clk->index;
885                 else if (clk->mode == &pba_clk_mode)
886                         pba_mask |= 1 << clk->index;
887                 else if (clk->mode == &pbb_clk_mode)
888                         pbb_mask |= 1 << clk->index;
889         }
890
891         sm_writel(sm, PM_CPU_MASK, cpu_mask);
892         sm_writel(sm, PM_HSB_MASK, hsb_mask);
893         sm_writel(sm, PM_PBA_MASK, pba_mask);
894         sm_writel(sm, PM_PBB_MASK, pbb_mask);
895 }