ae2186892c85f9728e1cfdee07861412281ae0f4
[linux-2.6.git] / arch / arm / mach-omap2 / serial.c
1 /*
2  * arch/arm/mach-omap2/serial.c
3  *
4  * OMAP2 serial support.
5  *
6  * Copyright (C) 2005-2008 Nokia Corporation
7  * Author: Paul Mundt <paul.mundt@nokia.com>
8  *
9  * Major rework for PM support by Kevin Hilman
10  *
11  * Based off of arch/arm/mach-omap/omap1/serial.c
12  *
13  * Copyright (C) 2009 Texas Instruments
14  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com
15  *
16  * This file is subject to the terms and conditions of the GNU General Public
17  * License. See the file "COPYING" in the main directory of this archive
18  * for more details.
19  */
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/serial_8250.h>
23 #include <linux/serial_reg.h>
24 #include <linux/clk.h>
25 #include <linux/io.h>
26
27 #include <mach/common.h>
28 #include <mach/board.h>
29 #include <mach/clock.h>
30 #include <mach/control.h>
31
32 #include "prm.h"
33 #include "pm.h"
34 #include "prm-regbits-34xx.h"
35
36 #define UART_OMAP_WER           0x17    /* Wake-up enable register */
37
38 #define DEFAULT_TIMEOUT (5 * HZ)
39
40 struct omap_uart_state {
41         int num;
42         int can_sleep;
43         struct timer_list timer;
44         u32 timeout;
45
46         void __iomem *wk_st;
47         void __iomem *wk_en;
48         u32 wk_mask;
49         u32 padconf;
50
51         struct clk *ick;
52         struct clk *fck;
53         int clocked;
54
55         struct plat_serial8250_port *p;
56         struct list_head node;
57         struct platform_device pdev;
58
59 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
60         int context_valid;
61
62         /* Registers to be saved/restored for OFF-mode */
63         u16 dll;
64         u16 dlh;
65         u16 ier;
66         u16 sysc;
67         u16 scr;
68         u16 wer;
69 #endif
70 };
71
72 static LIST_HEAD(uart_list);
73
74 static struct plat_serial8250_port serial_platform_data0[] = {
75         {
76                 .membase        = OMAP2_IO_ADDRESS(OMAP_UART1_BASE),
77                 .mapbase        = OMAP_UART1_BASE,
78                 .irq            = 72,
79                 .flags          = UPF_BOOT_AUTOCONF,
80                 .iotype         = UPIO_MEM,
81                 .regshift       = 2,
82                 .uartclk        = OMAP24XX_BASE_BAUD * 16,
83         }, {
84                 .flags          = 0
85         }
86 };
87
88 static struct plat_serial8250_port serial_platform_data1[] = {
89         {
90                 .membase        = OMAP2_IO_ADDRESS(OMAP_UART2_BASE),
91                 .mapbase        = OMAP_UART2_BASE,
92                 .irq            = 73,
93                 .flags          = UPF_BOOT_AUTOCONF,
94                 .iotype         = UPIO_MEM,
95                 .regshift       = 2,
96                 .uartclk        = OMAP24XX_BASE_BAUD * 16,
97         }, {
98                 .flags          = 0
99         }
100 };
101
102 static struct plat_serial8250_port serial_platform_data2[] = {
103         {
104                 .membase        = OMAP2_IO_ADDRESS(OMAP_UART3_BASE),
105                 .mapbase        = OMAP_UART3_BASE,
106                 .irq            = 74,
107                 .flags          = UPF_BOOT_AUTOCONF,
108                 .iotype         = UPIO_MEM,
109                 .regshift       = 2,
110                 .uartclk        = OMAP24XX_BASE_BAUD * 16,
111         }, {
112 #ifdef CONFIG_ARCH_OMAP4
113                 .membase        = OMAP2_IO_ADDRESS(OMAP_UART4_BASE),
114                 .mapbase        = OMAP_UART4_BASE,
115                 .irq            = 70,
116                 .flags          = UPF_BOOT_AUTOCONF,
117                 .iotype         = UPIO_MEM,
118                 .regshift       = 2,
119                 .uartclk        = OMAP24XX_BASE_BAUD * 16,
120         }, {
121 #endif
122                 .flags          = 0
123         }
124 };
125
126 #ifdef CONFIG_ARCH_OMAP4
127 static struct plat_serial8250_port serial_platform_data3[] = {
128         {
129                 .membase        = OMAP2_IO_ADDRESS(OMAP_UART4_BASE),
130                 .mapbase        = OMAP_UART4_BASE,
131                 .irq            = 70,
132                 .flags          = UPF_BOOT_AUTOCONF,
133                 .iotype         = UPIO_MEM,
134                 .regshift       = 2,
135                 .uartclk        = OMAP24XX_BASE_BAUD * 16,
136         }, {
137                 .flags          = 0
138         }
139 };
140 #endif
141 static inline unsigned int serial_read_reg(struct plat_serial8250_port *up,
142                                            int offset)
143 {
144         offset <<= up->regshift;
145         return (unsigned int)__raw_readb(up->membase + offset);
146 }
147
148 static inline void serial_write_reg(struct plat_serial8250_port *p, int offset,
149                                     int value)
150 {
151         offset <<= p->regshift;
152         __raw_writeb(value, p->membase + offset);
153 }
154
155 /*
156  * Internal UARTs need to be initialized for the 8250 autoconfig to work
157  * properly. Note that the TX watermark initialization may not be needed
158  * once the 8250.c watermark handling code is merged.
159  */
160 static inline void __init omap_uart_reset(struct omap_uart_state *uart)
161 {
162         struct plat_serial8250_port *p = uart->p;
163
164         serial_write_reg(p, UART_OMAP_MDR1, 0x07);
165         serial_write_reg(p, UART_OMAP_SCR, 0x08);
166         serial_write_reg(p, UART_OMAP_MDR1, 0x00);
167         serial_write_reg(p, UART_OMAP_SYSC, (0x02 << 3) | (1 << 2) | (1 << 0));
168 }
169
170 #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
171
172 static int enable_off_mode; /* to be removed by full off-mode patches */
173
174 static void omap_uart_save_context(struct omap_uart_state *uart)
175 {
176         u16 lcr = 0;
177         struct plat_serial8250_port *p = uart->p;
178
179         if (!enable_off_mode)
180                 return;
181
182         lcr = serial_read_reg(p, UART_LCR);
183         serial_write_reg(p, UART_LCR, 0xBF);
184         uart->dll = serial_read_reg(p, UART_DLL);
185         uart->dlh = serial_read_reg(p, UART_DLM);
186         serial_write_reg(p, UART_LCR, lcr);
187         uart->ier = serial_read_reg(p, UART_IER);
188         uart->sysc = serial_read_reg(p, UART_OMAP_SYSC);
189         uart->scr = serial_read_reg(p, UART_OMAP_SCR);
190         uart->wer = serial_read_reg(p, UART_OMAP_WER);
191
192         uart->context_valid = 1;
193 }
194
195 static void omap_uart_restore_context(struct omap_uart_state *uart)
196 {
197         u16 efr = 0;
198         struct plat_serial8250_port *p = uart->p;
199
200         if (!enable_off_mode)
201                 return;
202
203         if (!uart->context_valid)
204                 return;
205
206         uart->context_valid = 0;
207
208         serial_write_reg(p, UART_OMAP_MDR1, 0x7);
209         serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
210         efr = serial_read_reg(p, UART_EFR);
211         serial_write_reg(p, UART_EFR, UART_EFR_ECB);
212         serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */
213         serial_write_reg(p, UART_IER, 0x0);
214         serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
215         serial_write_reg(p, UART_DLL, uart->dll);
216         serial_write_reg(p, UART_DLM, uart->dlh);
217         serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */
218         serial_write_reg(p, UART_IER, uart->ier);
219         serial_write_reg(p, UART_FCR, 0xA1);
220         serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
221         serial_write_reg(p, UART_EFR, efr);
222         serial_write_reg(p, UART_LCR, UART_LCR_WLEN8);
223         serial_write_reg(p, UART_OMAP_SCR, uart->scr);
224         serial_write_reg(p, UART_OMAP_WER, uart->wer);
225         serial_write_reg(p, UART_OMAP_SYSC, uart->sysc);
226         serial_write_reg(p, UART_OMAP_MDR1, 0x00); /* UART 16x mode */
227 }
228 #else
229 static inline void omap_uart_save_context(struct omap_uart_state *uart) {}
230 static inline void omap_uart_restore_context(struct omap_uart_state *uart) {}
231 #endif /* CONFIG_PM && CONFIG_ARCH_OMAP3 */
232
233 static inline void omap_uart_enable_clocks(struct omap_uart_state *uart)
234 {
235         if (uart->clocked)
236                 return;
237
238         clk_enable(uart->ick);
239         clk_enable(uart->fck);
240         uart->clocked = 1;
241         omap_uart_restore_context(uart);
242 }
243
244 #ifdef CONFIG_PM
245
246 static inline void omap_uart_disable_clocks(struct omap_uart_state *uart)
247 {
248         if (!uart->clocked)
249                 return;
250
251         omap_uart_save_context(uart);
252         uart->clocked = 0;
253         clk_disable(uart->ick);
254         clk_disable(uart->fck);
255 }
256
257 static void omap_uart_enable_wakeup(struct omap_uart_state *uart)
258 {
259         /* Set wake-enable bit */
260         if (uart->wk_en && uart->wk_mask) {
261                 u32 v = __raw_readl(uart->wk_en);
262                 v |= uart->wk_mask;
263                 __raw_writel(v, uart->wk_en);
264         }
265
266         /* Ensure IOPAD wake-enables are set */
267         if (cpu_is_omap34xx() && uart->padconf) {
268                 u16 v = omap_ctrl_readw(uart->padconf);
269                 v |= OMAP3_PADCONF_WAKEUPENABLE0;
270                 omap_ctrl_writew(v, uart->padconf);
271         }
272 }
273
274 static void omap_uart_disable_wakeup(struct omap_uart_state *uart)
275 {
276         /* Clear wake-enable bit */
277         if (uart->wk_en && uart->wk_mask) {
278                 u32 v = __raw_readl(uart->wk_en);
279                 v &= ~uart->wk_mask;
280                 __raw_writel(v, uart->wk_en);
281         }
282
283         /* Ensure IOPAD wake-enables are cleared */
284         if (cpu_is_omap34xx() && uart->padconf) {
285                 u16 v = omap_ctrl_readw(uart->padconf);
286                 v &= ~OMAP3_PADCONF_WAKEUPENABLE0;
287                 omap_ctrl_writew(v, uart->padconf);
288         }
289 }
290
291 static void omap_uart_smart_idle_enable(struct omap_uart_state *uart,
292                                           int enable)
293 {
294         struct plat_serial8250_port *p = uart->p;
295         u16 sysc;
296
297         sysc = serial_read_reg(p, UART_OMAP_SYSC) & 0x7;
298         if (enable)
299                 sysc |= 0x2 << 3;
300         else
301                 sysc |= 0x1 << 3;
302
303         serial_write_reg(p, UART_OMAP_SYSC, sysc);
304 }
305
306 static void omap_uart_block_sleep(struct omap_uart_state *uart)
307 {
308         omap_uart_enable_clocks(uart);
309
310         omap_uart_smart_idle_enable(uart, 0);
311         uart->can_sleep = 0;
312         if (uart->timeout)
313                 mod_timer(&uart->timer, jiffies + uart->timeout);
314         else
315                 del_timer(&uart->timer);
316 }
317
318 static void omap_uart_allow_sleep(struct omap_uart_state *uart)
319 {
320         if (device_may_wakeup(&uart->pdev.dev))
321                 omap_uart_enable_wakeup(uart);
322         else
323                 omap_uart_disable_wakeup(uart);
324
325         if (!uart->clocked)
326                 return;
327
328         omap_uart_smart_idle_enable(uart, 1);
329         uart->can_sleep = 1;
330         del_timer(&uart->timer);
331 }
332
333 static void omap_uart_idle_timer(unsigned long data)
334 {
335         struct omap_uart_state *uart = (struct omap_uart_state *)data;
336
337         omap_uart_allow_sleep(uart);
338 }
339
340 void omap_uart_prepare_idle(int num)
341 {
342         struct omap_uart_state *uart;
343
344         list_for_each_entry(uart, &uart_list, node) {
345                 if (num == uart->num && uart->can_sleep) {
346                         omap_uart_disable_clocks(uart);
347                         return;
348                 }
349         }
350 }
351
352 void omap_uart_resume_idle(int num)
353 {
354         struct omap_uart_state *uart;
355
356         list_for_each_entry(uart, &uart_list, node) {
357                 if (num == uart->num) {
358                         omap_uart_enable_clocks(uart);
359
360                         /* Check for IO pad wakeup */
361                         if (cpu_is_omap34xx() && uart->padconf) {
362                                 u16 p = omap_ctrl_readw(uart->padconf);
363
364                                 if (p & OMAP3_PADCONF_WAKEUPEVENT0)
365                                         omap_uart_block_sleep(uart);
366                         }
367
368                         /* Check for normal UART wakeup */
369                         if (__raw_readl(uart->wk_st) & uart->wk_mask)
370                                 omap_uart_block_sleep(uart);
371                         return;
372                 }
373         }
374 }
375
376 void omap_uart_prepare_suspend(void)
377 {
378         struct omap_uart_state *uart;
379
380         list_for_each_entry(uart, &uart_list, node) {
381                 omap_uart_allow_sleep(uart);
382         }
383 }
384
385 int omap_uart_can_sleep(void)
386 {
387         struct omap_uart_state *uart;
388         int can_sleep = 1;
389
390         list_for_each_entry(uart, &uart_list, node) {
391                 if (!uart->clocked)
392                         continue;
393
394                 if (!uart->can_sleep) {
395                         can_sleep = 0;
396                         continue;
397                 }
398
399                 /* This UART can now safely sleep. */
400                 omap_uart_allow_sleep(uart);
401         }
402
403         return can_sleep;
404 }
405
406 /**
407  * omap_uart_interrupt()
408  *
409  * This handler is used only to detect that *any* UART interrupt has
410  * occurred.  It does _nothing_ to handle the interrupt.  Rather,
411  * any UART interrupt will trigger the inactivity timer so the
412  * UART will not idle or sleep for its timeout period.
413  *
414  **/
415 static irqreturn_t omap_uart_interrupt(int irq, void *dev_id)
416 {
417         struct omap_uart_state *uart = dev_id;
418
419         omap_uart_block_sleep(uart);
420
421         return IRQ_NONE;
422 }
423
424 static void omap_uart_idle_init(struct omap_uart_state *uart)
425 {
426         struct plat_serial8250_port *p = uart->p;
427         int ret;
428
429         uart->can_sleep = 0;
430         uart->timeout = DEFAULT_TIMEOUT;
431         setup_timer(&uart->timer, omap_uart_idle_timer,
432                     (unsigned long) uart);
433         mod_timer(&uart->timer, jiffies + uart->timeout);
434         omap_uart_smart_idle_enable(uart, 0);
435
436         if (cpu_is_omap34xx()) {
437                 u32 mod = (uart->num == 2) ? OMAP3430_PER_MOD : CORE_MOD;
438                 u32 wk_mask = 0;
439                 u32 padconf = 0;
440
441                 uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1);
442                 uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1);
443                 switch (uart->num) {
444                 case 0:
445                         wk_mask = OMAP3430_ST_UART1_MASK;
446                         padconf = 0x182;
447                         break;
448                 case 1:
449                         wk_mask = OMAP3430_ST_UART2_MASK;
450                         padconf = 0x17a;
451                         break;
452                 case 2:
453                         wk_mask = OMAP3430_ST_UART3_MASK;
454                         padconf = 0x19e;
455                         break;
456                 }
457                 uart->wk_mask = wk_mask;
458                 uart->padconf = padconf;
459         } else if (cpu_is_omap24xx()) {
460                 u32 wk_mask = 0;
461
462                 if (cpu_is_omap2430()) {
463                         uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKEN1);
464                         uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKST1);
465                 } else if (cpu_is_omap2420()) {
466                         uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKEN1);
467                         uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKST1);
468                 }
469                 switch (uart->num) {
470                 case 0:
471                         wk_mask = OMAP24XX_ST_UART1_MASK;
472                         break;
473                 case 1:
474                         wk_mask = OMAP24XX_ST_UART2_MASK;
475                         break;
476                 case 2:
477                         wk_mask = OMAP24XX_ST_UART3_MASK;
478                         break;
479                 }
480                 uart->wk_mask = wk_mask;
481         } else {
482                 uart->wk_en = 0;
483                 uart->wk_st = 0;
484                 uart->wk_mask = 0;
485                 uart->padconf = 0;
486         }
487
488         p->irqflags |= IRQF_SHARED;
489         ret = request_irq(p->irq, omap_uart_interrupt, IRQF_SHARED,
490                           "serial idle", (void *)uart);
491         WARN_ON(ret);
492 }
493
494 void omap_uart_enable_irqs(int enable)
495 {
496         int ret;
497         struct omap_uart_state *uart;
498
499         list_for_each_entry(uart, &uart_list, node) {
500                 if (enable)
501                         ret = request_irq(uart->p->irq, omap_uart_interrupt,
502                                 IRQF_SHARED, "serial idle", (void *)uart);
503                 else
504                         free_irq(uart->p->irq, (void *)uart);
505         }
506 }
507
508 static ssize_t sleep_timeout_show(struct device *dev,
509                                   struct device_attribute *attr,
510                                   char *buf)
511 {
512         struct platform_device *pdev = container_of(dev,
513                                         struct platform_device, dev);
514         struct omap_uart_state *uart = container_of(pdev,
515                                         struct omap_uart_state, pdev);
516
517         return sprintf(buf, "%u\n", uart->timeout / HZ);
518 }
519
520 static ssize_t sleep_timeout_store(struct device *dev,
521                                    struct device_attribute *attr,
522                                    const char *buf, size_t n)
523 {
524         struct platform_device *pdev = container_of(dev,
525                                         struct platform_device, dev);
526         struct omap_uart_state *uart = container_of(pdev,
527                                         struct omap_uart_state, pdev);
528         unsigned int value;
529
530         if (sscanf(buf, "%u", &value) != 1) {
531                 printk(KERN_ERR "sleep_timeout_store: Invalid value\n");
532                 return -EINVAL;
533         }
534
535         uart->timeout = value * HZ;
536         if (uart->timeout)
537                 mod_timer(&uart->timer, jiffies + uart->timeout);
538         else
539                 /* A zero value means disable timeout feature */
540                 omap_uart_block_sleep(uart);
541
542         return n;
543 }
544
545 DEVICE_ATTR(sleep_timeout, 0644, sleep_timeout_show, sleep_timeout_store);
546 #define DEV_CREATE_FILE(dev, attr) WARN_ON(device_create_file(dev, attr))
547 #else
548 static inline void omap_uart_idle_init(struct omap_uart_state *uart) {}
549 #define DEV_CREATE_FILE(dev, attr)
550 #endif /* CONFIG_PM */
551
552 static struct omap_uart_state omap_uart[OMAP_MAX_NR_PORTS] = {
553         {
554                 .pdev = {
555                         .name                   = "serial8250",
556                         .id                     = PLAT8250_DEV_PLATFORM,
557                         .dev                    = {
558                                 .platform_data  = serial_platform_data0,
559                         },
560                 },
561         }, {
562                 .pdev = {
563                         .name                   = "serial8250",
564                         .id                     = PLAT8250_DEV_PLATFORM1,
565                         .dev                    = {
566                                 .platform_data  = serial_platform_data1,
567                         },
568                 },
569         }, {
570                 .pdev = {
571                         .name                   = "serial8250",
572                         .id                     = PLAT8250_DEV_PLATFORM2,
573                         .dev                    = {
574                                 .platform_data  = serial_platform_data2,
575                         },
576                 },
577         },
578 #ifdef CONFIG_ARCH_OMAP4
579         {
580                 .pdev = {
581                         .name                   = "serial8250",
582                         .id                     = 3,
583                         .dev                    = {
584                                 .platform_data  = serial_platform_data3,
585                         },
586                 },
587         },
588 #endif
589 };
590
591 void __init omap_serial_early_init(void)
592 {
593         int i;
594         char name[16];
595
596         /*
597          * Make sure the serial ports are muxed on at this point.
598          * You have to mux them off in device drivers later on
599          * if not needed.
600          */
601
602         for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
603                 struct omap_uart_state *uart = &omap_uart[i];
604                 struct platform_device *pdev = &uart->pdev;
605                 struct device *dev = &pdev->dev;
606                 struct plat_serial8250_port *p = dev->platform_data;
607
608                 sprintf(name, "uart%d_ick", i+1);
609                 uart->ick = clk_get(NULL, name);
610                 if (IS_ERR(uart->ick)) {
611                         printk(KERN_ERR "Could not get uart%d_ick\n", i+1);
612                         uart->ick = NULL;
613                 }
614
615                 sprintf(name, "uart%d_fck", i+1);
616                 uart->fck = clk_get(NULL, name);
617                 if (IS_ERR(uart->fck)) {
618                         printk(KERN_ERR "Could not get uart%d_fck\n", i+1);
619                         uart->fck = NULL;
620                 }
621
622                 /* FIXME: Remove this once the clkdev is ready */
623                 if (!cpu_is_omap44xx()) {
624                         if (!uart->ick || !uart->fck)
625                                 continue;
626                 }
627
628                 uart->num = i;
629                 p->private_data = uart;
630                 uart->p = p;
631                 list_add_tail(&uart->node, &uart_list);
632
633                 if (cpu_is_omap44xx())
634                         p->irq += 32;
635
636                 omap_uart_enable_clocks(uart);
637         }
638 }
639
640 void __init omap_serial_init(void)
641 {
642         int i;
643
644         for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
645                 struct omap_uart_state *uart = &omap_uart[i];
646                 struct platform_device *pdev = &uart->pdev;
647                 struct device *dev = &pdev->dev;
648
649                 omap_uart_reset(uart);
650                 omap_uart_idle_init(uart);
651
652                 if (WARN_ON(platform_device_register(pdev)))
653                         continue;
654                 if ((cpu_is_omap34xx() && uart->padconf) ||
655                     (uart->wk_en && uart->wk_mask)) {
656                         device_init_wakeup(dev, true);
657                         DEV_CREATE_FILE(dev, &dev_attr_sleep_timeout);
658                 }
659         }
660 }