arch/arm/mach-omap2/clock44xx_data.c

   1 /*
   2  * OMAP4 Clock data
   3  *
   4  * Copyright (C) 2009-2010 Texas Instruments, Inc.
   5  * Copyright (C) 2009-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley (paul@pwsan.com)
   8  * Rajendra Nayak (rnayak@ti.com)
   9  * Benoit Cousson (b-cousson@ti.com)
  10  *
  11  * This file is automatically generated from the OMAP hardware databases.
  12  * We respectfully ask that any modifications to this file be coordinated
  13  * with the public linux-omap@vger.kernel.org mailing list and the
  14  * authors above to ensure that the autogeneration scripts are kept
  15  * up-to-date with the file contents.
  16  *
  17  * This program is free software; you can redistribute it and/or modify
  18  * it under the terms of the GNU General Public License version 2 as
  19  * published by the Free Software Foundation.
  20  *
  21  * XXX Some of the ES1 clocks have been removed/changed; once support
  22  * is added for discriminating clocks by ES level, these should be added back
  23  * in.
  24  */
  25
  26 #include <linux/kernel.h>
  27 #include <linux/list.h>
  28 #include <linux/clk.h>
  29 #include <plat/clkdev_omap.h>
  30
  31 #include "clock.h"
  32 #include "clock44xx.h"
  33 #include "cm1_44xx.h"
  34 #include "cm2_44xx.h"
  35 #include "cm-regbits-44xx.h"
  36 #include "prm44xx.h"
  37 #include "prm-regbits-44xx.h"
  38 #include "control.h"
  39 #include "scrm44xx.h"
  40
  41 /* OMAP4 modulemode control */
  42 #define OMAP4430_MODULEMODE_HWCTRL                      0
  43 #define OMAP4430_MODULEMODE_SWCTRL                      1
  44
  45 /* Root clocks */
  46
  47 static struct clk extalt_clkin_ck = {
  48         .name           = "extalt_clkin_ck",
  49         .rate           = 59000000,
  50         .ops            = &clkops_null,
  51 };
  52
  53 static struct clk pad_clks_ck = {
  54         .name           = "pad_clks_ck",
  55         .rate           = 12000000,
  56         .ops            = &clkops_omap2_dflt,
  57         .enable_reg     = OMAP4430_CM_CLKSEL_ABE,
  58         .enable_bit     = OMAP4430_PAD_CLKS_GATE_SHIFT,
  59 };
  60
  61 static struct clk pad_slimbus_core_clks_ck = {
  62         .name           = "pad_slimbus_core_clks_ck",
  63         .rate           = 12000000,
  64         .ops            = &clkops_null,
  65 };
  66
  67 static struct clk secure_32k_clk_src_ck = {
  68         .name           = "secure_32k_clk_src_ck",
  69         .rate           = 32768,
  70         .ops            = &clkops_null,
  71 };
  72
  73 static struct clk slimbus_clk = {
  74         .name           = "slimbus_clk",
  75         .rate           = 12000000,
  76         .ops            = &clkops_omap2_dflt,
  77         .enable_reg     = OMAP4430_CM_CLKSEL_ABE,
  78         .enable_bit     = OMAP4430_SLIMBUS_CLK_GATE_SHIFT,
  79 };
  80
  81 static struct clk sys_32k_ck = {
  82         .name           = "sys_32k_ck",
  83         .rate           = 32768,
  84         .ops            = &clkops_null,
  85 };
  86
  87 static struct clk virt_12000000_ck = {
  88         .name           = "virt_12000000_ck",
  89         .ops            = &clkops_null,
  90         .rate           = 12000000,
  91 };
  92
  93 static struct clk virt_13000000_ck = {
  94         .name           = "virt_13000000_ck",
  95         .ops            = &clkops_null,
  96         .rate           = 13000000,
  97 };
  98
  99 static struct clk virt_16800000_ck = {
 100         .name           = "virt_16800000_ck",
 101         .ops            = &clkops_null,
 102         .rate           = 16800000,
 103 };
 104
 105 static struct clk virt_19200000_ck = {
 106         .name           = "virt_19200000_ck",
 107         .ops            = &clkops_null,
 108         .rate           = 19200000,
 109 };
 110
 111 static struct clk virt_26000000_ck = {
 112         .name           = "virt_26000000_ck",
 113         .ops            = &clkops_null,
 114         .rate           = 26000000,
 115 };
 116
 117 static struct clk virt_27000000_ck = {
 118         .name           = "virt_27000000_ck",
 119         .ops            = &clkops_null,
 120         .rate           = 27000000,
 121 };
 122
 123 static struct clk virt_38400000_ck = {
 124         .name           = "virt_38400000_ck",
 125         .ops            = &clkops_null,
 126         .rate           = 38400000,
 127 };
 128
 129 static const struct clksel_rate div_1_0_rates[] = {
 130         { .div = 1, .val = 0, .flags = RATE_IN_4430 },
 131         { .div = 0 },
 132 };
 133
 134 static const struct clksel_rate div_1_1_rates[] = {
 135         { .div = 1, .val = 1, .flags = RATE_IN_4430 },
 136         { .div = 0 },
 137 };
 138
 139 static const struct clksel_rate div_1_2_rates[] = {
 140         { .div = 1, .val = 2, .flags = RATE_IN_4430 },
 141         { .div = 0 },
 142 };
 143
 144 static const struct clksel_rate div_1_3_rates[] = {
 145         { .div = 1, .val = 3, .flags = RATE_IN_4430 },
 146         { .div = 0 },
 147 };
 148
 149 static const struct clksel_rate div_1_4_rates[] = {
 150         { .div = 1, .val = 4, .flags = RATE_IN_4430 },
 151         { .div = 0 },
 152 };
 153
 154 static const struct clksel_rate div_1_5_rates[] = {
 155         { .div = 1, .val = 5, .flags = RATE_IN_4430 },
 156         { .div = 0 },
 157 };
 158
 159 static const struct clksel_rate div_1_6_rates[] = {
 160         { .div = 1, .val = 6, .flags = RATE_IN_4430 },
 161         { .div = 0 },
 162 };
 163
 164 static const struct clksel_rate div_1_7_rates[] = {
 165         { .div = 1, .val = 7, .flags = RATE_IN_4430 },
 166         { .div = 0 },
 167 };
 168
 169 static const struct clksel sys_clkin_sel[] = {
 170         { .parent = &virt_12000000_ck, .rates = div_1_1_rates },
 171         { .parent = &virt_13000000_ck, .rates = div_1_2_rates },
 172         { .parent = &virt_16800000_ck, .rates = div_1_3_rates },
 173         { .parent = &virt_19200000_ck, .rates = div_1_4_rates },
 174         { .parent = &virt_26000000_ck, .rates = div_1_5_rates },
 175         { .parent = &virt_27000000_ck, .rates = div_1_6_rates },
 176         { .parent = &virt_38400000_ck, .rates = div_1_7_rates },
 177         { .parent = NULL },
 178 };
 179
 180 static struct clk sys_clkin_ck = {
 181         .name           = "sys_clkin_ck",
 182         .rate           = 38400000,
 183         .clksel         = sys_clkin_sel,
 184         .init           = &omap2_init_clksel_parent,
 185         .clksel_reg     = OMAP4430_CM_SYS_CLKSEL,
 186         .clksel_mask    = OMAP4430_SYS_CLKSEL_MASK,
 187         .ops            = &clkops_null,
 188         .recalc         = &omap2_clksel_recalc,
 189 };
 190
 191 static struct clk tie_low_clock_ck = {
 192         .name           = "tie_low_clock_ck",
 193         .rate           = 0,
 194         .ops            = &clkops_null,
 195 };
 196
 197 static struct clk utmi_phy_clkout_ck = {
 198         .name           = "utmi_phy_clkout_ck",
 199         .rate           = 60000000,
 200         .ops            = &clkops_null,
 201 };
 202
 203 static struct clk xclk60mhsp1_ck = {
 204         .name           = "xclk60mhsp1_ck",
 205         .rate           = 60000000,
 206         .ops            = &clkops_null,
 207 };
 208
 209 static struct clk xclk60mhsp2_ck = {
 210         .name           = "xclk60mhsp2_ck",
 211         .rate           = 60000000,
 212         .ops            = &clkops_null,
 213 };
 214
 215 static struct clk xclk60motg_ck = {
 216         .name           = "xclk60motg_ck",
 217         .rate           = 60000000,
 218         .ops            = &clkops_null,
 219 };
 220
 221 /* Module clocks and DPLL outputs */
 222
 223 static const struct clksel abe_dpll_bypass_clk_mux_sel[] = {
 224         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
 225         { .parent = &sys_32k_ck, .rates = div_1_1_rates },
 226         { .parent = NULL },
 227 };
 228
 229 static struct clk abe_dpll_bypass_clk_mux_ck = {
 230         .name           = "abe_dpll_bypass_clk_mux_ck",
 231         .parent         = &sys_clkin_ck,
 232         .ops            = &clkops_null,
 233         .recalc         = &followparent_recalc,
 234 };
 235
 236 static struct clk abe_dpll_refclk_mux_ck = {
 237         .name           = "abe_dpll_refclk_mux_ck",
 238         .parent         = &sys_clkin_ck,
 239         .clksel         = abe_dpll_bypass_clk_mux_sel,
 240         .init           = &omap2_init_clksel_parent,
 241         .clksel_reg     = OMAP4430_CM_ABE_PLL_REF_CLKSEL,
 242         .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
 243         .ops            = &clkops_null,
 244         .recalc         = &omap2_clksel_recalc,
 245 };
 246
 247 /* DPLL_ABE */
 248 static struct dpll_data dpll_abe_dd = {
 249         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_ABE,
 250         .clk_bypass     = &abe_dpll_bypass_clk_mux_ck,
 251         .clk_ref        = &abe_dpll_refclk_mux_ck,
 252         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_ABE,
 253         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 254         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_ABE,
 255         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_ABE,
 256         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 257         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 258         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 259         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 260         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 261         .max_multiplier = 2047,
 262         .max_divider    = 128,
 263         .min_divider    = 1,
 264 };
 265
 266
 267 static struct clk dpll_abe_ck = {
 268         .name           = "dpll_abe_ck",
 269         .parent         = &abe_dpll_refclk_mux_ck,
 270         .dpll_data      = &dpll_abe_dd,
 271         .init           = &omap2_init_dpll_parent,
 272         .ops            = &clkops_omap3_noncore_dpll_ops,
 273         .recalc         = &omap3_dpll_recalc,
 274         .round_rate     = &omap2_dpll_round_rate,
 275         .set_rate       = &omap3_noncore_dpll_set_rate,
 276 };
 277
 278 static struct clk dpll_abe_x2_ck = {
 279         .name           = "dpll_abe_x2_ck",
 280         .parent         = &dpll_abe_ck,
 281         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_ABE,
 282         .flags          = CLOCK_CLKOUTX2,
 283         .ops            = &clkops_omap4_dpllmx_ops,
 284         .recalc         = &omap3_clkoutx2_recalc,
 285 };
 286
 287 static const struct clksel_rate div31_1to31_rates[] = {
 288         { .div = 1, .val = 1, .flags = RATE_IN_4430 },
 289         { .div = 2, .val = 2, .flags = RATE_IN_4430 },
 290         { .div = 3, .val = 3, .flags = RATE_IN_4430 },
 291         { .div = 4, .val = 4, .flags = RATE_IN_4430 },
 292         { .div = 5, .val = 5, .flags = RATE_IN_4430 },
 293         { .div = 6, .val = 6, .flags = RATE_IN_4430 },
 294         { .div = 7, .val = 7, .flags = RATE_IN_4430 },
 295         { .div = 8, .val = 8, .flags = RATE_IN_4430 },
 296         { .div = 9, .val = 9, .flags = RATE_IN_4430 },
 297         { .div = 10, .val = 10, .flags = RATE_IN_4430 },
 298         { .div = 11, .val = 11, .flags = RATE_IN_4430 },
 299         { .div = 12, .val = 12, .flags = RATE_IN_4430 },
 300         { .div = 13, .val = 13, .flags = RATE_IN_4430 },
 301         { .div = 14, .val = 14, .flags = RATE_IN_4430 },
 302         { .div = 15, .val = 15, .flags = RATE_IN_4430 },
 303         { .div = 16, .val = 16, .flags = RATE_IN_4430 },
 304         { .div = 17, .val = 17, .flags = RATE_IN_4430 },
 305         { .div = 18, .val = 18, .flags = RATE_IN_4430 },
 306         { .div = 19, .val = 19, .flags = RATE_IN_4430 },
 307         { .div = 20, .val = 20, .flags = RATE_IN_4430 },
 308         { .div = 21, .val = 21, .flags = RATE_IN_4430 },
 309         { .div = 22, .val = 22, .flags = RATE_IN_4430 },
 310         { .div = 23, .val = 23, .flags = RATE_IN_4430 },
 311         { .div = 24, .val = 24, .flags = RATE_IN_4430 },
 312         { .div = 25, .val = 25, .flags = RATE_IN_4430 },
 313         { .div = 26, .val = 26, .flags = RATE_IN_4430 },
 314         { .div = 27, .val = 27, .flags = RATE_IN_4430 },
 315         { .div = 28, .val = 28, .flags = RATE_IN_4430 },
 316         { .div = 29, .val = 29, .flags = RATE_IN_4430 },
 317         { .div = 30, .val = 30, .flags = RATE_IN_4430 },
 318         { .div = 31, .val = 31, .flags = RATE_IN_4430 },
 319         { .div = 0 },
 320 };
 321
 322 static const struct clksel dpll_abe_m2x2_div[] = {
 323         { .parent = &dpll_abe_x2_ck, .rates = div31_1to31_rates },
 324         { .parent = NULL },
 325 };
 326
 327 static struct clk dpll_abe_m2x2_ck = {
 328         .name           = "dpll_abe_m2x2_ck",
 329         .parent         = &dpll_abe_x2_ck,
 330         .clksel         = dpll_abe_m2x2_div,
 331         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_ABE,
 332         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
 333         .ops            = &clkops_omap4_dpllmx_ops,
 334         .recalc         = &omap2_clksel_recalc,
 335         .round_rate     = &omap2_clksel_round_rate,
 336         .set_rate       = &omap2_clksel_set_rate,
 337 };
 338
 339 static struct clk abe_24m_fclk = {
 340         .name           = "abe_24m_fclk",
 341         .parent         = &dpll_abe_m2x2_ck,
 342         .ops            = &clkops_null,
 343         .fixed_div      = 8,
 344         .recalc         = &omap_fixed_divisor_recalc,
 345 };
 346
 347 static const struct clksel_rate div3_1to4_rates[] = {
 348         { .div = 1, .val = 0, .flags = RATE_IN_4430 },
 349         { .div = 2, .val = 1, .flags = RATE_IN_4430 },
 350         { .div = 4, .val = 2, .flags = RATE_IN_4430 },
 351         { .div = 0 },
 352 };
 353
 354 static const struct clksel abe_clk_div[] = {
 355         { .parent = &dpll_abe_m2x2_ck, .rates = div3_1to4_rates },
 356         { .parent = NULL },
 357 };
 358
 359 static struct clk abe_clk = {
 360         .name           = "abe_clk",
 361         .parent         = &dpll_abe_m2x2_ck,
 362         .clksel         = abe_clk_div,
 363         .clksel_reg     = OMAP4430_CM_CLKSEL_ABE,
 364         .clksel_mask    = OMAP4430_CLKSEL_OPP_MASK,
 365         .ops            = &clkops_null,
 366         .recalc         = &omap2_clksel_recalc,
 367         .round_rate     = &omap2_clksel_round_rate,
 368         .set_rate       = &omap2_clksel_set_rate,
 369 };
 370
 371 static const struct clksel_rate div2_1to2_rates[] = {
 372         { .div = 1, .val = 0, .flags = RATE_IN_4430 },
 373         { .div = 2, .val = 1, .flags = RATE_IN_4430 },
 374         { .div = 0 },
 375 };
 376
 377 static const struct clksel aess_fclk_div[] = {
 378         { .parent = &abe_clk, .rates = div2_1to2_rates },
 379         { .parent = NULL },
 380 };
 381
 382 static struct clk aess_fclk = {
 383         .name           = "aess_fclk",
 384         .parent         = &abe_clk,
 385         .clksel         = aess_fclk_div,
 386         .clksel_reg     = OMAP4430_CM1_ABE_AESS_CLKCTRL,
 387         .clksel_mask    = OMAP4430_CLKSEL_AESS_FCLK_MASK,
 388         .ops            = &clkops_null,
 389         .recalc         = &omap2_clksel_recalc,
 390         .round_rate     = &omap2_clksel_round_rate,
 391         .set_rate       = &omap2_clksel_set_rate,
 392 };
 393
 394 static struct clk dpll_abe_m3x2_ck = {
 395         .name           = "dpll_abe_m3x2_ck",
 396         .parent         = &dpll_abe_x2_ck,
 397         .clksel         = dpll_abe_m2x2_div,
 398         .clksel_reg     = OMAP4430_CM_DIV_M3_DPLL_ABE,
 399         .clksel_mask    = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
 400         .ops            = &clkops_omap4_dpllmx_ops,
 401         .recalc         = &omap2_clksel_recalc,
 402         .round_rate     = &omap2_clksel_round_rate,
 403         .set_rate       = &omap2_clksel_set_rate,
 404 };
 405
 406 static const struct clksel core_hsd_byp_clk_mux_sel[] = {
 407         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
 408         { .parent = &dpll_abe_m3x2_ck, .rates = div_1_1_rates },
 409         { .parent = NULL },
 410 };
 411
 412 static struct clk core_hsd_byp_clk_mux_ck = {
 413         .name           = "core_hsd_byp_clk_mux_ck",
 414         .parent         = &sys_clkin_ck,
 415         .clksel         = core_hsd_byp_clk_mux_sel,
 416         .init           = &omap2_init_clksel_parent,
 417         .clksel_reg     = OMAP4430_CM_CLKSEL_DPLL_CORE,
 418         .clksel_mask    = OMAP4430_DPLL_BYP_CLKSEL_MASK,
 419         .ops            = &clkops_null,
 420         .recalc         = &omap2_clksel_recalc,
 421 };
 422
 423 /* DPLL_CORE */
 424 static struct dpll_data dpll_core_dd = {
 425         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_CORE,
 426         .clk_bypass     = &core_hsd_byp_clk_mux_ck,
 427         .clk_ref        = &sys_clkin_ck,
 428         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_CORE,
 429         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 430         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_CORE,
 431         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_CORE,
 432         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 433         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 434         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 435         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 436         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 437         .max_multiplier = 2047,
 438         .max_divider    = 128,
 439         .min_divider    = 1,
 440 };
 441
 442
 443 static struct clk dpll_core_ck = {
 444         .name           = "dpll_core_ck",
 445         .parent         = &sys_clkin_ck,
 446         .dpll_data      = &dpll_core_dd,
 447         .init           = &omap2_init_dpll_parent,
 448         .ops            = &clkops_omap3_core_dpll_ops,
 449         .recalc         = &omap3_dpll_recalc,
 450 };
 451
 452 static struct clk dpll_core_x2_ck = {
 453         .name           = "dpll_core_x2_ck",
 454         .parent         = &dpll_core_ck,
 455         .flags          = CLOCK_CLKOUTX2,
 456         .ops            = &clkops_null,
 457         .recalc         = &omap3_clkoutx2_recalc,
 458 };
 459
 460 static const struct clksel dpll_core_m6x2_div[] = {
 461         { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
 462         { .parent = NULL },
 463 };
 464
 465 static struct clk dpll_core_m6x2_ck = {
 466         .name           = "dpll_core_m6x2_ck",
 467         .parent         = &dpll_core_x2_ck,
 468         .clksel         = dpll_core_m6x2_div,
 469         .clksel_reg     = OMAP4430_CM_DIV_M6_DPLL_CORE,
 470         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
 471         .ops            = &clkops_omap4_dpllmx_ops,
 472         .recalc         = &omap2_clksel_recalc,
 473         .round_rate     = &omap2_clksel_round_rate,
 474         .set_rate       = &omap2_clksel_set_rate,
 475 };
 476
 477 static const struct clksel dbgclk_mux_sel[] = {
 478         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
 479         { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates },
 480         { .parent = NULL },
 481 };
 482
 483 static struct clk dbgclk_mux_ck = {
 484         .name           = "dbgclk_mux_ck",
 485         .parent         = &sys_clkin_ck,
 486         .ops            = &clkops_null,
 487         .recalc         = &followparent_recalc,
 488 };
 489
 490 static const struct clksel dpll_core_m2_div[] = {
 491         { .parent = &dpll_core_ck, .rates = div31_1to31_rates },
 492         { .parent = NULL },
 493 };
 494
 495 static struct clk dpll_core_m2_ck = {
 496         .name           = "dpll_core_m2_ck",
 497         .parent         = &dpll_core_ck,
 498         .clksel         = dpll_core_m2_div,
 499         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_CORE,
 500         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
 501         .ops            = &clkops_omap4_dpllmx_ops,
 502         .recalc         = &omap2_clksel_recalc,
 503         .round_rate     = &omap2_clksel_round_rate,
 504         .set_rate       = &omap2_clksel_set_rate,
 505 };
 506
 507 static struct clk ddrphy_ck = {
 508         .name           = "ddrphy_ck",
 509         .parent         = &dpll_core_m2_ck,
 510         .ops            = &clkops_null,
 511         .fixed_div      = 2,
 512         .recalc         = &omap_fixed_divisor_recalc,
 513 };
 514
 515 static struct clk dpll_core_m5x2_ck = {
 516         .name           = "dpll_core_m5x2_ck",
 517         .parent         = &dpll_core_x2_ck,
 518         .clksel         = dpll_core_m6x2_div,
 519         .clksel_reg     = OMAP4430_CM_DIV_M5_DPLL_CORE,
 520         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
 521         .ops            = &clkops_omap4_dpllmx_ops,
 522         .recalc         = &omap2_clksel_recalc,
 523         .round_rate     = &omap2_clksel_round_rate,
 524         .set_rate       = &omap2_clksel_set_rate,
 525 };
 526
 527 static const struct clksel div_core_div[] = {
 528         { .parent = &dpll_core_m5x2_ck, .rates = div2_1to2_rates },
 529         { .parent = NULL },
 530 };
 531
 532 static struct clk div_core_ck = {
 533         .name           = "div_core_ck",
 534         .parent         = &dpll_core_m5x2_ck,
 535         .clksel         = div_core_div,
 536         .clksel_reg     = OMAP4430_CM_CLKSEL_CORE,
 537         .clksel_mask    = OMAP4430_CLKSEL_CORE_MASK,
 538         .ops            = &clkops_null,
 539         .recalc         = &omap2_clksel_recalc,
 540         .round_rate     = &omap2_clksel_round_rate,
 541         .set_rate       = &omap2_clksel_set_rate,
 542 };
 543
 544 static const struct clksel_rate div4_1to8_rates[] = {
 545         { .div = 1, .val = 0, .flags = RATE_IN_4430 },
 546         { .div = 2, .val = 1, .flags = RATE_IN_4430 },
 547         { .div = 4, .val = 2, .flags = RATE_IN_4430 },
 548         { .div = 8, .val = 3, .flags = RATE_IN_4430 },
 549         { .div = 0 },
 550 };
 551
 552 static const struct clksel div_iva_hs_clk_div[] = {
 553         { .parent = &dpll_core_m5x2_ck, .rates = div4_1to8_rates },
 554         { .parent = NULL },
 555 };
 556
 557 static struct clk div_iva_hs_clk = {
 558         .name           = "div_iva_hs_clk",
 559         .parent         = &dpll_core_m5x2_ck,
 560         .clksel         = div_iva_hs_clk_div,
 561         .clksel_reg     = OMAP4430_CM_BYPCLK_DPLL_IVA,
 562         .clksel_mask    = OMAP4430_CLKSEL_0_1_MASK,
 563         .ops            = &clkops_null,
 564         .recalc         = &omap2_clksel_recalc,
 565         .round_rate     = &omap2_clksel_round_rate,
 566         .set_rate       = &omap2_clksel_set_rate,
 567 };
 568
 569 static struct clk div_mpu_hs_clk = {
 570         .name           = "div_mpu_hs_clk",
 571         .parent         = &dpll_core_m5x2_ck,
 572         .clksel         = div_iva_hs_clk_div,
 573         .clksel_reg     = OMAP4430_CM_BYPCLK_DPLL_MPU,
 574         .clksel_mask    = OMAP4430_CLKSEL_0_1_MASK,
 575         .ops            = &clkops_null,
 576         .recalc         = &omap2_clksel_recalc,
 577         .round_rate     = &omap2_clksel_round_rate,
 578         .set_rate       = &omap2_clksel_set_rate,
 579 };
 580
 581 static struct clk dpll_core_m4x2_ck = {
 582         .name           = "dpll_core_m4x2_ck",
 583         .parent         = &dpll_core_x2_ck,
 584         .clksel         = dpll_core_m6x2_div,
 585         .clksel_reg     = OMAP4430_CM_DIV_M4_DPLL_CORE,
 586         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
 587         .ops            = &clkops_omap4_dpllmx_ops,
 588         .recalc         = &omap2_clksel_recalc,
 589         .round_rate     = &omap2_clksel_round_rate,
 590         .set_rate       = &omap2_clksel_set_rate,
 591 };
 592
 593 static struct clk dll_clk_div_ck = {
 594         .name           = "dll_clk_div_ck",
 595         .parent         = &dpll_core_m4x2_ck,
 596         .ops            = &clkops_null,
 597         .fixed_div      = 2,
 598         .recalc         = &omap_fixed_divisor_recalc,
 599 };
 600
 601 static const struct clksel dpll_abe_m2_div[] = {
 602         { .parent = &dpll_abe_ck, .rates = div31_1to31_rates },
 603         { .parent = NULL },
 604 };
 605
 606 static struct clk dpll_abe_m2_ck = {
 607         .name           = "dpll_abe_m2_ck",
 608         .parent         = &dpll_abe_ck,
 609         .clksel         = dpll_abe_m2_div,
 610         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_ABE,
 611         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
 612         .ops            = &clkops_omap4_dpllmx_ops,
 613         .recalc         = &omap2_clksel_recalc,
 614         .round_rate     = &omap2_clksel_round_rate,
 615         .set_rate       = &omap2_clksel_set_rate,
 616 };
 617
 618 static struct clk dpll_core_m3x2_ck = {
 619         .name           = "dpll_core_m3x2_ck",
 620         .parent         = &dpll_core_x2_ck,
 621         .clksel         = dpll_core_m6x2_div,
 622         .clksel_reg     = OMAP4430_CM_DIV_M3_DPLL_CORE,
 623         .clksel_mask    = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
 624         .ops            = &clkops_omap2_dflt,
 625         .recalc         = &omap2_clksel_recalc,
 626         .round_rate     = &omap2_clksel_round_rate,
 627         .set_rate       = &omap2_clksel_set_rate,
 628         .enable_reg     = OMAP4430_CM_DIV_M3_DPLL_CORE,
 629         .enable_bit     = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
 630 };
 631
 632 static struct clk dpll_core_m7x2_ck = {
 633         .name           = "dpll_core_m7x2_ck",
 634         .parent         = &dpll_core_x2_ck,
 635         .clksel         = dpll_core_m6x2_div,
 636         .clksel_reg     = OMAP4430_CM_DIV_M7_DPLL_CORE,
 637         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
 638         .ops            = &clkops_omap4_dpllmx_ops,
 639         .recalc         = &omap2_clksel_recalc,
 640         .round_rate     = &omap2_clksel_round_rate,
 641         .set_rate       = &omap2_clksel_set_rate,
 642 };
 643
 644 static const struct clksel iva_hsd_byp_clk_mux_sel[] = {
 645         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
 646         { .parent = &div_iva_hs_clk, .rates = div_1_1_rates },
 647         { .parent = NULL },
 648 };
 649
 650 static struct clk iva_hsd_byp_clk_mux_ck = {
 651         .name           = "iva_hsd_byp_clk_mux_ck",
 652         .parent         = &sys_clkin_ck,
 653         .clksel         = iva_hsd_byp_clk_mux_sel,
 654         .init           = &omap2_init_clksel_parent,
 655         .clksel_reg     = OMAP4430_CM_CLKSEL_DPLL_IVA,
 656         .clksel_mask    = OMAP4430_DPLL_BYP_CLKSEL_MASK,
 657         .ops            = &clkops_null,
 658         .recalc         = &omap2_clksel_recalc,
 659 };
 660
 661 /* DPLL_IVA */
 662 static struct dpll_data dpll_iva_dd = {
 663         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_IVA,
 664         .clk_bypass     = &iva_hsd_byp_clk_mux_ck,
 665         .clk_ref        = &sys_clkin_ck,
 666         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_IVA,
 667         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 668         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_IVA,
 669         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_IVA,
 670         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 671         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 672         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 673         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 674         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 675         .max_multiplier = 2047,
 676         .max_divider    = 128,
 677         .min_divider    = 1,
 678 };
 679
 680
 681 static struct clk dpll_iva_ck = {
 682         .name           = "dpll_iva_ck",
 683         .parent         = &sys_clkin_ck,
 684         .dpll_data      = &dpll_iva_dd,
 685         .init           = &omap2_init_dpll_parent,
 686         .ops            = &clkops_omap3_noncore_dpll_ops,
 687         .recalc         = &omap3_dpll_recalc,
 688         .round_rate     = &omap2_dpll_round_rate,
 689         .set_rate       = &omap3_noncore_dpll_set_rate,
 690 };
 691
 692 static struct clk dpll_iva_x2_ck = {
 693         .name           = "dpll_iva_x2_ck",
 694         .parent         = &dpll_iva_ck,
 695         .flags          = CLOCK_CLKOUTX2,
 696         .ops            = &clkops_null,
 697         .recalc         = &omap3_clkoutx2_recalc,
 698 };
 699
 700 static const struct clksel dpll_iva_m4x2_div[] = {
 701         { .parent = &dpll_iva_x2_ck, .rates = div31_1to31_rates },
 702         { .parent = NULL },
 703 };
 704
 705 static struct clk dpll_iva_m4x2_ck = {
 706         .name           = "dpll_iva_m4x2_ck",
 707         .parent         = &dpll_iva_x2_ck,
 708         .clksel         = dpll_iva_m4x2_div,
 709         .clksel_reg     = OMAP4430_CM_DIV_M4_DPLL_IVA,
 710         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
 711         .ops            = &clkops_omap4_dpllmx_ops,
 712         .recalc         = &omap2_clksel_recalc,
 713         .round_rate     = &omap2_clksel_round_rate,
 714         .set_rate       = &omap2_clksel_set_rate,
 715 };
 716
 717 static struct clk dpll_iva_m5x2_ck = {
 718         .name           = "dpll_iva_m5x2_ck",
 719         .parent         = &dpll_iva_x2_ck,
 720         .clksel         = dpll_iva_m4x2_div,
 721         .clksel_reg     = OMAP4430_CM_DIV_M5_DPLL_IVA,
 722         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
 723         .ops            = &clkops_omap4_dpllmx_ops,
 724         .recalc         = &omap2_clksel_recalc,
 725         .round_rate     = &omap2_clksel_round_rate,
 726         .set_rate       = &omap2_clksel_set_rate,
 727 };
 728
 729 /* DPLL_MPU */
 730 static struct dpll_data dpll_mpu_dd = {
 731         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_MPU,
 732         .clk_bypass     = &div_mpu_hs_clk,
 733         .clk_ref        = &sys_clkin_ck,
 734         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_MPU,
 735         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 736         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_MPU,
 737         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_MPU,
 738         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 739         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 740         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 741         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 742         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 743         .max_multiplier = 2047,
 744         .max_divider    = 128,
 745         .min_divider    = 1,
 746 };
 747
 748
 749 static struct clk dpll_mpu_ck = {
 750         .name           = "dpll_mpu_ck",
 751         .parent         = &sys_clkin_ck,
 752         .dpll_data      = &dpll_mpu_dd,
 753         .init           = &omap2_init_dpll_parent,
 754         .ops            = &clkops_omap3_noncore_dpll_ops,
 755         .recalc         = &omap3_dpll_recalc,
 756         .round_rate     = &omap2_dpll_round_rate,
 757         .set_rate       = &omap3_noncore_dpll_set_rate,
 758 };
 759
 760 static const struct clksel dpll_mpu_m2_div[] = {
 761         { .parent = &dpll_mpu_ck, .rates = div31_1to31_rates },
 762         { .parent = NULL },
 763 };
 764
 765 static struct clk dpll_mpu_m2_ck = {
 766         .name           = "dpll_mpu_m2_ck",
 767         .parent         = &dpll_mpu_ck,
 768         .clksel         = dpll_mpu_m2_div,
 769         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_MPU,
 770         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
 771         .ops            = &clkops_omap4_dpllmx_ops,
 772         .recalc         = &omap2_clksel_recalc,
 773         .round_rate     = &omap2_clksel_round_rate,
 774         .set_rate       = &omap2_clksel_set_rate,
 775 };
 776
 777 static struct clk per_hs_clk_div_ck = {
 778         .name           = "per_hs_clk_div_ck",
 779         .parent         = &dpll_abe_m3x2_ck,
 780         .ops            = &clkops_null,
 781         .fixed_div      = 2,
 782         .recalc         = &omap_fixed_divisor_recalc,
 783 };
 784
 785 static const struct clksel per_hsd_byp_clk_mux_sel[] = {
 786         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
 787         { .parent = &per_hs_clk_div_ck, .rates = div_1_1_rates },
 788         { .parent = NULL },
 789 };
 790
 791 static struct clk per_hsd_byp_clk_mux_ck = {
 792         .name           = "per_hsd_byp_clk_mux_ck",
 793         .parent         = &sys_clkin_ck,
 794         .clksel         = per_hsd_byp_clk_mux_sel,
 795         .init           = &omap2_init_clksel_parent,
 796         .clksel_reg     = OMAP4430_CM_CLKSEL_DPLL_PER,
 797         .clksel_mask    = OMAP4430_DPLL_BYP_CLKSEL_MASK,
 798         .ops            = &clkops_null,
 799         .recalc         = &omap2_clksel_recalc,
 800 };
 801
 802 /* DPLL_PER */
 803 static struct dpll_data dpll_per_dd = {
 804         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_PER,
 805         .clk_bypass     = &per_hsd_byp_clk_mux_ck,
 806         .clk_ref        = &sys_clkin_ck,
 807         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_PER,
 808         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 809         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_PER,
 810         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_PER,
 811         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 812         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 813         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 814         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 815         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 816         .max_multiplier = 2047,
 817         .max_divider    = 128,
 818         .min_divider    = 1,
 819 };
 820
 821
 822 static struct clk dpll_per_ck = {
 823         .name           = "dpll_per_ck",
 824         .parent         = &sys_clkin_ck,
 825         .dpll_data      = &dpll_per_dd,
 826         .init           = &omap2_init_dpll_parent,
 827         .ops            = &clkops_omap3_noncore_dpll_ops,
 828         .recalc         = &omap3_dpll_recalc,
 829         .round_rate     = &omap2_dpll_round_rate,
 830         .set_rate       = &omap3_noncore_dpll_set_rate,
 831 };
 832
 833 static const struct clksel dpll_per_m2_div[] = {
 834         { .parent = &dpll_per_ck, .rates = div31_1to31_rates },
 835         { .parent = NULL },
 836 };
 837
 838 static struct clk dpll_per_m2_ck = {
 839         .name           = "dpll_per_m2_ck",
 840         .parent         = &dpll_per_ck,
 841         .clksel         = dpll_per_m2_div,
 842         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_PER,
 843         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
 844         .ops            = &clkops_omap4_dpllmx_ops,
 845         .recalc         = &omap2_clksel_recalc,
 846         .round_rate     = &omap2_clksel_round_rate,
 847         .set_rate       = &omap2_clksel_set_rate,
 848 };
 849
 850 static struct clk dpll_per_x2_ck = {
 851         .name           = "dpll_per_x2_ck",
 852         .parent         = &dpll_per_ck,
 853         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_PER,
 854         .flags          = CLOCK_CLKOUTX2,
 855         .ops            = &clkops_omap4_dpllmx_ops,
 856         .recalc         = &omap3_clkoutx2_recalc,
 857 };
 858
 859 static const struct clksel dpll_per_m2x2_div[] = {
 860         { .parent = &dpll_per_x2_ck, .rates = div31_1to31_rates },
 861         { .parent = NULL },
 862 };
 863
 864 static struct clk dpll_per_m2x2_ck = {
 865         .name           = "dpll_per_m2x2_ck",
 866         .parent         = &dpll_per_x2_ck,
 867         .clksel         = dpll_per_m2x2_div,
 868         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_PER,
 869         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
 870         .ops            = &clkops_omap4_dpllmx_ops,
 871         .recalc         = &omap2_clksel_recalc,
 872         .round_rate     = &omap2_clksel_round_rate,
 873         .set_rate       = &omap2_clksel_set_rate,
 874 };
 875
 876 static struct clk dpll_per_m3x2_ck = {
 877         .name           = "dpll_per_m3x2_ck",
 878         .parent         = &dpll_per_x2_ck,
 879         .clksel         = dpll_per_m2x2_div,
 880         .clksel_reg     = OMAP4430_CM_DIV_M3_DPLL_PER,
 881         .clksel_mask    = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
 882         .ops            = &clkops_omap2_dflt,
 883         .recalc         = &omap2_clksel_recalc,
 884         .round_rate     = &omap2_clksel_round_rate,
 885         .set_rate       = &omap2_clksel_set_rate,
 886         .enable_reg     = OMAP4430_CM_DIV_M3_DPLL_PER,
 887         .enable_bit     = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
 888 };
 889
 890 static struct clk dpll_per_m4x2_ck = {
 891         .name           = "dpll_per_m4x2_ck",
 892         .parent         = &dpll_per_x2_ck,
 893         .clksel         = dpll_per_m2x2_div,
 894         .clksel_reg     = OMAP4430_CM_DIV_M4_DPLL_PER,
 895         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
 896         .ops            = &clkops_omap4_dpllmx_ops,
 897         .recalc         = &omap2_clksel_recalc,
 898         .round_rate     = &omap2_clksel_round_rate,
 899         .set_rate       = &omap2_clksel_set_rate,
 900 };
 901
 902 static struct clk dpll_per_m5x2_ck = {
 903         .name           = "dpll_per_m5x2_ck",
 904         .parent         = &dpll_per_x2_ck,
 905         .clksel         = dpll_per_m2x2_div,
 906         .clksel_reg     = OMAP4430_CM_DIV_M5_DPLL_PER,
 907         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
 908         .ops            = &clkops_omap4_dpllmx_ops,
 909         .recalc         = &omap2_clksel_recalc,
 910         .round_rate     = &omap2_clksel_round_rate,
 911         .set_rate       = &omap2_clksel_set_rate,
 912 };
 913
 914 static struct clk dpll_per_m6x2_ck = {
 915         .name           = "dpll_per_m6x2_ck",
 916         .parent         = &dpll_per_x2_ck,
 917         .clksel         = dpll_per_m2x2_div,
 918         .clksel_reg     = OMAP4430_CM_DIV_M6_DPLL_PER,
 919         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
 920         .ops            = &clkops_omap4_dpllmx_ops,
 921         .recalc         = &omap2_clksel_recalc,
 922         .round_rate     = &omap2_clksel_round_rate,
 923         .set_rate       = &omap2_clksel_set_rate,
 924 };
 925
 926 static struct clk dpll_per_m7x2_ck = {
 927         .name           = "dpll_per_m7x2_ck",
 928         .parent         = &dpll_per_x2_ck,
 929         .clksel         = dpll_per_m2x2_div,
 930         .clksel_reg     = OMAP4430_CM_DIV_M7_DPLL_PER,
 931         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
 932         .ops            = &clkops_omap4_dpllmx_ops,
 933         .recalc         = &omap2_clksel_recalc,
 934         .round_rate     = &omap2_clksel_round_rate,
 935         .set_rate       = &omap2_clksel_set_rate,
 936 };
 937
 938 static struct clk usb_hs_clk_div_ck = {
 939         .name           = "usb_hs_clk_div_ck",
 940         .parent         = &dpll_abe_m3x2_ck,
 941         .ops            = &clkops_null,
 942         .fixed_div      = 3,
 943         .recalc         = &omap_fixed_divisor_recalc,
 944 };
 945
 946 /* DPLL_USB */
 947 static struct dpll_data dpll_usb_dd = {
 948         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_USB,
 949         .clk_bypass     = &usb_hs_clk_div_ck,
 950         .flags          = DPLL_J_TYPE,
 951         .clk_ref        = &sys_clkin_ck,
 952         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_USB,
 953         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 954         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_USB,
 955         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_USB,
 956         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 957         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 958         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 959         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 960         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 961         .sddiv_mask     = OMAP4430_DPLL_SD_DIV_MASK,
 962         .max_multiplier = 4095,
 963         .max_divider    = 256,
 964         .min_divider    = 1,
 965 };
 966
 967
 968 static struct clk dpll_usb_ck = {
 969         .name           = "dpll_usb_ck",
 970         .parent         = &sys_clkin_ck,
 971         .dpll_data      = &dpll_usb_dd,
 972         .init           = &omap2_init_dpll_parent,
 973         .ops            = &clkops_omap3_noncore_dpll_ops,
 974         .recalc         = &omap3_dpll_recalc,
 975         .round_rate     = &omap2_dpll_round_rate,
 976         .set_rate       = &omap3_noncore_dpll_set_rate,
 977 };
 978
 979 static struct clk dpll_usb_clkdcoldo_ck = {
 980         .name           = "dpll_usb_clkdcoldo_ck",
 981         .parent         = &dpll_usb_ck,
 982         .clksel_reg     = OMAP4430_CM_CLKDCOLDO_DPLL_USB,
 983         .ops            = &clkops_omap4_dpllmx_ops,
 984         .recalc         = &followparent_recalc,
 985 };
 986
 987 static const struct clksel dpll_usb_m2_div[] = {
 988         { .parent = &dpll_usb_ck, .rates = div31_1to31_rates },
 989         { .parent = NULL },
 990 };
 991
 992 static struct clk dpll_usb_m2_ck = {
 993         .name           = "dpll_usb_m2_ck",
 994         .parent         = &dpll_usb_ck,
 995         .clksel         = dpll_usb_m2_div,
 996         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_USB,
 997         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK,
 998         .ops            = &clkops_omap4_dpllmx_ops,
 999         .recalc         = &omap2_clksel_recalc,
1000         .round_rate     = &omap2_clksel_round_rate,
1001         .set_rate       = &omap2_clksel_set_rate,
1002 };
1003
1004 static const struct clksel ducati_clk_mux_sel[] = {
1005         { .parent = &div_core_ck, .rates = div_1_0_rates },
1006         { .parent = &dpll_per_m6x2_ck, .rates = div_1_1_rates },
1007         { .parent = NULL },
1008 };
1009
1010 static struct clk ducati_clk_mux_ck = {
1011         .name           = "ducati_clk_mux_ck",
1012         .parent         = &div_core_ck,
1013         .clksel         = ducati_clk_mux_sel,
1014         .init           = &omap2_init_clksel_parent,
1015         .clksel_reg     = OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT,
1016         .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
1017         .ops            = &clkops_null,
1018         .recalc         = &omap2_clksel_recalc,
1019 };
1020
1021 static struct clk func_12m_fclk = {
1022         .name           = "func_12m_fclk",
1023         .parent         = &dpll_per_m2x2_ck,
1024         .ops            = &clkops_null,
1025         .fixed_div      = 16,
1026         .recalc         = &omap_fixed_divisor_recalc,
1027 };
1028
1029 static struct clk func_24m_clk = {
1030         .name           = "func_24m_clk",
1031         .parent         = &dpll_per_m2_ck,
1032         .ops            = &clkops_null,
1033         .fixed_div      = 4,
1034         .recalc         = &omap_fixed_divisor_recalc,
1035 };
1036
1037 static struct clk func_24mc_fclk = {
1038         .name           = "func_24mc_fclk",
1039         .parent         = &dpll_per_m2x2_ck,
1040         .ops            = &clkops_null,
1041         .fixed_div      = 8,
1042         .recalc         = &omap_fixed_divisor_recalc,
1043 };
1044
1045 static const struct clksel_rate div2_4to8_rates[] = {
1046         { .div = 4, .val = 0, .flags = RATE_IN_4430 },
1047         { .div = 8, .val = 1, .flags = RATE_IN_4430 },
1048         { .div = 0 },
1049 };
1050
1051 static const struct clksel func_48m_fclk_div[] = {
1052         { .parent = &dpll_per_m2x2_ck, .rates = div2_4to8_rates },
1053         { .parent = NULL },
1054 };
1055
1056 static struct clk func_48m_fclk = {
1057         .name           = "func_48m_fclk",
1058         .parent         = &dpll_per_m2x2_ck,
1059         .clksel         = func_48m_fclk_div,
1060         .clksel_reg     = OMAP4430_CM_SCALE_FCLK,
1061         .clksel_mask    = OMAP4430_SCALE_FCLK_MASK,
1062         .ops            = &clkops_null,
1063         .recalc         = &omap2_clksel_recalc,
1064         .round_rate     = &omap2_clksel_round_rate,
1065         .set_rate       = &omap2_clksel_set_rate,
1066 };
1067
1068 static struct clk func_48mc_fclk = {
1069         .name           = "func_48mc_fclk",
1070         .parent         = &dpll_per_m2x2_ck,
1071         .ops            = &clkops_null,
1072         .fixed_div      = 4,
1073         .recalc         = &omap_fixed_divisor_recalc,
1074 };
1075
1076 static const struct clksel_rate div2_2to4_rates[] = {
1077         { .div = 2, .val = 0, .flags = RATE_IN_4430 },
1078         { .div = 4, .val = 1, .flags = RATE_IN_4430 },
1079         { .div = 0 },
1080 };
1081
1082 static const struct clksel func_64m_fclk_div[] = {
1083         { .parent = &dpll_per_m4x2_ck, .rates = div2_2to4_rates },
1084         { .parent = NULL },
1085 };
1086
1087 static struct clk func_64m_fclk = {
1088         .name           = "func_64m_fclk",
1089         .parent         = &dpll_per_m4x2_ck,
1090         .clksel         = func_64m_fclk_div,
1091         .clksel_reg     = OMAP4430_CM_SCALE_FCLK,
1092         .clksel_mask    = OMAP4430_SCALE_FCLK_MASK,
1093         .ops            = &clkops_null,
1094         .recalc         = &omap2_clksel_recalc,
1095         .round_rate     = &omap2_clksel_round_rate,
1096         .set_rate       = &omap2_clksel_set_rate,
1097 };
1098
1099 static const struct clksel func_96m_fclk_div[] = {
1100         { .parent = &dpll_per_m2x2_ck, .rates = div2_2to4_rates },
1101         { .parent = NULL },
1102 };
1103
1104 static struct clk func_96m_fclk = {
1105         .name           = "func_96m_fclk",
1106         .parent         = &dpll_per_m2x2_ck,
1107         .clksel         = func_96m_fclk_div,
1108         .clksel_reg     = OMAP4430_CM_SCALE_FCLK,
1109         .clksel_mask    = OMAP4430_SCALE_FCLK_MASK,
1110         .ops            = &clkops_null,
1111         .recalc         = &omap2_clksel_recalc,
1112         .round_rate     = &omap2_clksel_round_rate,
1113         .set_rate       = &omap2_clksel_set_rate,
1114 };
1115
1116 static const struct clksel_rate div2_1to8_rates[] = {
1117         { .div = 1, .val = 0, .flags = RATE_IN_4430 },
1118         { .div = 8, .val = 1, .flags = RATE_IN_4430 },
1119         { .div = 0 },
1120 };
1121
1122 static const struct clksel init_60m_fclk_div[] = {
1123         { .parent = &dpll_usb_m2_ck, .rates = div2_1to8_rates },
1124         { .parent = NULL },
1125 };
1126
1127 static struct clk init_60m_fclk = {
1128         .name           = "init_60m_fclk",
1129         .parent         = &dpll_usb_m2_ck,
1130         .clksel         = init_60m_fclk_div,
1131         .clksel_reg     = OMAP4430_CM_CLKSEL_USB_60MHZ,
1132         .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
1133         .ops            = &clkops_null,
1134         .recalc         = &omap2_clksel_recalc,
1135         .round_rate     = &omap2_clksel_round_rate,
1136         .set_rate       = &omap2_clksel_set_rate,
1137 };
1138
1139 static const struct clksel l3_div_div[] = {
1140         { .parent = &div_core_ck, .rates = div2_1to2_rates },
1141         { .parent = NULL },
1142 };
1143
1144 static struct clk l3_div_ck = {
1145         .name           = "l3_div_ck",
1146         .parent         = &div_core_ck,
1147         .clksel         = l3_div_div,
1148         .clksel_reg     = OMAP4430_CM_CLKSEL_CORE,
1149         .clksel_mask    = OMAP4430_CLKSEL_L3_MASK,
1150         .ops            = &clkops_null,
1151         .recalc         = &omap2_clksel_recalc,
1152         .round_rate     = &omap2_clksel_round_rate,
1153         .set_rate       = &omap2_clksel_set_rate,
1154 };
1155
1156 static const struct clksel l4_div_div[] = {
1157         { .parent = &l3_div_ck, .rates = div2_1to2_rates },
1158         { .parent = NULL },
1159 };
1160
1161 static struct clk l4_div_ck = {
1162         .name           = "l4_div_ck",
1163         .parent         = &l3_div_ck,
1164         .clksel         = l4_div_div,
1165         .clksel_reg     = OMAP4430_CM_CLKSEL_CORE,
1166         .clksel_mask    = OMAP4430_CLKSEL_L4_MASK,
1167         .ops            = &clkops_null,
1168         .recalc         = &omap2_clksel_recalc,
1169         .round_rate     = &omap2_clksel_round_rate,
1170         .set_rate       = &omap2_clksel_set_rate,
1171 };
1172
1173 static struct clk lp_clk_div_ck = {
1174         .name           = "lp_clk_div_ck",
1175         .parent         = &dpll_abe_m2x2_ck,
1176         .ops            = &clkops_null,
1177         .fixed_div      = 16,
1178         .recalc         = &omap_fixed_divisor_recalc,
1179 };
1180
1181 static const struct clksel l4_wkup_clk_mux_sel[] = {
1182         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
1183         { .parent = &lp_clk_div_ck, .rates = div_1_1_rates },
1184         { .parent = NULL },
1185 };
1186
1187 static struct clk l4_wkup_clk_mux_ck = {
1188         .name           = "l4_wkup_clk_mux_ck",
1189         .parent         = &sys_clkin_ck,
1190         .clksel         = l4_wkup_clk_mux_sel,
1191         .init           = &omap2_init_clksel_parent,
1192         .clksel_reg     = OMAP4430_CM_L4_WKUP_CLKSEL,
1193         .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
1194         .ops            = &clkops_null,
1195         .recalc         = &omap2_clksel_recalc,
1196 };
1197
1198 static struct clk ocp_abe_iclk = {
1199         .name           = "ocp_abe_iclk",
1200         .parent         = &aess_fclk,
1201         .ops            = &clkops_null,
1202         .recalc         = &followparent_recalc,
1203 };
1204
1205 static struct clk per_abe_24m_fclk = {
1206         .name           = "per_abe_24m_fclk",
1207         .parent         = &dpll_abe_m2_ck,
1208         .ops            = &clkops_null,
1209         .fixed_div      = 4,
1210         .recalc         = &omap_fixed_divisor_recalc,
1211 };
1212
1213 static const struct clksel per_abe_nc_fclk_div[] = {
1214         { .parent = &dpll_abe_m2_ck, .rates = div2_1to2_rates },
1215         { .parent = NULL },
1216 };
1217
1218 static struct clk per_abe_nc_fclk = {
1219         .name           = "per_abe_nc_fclk",
1220         .parent         = &dpll_abe_m2_ck,
1221         .clksel         = per_abe_nc_fclk_div,
1222         .clksel_reg     = OMAP4430_CM_SCALE_FCLK,
1223         .clksel_mask    = OMAP4430_SCALE_FCLK_MASK,
1224         .ops            = &clkops_null,
1225         .recalc         = &omap2_clksel_recalc,
1226         .round_rate     = &omap2_clksel_round_rate,
1227         .set_rate       = &omap2_clksel_set_rate,
1228 };
1229
1230 static const struct clksel pmd_stm_clock_mux_sel[] = {
1231         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
1232         { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates },
1233         { .parent = &tie_low_clock_ck, .rates = div_1_2_rates },
1234         { .parent = NULL },
1235 };
1236
1237 static struct clk pmd_stm_clock_mux_ck = {
1238         .name           = "pmd_stm_clock_mux_ck",
1239         .parent         = &sys_clkin_ck,
1240         .ops            = &clkops_null,
1241         .recalc         = &followparent_recalc,
1242 };
1243
1244 static struct clk pmd_trace_clk_mux_ck = {
1245         .name           = "pmd_trace_clk_mux_ck",
1246         .parent         = &sys_clkin_ck,
1247         .ops            = &clkops_null,
1248         .recalc         = &followparent_recalc,
1249 };
1250
1251 static const struct clksel syc_clk_div_div[] = {
1252         { .parent = &sys_clkin_ck, .rates = div2_1to2_rates },
1253         { .parent = NULL },
1254 };
1255
1256 static struct clk syc_clk_div_ck = {
1257         .name           = "syc_clk_div_ck",
1258         .parent         = &sys_clkin_ck,
1259         .clksel         = syc_clk_div_div,
1260         .clksel_reg     = OMAP4430_CM_ABE_DSS_SYS_CLKSEL,
1261         .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
1262         .ops            = &clkops_null,
1263         .recalc         = &omap2_clksel_recalc,
1264         .round_rate     = &omap2_clksel_round_rate,
1265         .set_rate       = &omap2_clksel_set_rate,
1266 };
1267
1268 /* Leaf clocks controlled by modules */
1269
1270 static struct clk aes1_fck = {
1271         .name           = "aes1_fck",
1272         .ops            = &clkops_omap2_dflt,
1273         .enable_reg     = OMAP4430_CM_L4SEC_AES1_CLKCTRL,
1274         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1275         .clkdm_name     = "l4_secure_clkdm",
1276         .parent         = &l3_div_ck,
1277         .recalc         = &followparent_recalc,
1278 };
1279
1280 static struct clk aes2_fck = {
1281         .name           = "aes2_fck",
1282         .ops            = &clkops_omap2_dflt,
1283         .enable_reg     = OMAP4430_CM_L4SEC_AES2_CLKCTRL,
1284         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1285         .clkdm_name     = "l4_secure_clkdm",
1286         .parent         = &l3_div_ck,
1287         .recalc         = &followparent_recalc,
1288 };
1289
1290 static struct clk aess_fck = {
1291         .name           = "aess_fck",
1292         .ops            = &clkops_omap2_dflt,
1293         .enable_reg     = OMAP4430_CM1_ABE_AESS_CLKCTRL,
1294         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1295         .clkdm_name     = "abe_clkdm",
1296         .parent         = &aess_fclk,
1297         .recalc         = &followparent_recalc,
1298 };
1299
1300 static struct clk bandgap_fclk = {
1301         .name           = "bandgap_fclk",
1302         .ops            = &clkops_omap2_dflt,
1303         .enable_reg     = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
1304         .enable_bit     = OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT,
1305         .clkdm_name     = "l4_wkup_clkdm",
1306         .parent         = &sys_32k_ck,
1307         .recalc         = &followparent_recalc,
1308 };
1309
1310 static struct clk des3des_fck = {
1311         .name           = "des3des_fck",
1312         .ops            = &clkops_omap2_dflt,
1313         .enable_reg     = OMAP4430_CM_L4SEC_DES3DES_CLKCTRL,
1314         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1315         .clkdm_name     = "l4_secure_clkdm",
1316         .parent         = &l4_div_ck,
1317         .recalc         = &followparent_recalc,
1318 };
1319
1320 static const struct clksel dmic_sync_mux_sel[] = {
1321         { .parent = &abe_24m_fclk, .rates = div_1_0_rates },
1322         { .parent = &syc_clk_div_ck, .rates = div_1_1_rates },
1323         { .parent = &func_24m_clk, .rates = div_1_2_rates },
1324         { .parent = NULL },
1325 };
1326
1327 static struct clk dmic_sync_mux_ck = {
1328         .name           = "dmic_sync_mux_ck",
1329         .parent         = &abe_24m_fclk,
1330         .clksel         = dmic_sync_mux_sel,
1331         .init           = &omap2_init_clksel_parent,
1332         .clksel_reg     = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1333         .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1334         .ops            = &clkops_null,
1335         .recalc         = &omap2_clksel_recalc,
1336 };
1337
1338 static const struct clksel func_dmic_abe_gfclk_sel[] = {
1339         { .parent = &dmic_sync_mux_ck, .rates = div_1_0_rates },
1340         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1341         { .parent = &slimbus_clk, .rates = div_1_2_rates },
1342         { .parent = NULL },
1343 };
1344
1345 /* Merged func_dmic_abe_gfclk into dmic */
1346 static struct clk dmic_fck = {
1347         .name           = "dmic_fck",
1348         .parent         = &dmic_sync_mux_ck,
1349         .clksel         = func_dmic_abe_gfclk_sel,
1350         .init           = &omap2_init_clksel_parent,
1351         .clksel_reg     = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1352         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
1353         .ops            = &clkops_omap2_dflt,
1354         .recalc         = &omap2_clksel_recalc,
1355         .enable_reg     = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1356         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1357         .clkdm_name     = "abe_clkdm",
1358 };
1359
1360 static struct clk dsp_fck = {
1361         .name           = "dsp_fck",
1362         .ops            = &clkops_omap2_dflt,
1363         .enable_reg     = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
1364         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1365         .clkdm_name     = "tesla_clkdm",
1366         .parent         = &dpll_iva_m4x2_ck,
1367         .recalc         = &followparent_recalc,
1368 };
1369
1370 static struct clk dss_sys_clk = {
1371         .name           = "dss_sys_clk",
1372         .ops            = &clkops_omap2_dflt,
1373         .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
1374         .enable_bit     = OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT,
1375         .clkdm_name     = "l3_dss_clkdm",
1376         .parent         = &syc_clk_div_ck,
1377         .recalc         = &followparent_recalc,
1378 };
1379
1380 static struct clk dss_tv_clk = {
1381         .name           = "dss_tv_clk",
1382         .ops            = &clkops_omap2_dflt,
1383         .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
1384         .enable_bit     = OMAP4430_OPTFCLKEN_TV_CLK_SHIFT,
1385         .clkdm_name     = "l3_dss_clkdm",
1386         .parent         = &extalt_clkin_ck,
1387         .recalc         = &followparent_recalc,
1388 };
1389
1390 static struct clk dss_dss_clk = {
1391         .name           = "dss_dss_clk",
1392         .ops            = &clkops_omap2_dflt,
1393         .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
1394         .enable_bit     = OMAP4430_OPTFCLKEN_DSSCLK_SHIFT,
1395         .clkdm_name     = "l3_dss_clkdm",
1396         .parent         = &dpll_per_m5x2_ck,
1397         .recalc         = &followparent_recalc,
1398 };
1399
1400 static const struct clksel_rate div3_8to32_rates[] = {
1401         { .div = 8, .val = 0, .flags = RATE_IN_44XX },
1402         { .div = 16, .val = 1, .flags = RATE_IN_44XX },
1403         { .div = 32, .val = 2, .flags = RATE_IN_44XX },
1404         { .div = 0 },
1405 };
1406
1407 static const struct clksel div_ts_div[] = {
1408         { .parent = &l4_wkup_clk_mux_ck, .rates = div3_8to32_rates },
1409         { .parent = NULL },
1410 };
1411
1412 static struct clk div_ts_ck = {
1413         .name           = "div_ts_ck",
1414         .parent         = &l4_wkup_clk_mux_ck,
1415         .clksel         = div_ts_div,
1416         .clksel_reg     = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
1417         .clksel_mask    = OMAP4430_CLKSEL_24_25_MASK,
1418         .ops            = &clkops_null,
1419         .recalc         = &omap2_clksel_recalc,
1420         .round_rate     = &omap2_clksel_round_rate,
1421         .set_rate       = &omap2_clksel_set_rate,
1422 };
1423
1424 static struct clk bandgap_ts_fclk = {
1425         .name           = "bandgap_ts_fclk",
1426         .ops            = &clkops_omap2_dflt,
1427         .enable_reg     = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
1428         .enable_bit     = OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT,
1429         .clkdm_name     = "l4_wkup_clkdm",
1430         .parent         = &div_ts_ck,
1431         .recalc         = &followparent_recalc,
1432 };
1433
1434 static struct clk dss_48mhz_clk = {
1435         .name           = "dss_48mhz_clk",
1436         .ops            = &clkops_omap2_dflt,
1437         .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
1438         .enable_bit     = OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT,
1439         .clkdm_name     = "l3_dss_clkdm",
1440         .parent         = &func_48mc_fclk,
1441         .recalc         = &followparent_recalc,
1442 };
1443
1444 static struct clk dss_fck = {
1445         .name           = "dss_fck",
1446         .ops            = &clkops_omap2_dflt,
1447         .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
1448         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1449         .clkdm_name     = "l3_dss_clkdm",
1450         .parent         = &l3_div_ck,
1451         .recalc         = &followparent_recalc,
1452 };
1453
1454 static struct clk efuse_ctrl_cust_fck = {
1455         .name           = "efuse_ctrl_cust_fck",
1456         .ops            = &clkops_omap2_dflt,
1457         .enable_reg     = OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL,
1458         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1459         .clkdm_name     = "l4_cefuse_clkdm",
1460         .parent         = &sys_clkin_ck,
1461         .recalc         = &followparent_recalc,
1462 };
1463
1464 static struct clk emif1_fck = {
1465         .name           = "emif1_fck",
1466         .ops            = &clkops_omap2_dflt,
1467         .enable_reg     = OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL,
1468         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1469         .flags          = ENABLE_ON_INIT,
1470         .clkdm_name     = "l3_emif_clkdm",
1471         .parent         = &ddrphy_ck,
1472         .recalc         = &followparent_recalc,
1473 };
1474
1475 static struct clk emif2_fck = {
1476         .name           = "emif2_fck",
1477         .ops            = &clkops_omap2_dflt,
1478         .enable_reg     = OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL,
1479         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1480         .flags          = ENABLE_ON_INIT,
1481         .clkdm_name     = "l3_emif_clkdm",
1482         .parent         = &ddrphy_ck,
1483         .recalc         = &followparent_recalc,
1484 };
1485
1486 static const struct clksel fdif_fclk_div[] = {
1487         { .parent = &dpll_per_m4x2_ck, .rates = div3_1to4_rates },
1488         { .parent = NULL },
1489 };
1490
1491 /* Merged fdif_fclk into fdif */
1492 static struct clk fdif_fck = {
1493         .name           = "fdif_fck",
1494         .parent         = &dpll_per_m4x2_ck,
1495         .clksel         = fdif_fclk_div,
1496         .clksel_reg     = OMAP4430_CM_CAM_FDIF_CLKCTRL,
1497         .clksel_mask    = OMAP4430_CLKSEL_FCLK_MASK,
1498         .ops            = &clkops_omap2_dflt,
1499         .recalc         = &omap2_clksel_recalc,
1500         .round_rate     = &omap2_clksel_round_rate,
1501         .set_rate       = &omap2_clksel_set_rate,
1502         .enable_reg     = OMAP4430_CM_CAM_FDIF_CLKCTRL,
1503         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1504         .clkdm_name     = "iss_clkdm",
1505 };
1506
1507 static struct clk fpka_fck = {
1508         .name           = "fpka_fck",
1509         .ops            = &clkops_omap2_dflt,
1510         .enable_reg     = OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL,
1511         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1512         .clkdm_name     = "l4_secure_clkdm",
1513         .parent         = &l4_div_ck,
1514         .recalc         = &followparent_recalc,
1515 };
1516
1517 static struct clk gpio1_dbclk = {
1518         .name           = "gpio1_dbclk",
1519         .ops            = &clkops_omap2_dflt,
1520         .enable_reg     = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
1521         .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1522         .clkdm_name     = "l4_wkup_clkdm",
1523         .parent         = &sys_32k_ck,
1524         .recalc         = &followparent_recalc,
1525 };
1526
1527 static struct clk gpio1_ick = {
1528         .name           = "gpio1_ick",
1529         .ops            = &clkops_omap2_dflt,
1530         .enable_reg     = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
1531         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1532         .clkdm_name     = "l4_wkup_clkdm",
1533         .parent         = &l4_wkup_clk_mux_ck,
1534         .recalc         = &followparent_recalc,
1535 };
1536
1537 static struct clk gpio2_dbclk = {
1538         .name           = "gpio2_dbclk",
1539         .ops            = &clkops_omap2_dflt,
1540         .enable_reg     = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
1541         .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1542         .clkdm_name     = "l4_per_clkdm",
1543         .parent         = &sys_32k_ck,
1544         .recalc         = &followparent_recalc,
1545 };
1546
1547 static struct clk gpio2_ick = {
1548         .name           = "gpio2_ick",
1549         .ops            = &clkops_omap2_dflt,
1550         .enable_reg     = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
1551         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1552         .clkdm_name     = "l4_per_clkdm",
1553         .parent         = &l4_div_ck,
1554         .recalc         = &followparent_recalc,
1555 };
1556
1557 static struct clk gpio3_dbclk = {
1558         .name           = "gpio3_dbclk",
1559         .ops            = &clkops_omap2_dflt,
1560         .enable_reg     = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
1561         .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1562         .clkdm_name     = "l4_per_clkdm",
1563         .parent         = &sys_32k_ck,
1564         .recalc         = &followparent_recalc,
1565 };
1566
1567 static struct clk gpio3_ick = {
1568         .name           = "gpio3_ick",
1569         .ops            = &clkops_omap2_dflt,
1570         .enable_reg     = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
1571         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1572         .clkdm_name     = "l4_per_clkdm",
1573         .parent         = &l4_div_ck,
1574         .recalc         = &followparent_recalc,
1575 };
1576
1577 static struct clk gpio4_dbclk = {
1578         .name           = "gpio4_dbclk",
1579         .ops            = &clkops_omap2_dflt,
1580         .enable_reg     = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
1581         .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1582         .clkdm_name     = "l4_per_clkdm",
1583         .parent         = &sys_32k_ck,
1584         .recalc         = &followparent_recalc,
1585 };
1586
1587 static struct clk gpio4_ick = {
1588         .name           = "gpio4_ick",
1589         .ops            = &clkops_omap2_dflt,
1590         .enable_reg     = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
1591         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1592         .clkdm_name     = "l4_per_clkdm",
1593         .parent         = &l4_div_ck,
1594         .recalc         = &followparent_recalc,
1595 };
1596
1597 static struct clk gpio5_dbclk = {
1598         .name           = "gpio5_dbclk",
1599         .ops            = &clkops_omap2_dflt,
1600         .enable_reg     = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
1601         .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1602         .clkdm_name     = "l4_per_clkdm",
1603         .parent         = &sys_32k_ck,
1604         .recalc         = &followparent_recalc,
1605 };
1606
1607 static struct clk gpio5_ick = {
1608         .name           = "gpio5_ick",
1609         .ops            = &clkops_omap2_dflt,
1610         .enable_reg     = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
1611         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1612         .clkdm_name     = "l4_per_clkdm",
1613         .parent         = &l4_div_ck,
1614         .recalc         = &followparent_recalc,
1615 };
1616
1617 static struct clk gpio6_dbclk = {
1618         .name           = "gpio6_dbclk",
1619         .ops            = &clkops_omap2_dflt,
1620         .enable_reg     = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
1621         .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1622         .clkdm_name     = "l4_per_clkdm",
1623         .parent         = &sys_32k_ck,
1624         .recalc         = &followparent_recalc,
1625 };
1626
1627 static struct clk gpio6_ick = {
1628         .name           = "gpio6_ick",
1629         .ops            = &clkops_omap2_dflt,
1630         .enable_reg     = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
1631         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1632         .clkdm_name     = "l4_per_clkdm",
1633         .parent         = &l4_div_ck,
1634         .recalc         = &followparent_recalc,
1635 };
1636
1637 static struct clk gpmc_ick = {
1638         .name           = "gpmc_ick",
1639         .ops            = &clkops_omap2_dflt,
1640         .enable_reg     = OMAP4430_CM_L3_2_GPMC_CLKCTRL,
1641         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1642         .clkdm_name     = "l3_2_clkdm",
1643         .parent         = &l3_div_ck,
1644         .recalc         = &followparent_recalc,
1645 };
1646
1647 static const struct clksel sgx_clk_mux_sel[] = {
1648         { .parent = &dpll_core_m7x2_ck, .rates = div_1_0_rates },
1649         { .parent = &dpll_per_m7x2_ck, .rates = div_1_1_rates },
1650         { .parent = NULL },
1651 };
1652
1653 /* Merged sgx_clk_mux into gpu */
1654 static struct clk gpu_fck = {
1655         .name           = "gpu_fck",
1656         .parent         = &dpll_core_m7x2_ck,
1657         .clksel         = sgx_clk_mux_sel,
1658         .init           = &omap2_init_clksel_parent,
1659         .clksel_reg     = OMAP4430_CM_GFX_GFX_CLKCTRL,
1660         .clksel_mask    = OMAP4430_CLKSEL_SGX_FCLK_MASK,
1661         .ops            = &clkops_omap2_dflt,
1662         .recalc         = &omap2_clksel_recalc,
1663         .enable_reg     = OMAP4430_CM_GFX_GFX_CLKCTRL,
1664         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1665         .clkdm_name     = "l3_gfx_clkdm",
1666 };
1667
1668 static struct clk hdq1w_fck = {
1669         .name           = "hdq1w_fck",
1670         .ops            = &clkops_omap2_dflt,
1671         .enable_reg     = OMAP4430_CM_L4PER_HDQ1W_CLKCTRL,
1672         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1673         .clkdm_name     = "l4_per_clkdm",
1674         .parent         = &func_12m_fclk,
1675         .recalc         = &followparent_recalc,
1676 };
1677
1678 static const struct clksel hsi_fclk_div[] = {
1679         { .parent = &dpll_per_m2x2_ck, .rates = div3_1to4_rates },
1680         { .parent = NULL },
1681 };
1682
1683 /* Merged hsi_fclk into hsi */
1684 static struct clk hsi_fck = {
1685         .name           = "hsi_fck",
1686         .parent         = &dpll_per_m2x2_ck,
1687         .clksel         = hsi_fclk_div,
1688         .clksel_reg     = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
1689         .clksel_mask    = OMAP4430_CLKSEL_24_25_MASK,
1690         .ops            = &clkops_omap2_dflt,
1691         .recalc         = &omap2_clksel_recalc,
1692         .round_rate     = &omap2_clksel_round_rate,
1693         .set_rate       = &omap2_clksel_set_rate,
1694         .enable_reg     = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
1695         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1696         .clkdm_name     = "l3_init_clkdm",
1697 };
1698
1699 static struct clk i2c1_fck = {
1700         .name           = "i2c1_fck",
1701         .ops            = &clkops_omap2_dflt,
1702         .enable_reg     = OMAP4430_CM_L4PER_I2C1_CLKCTRL,
1703         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1704         .clkdm_name     = "l4_per_clkdm",
1705         .parent         = &func_96m_fclk,
1706         .recalc         = &followparent_recalc,
1707 };
1708
1709 static struct clk i2c2_fck = {
1710         .name           = "i2c2_fck",
1711         .ops            = &clkops_omap2_dflt,
1712         .enable_reg     = OMAP4430_CM_L4PER_I2C2_CLKCTRL,
1713         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1714         .clkdm_name     = "l4_per_clkdm",
1715         .parent         = &func_96m_fclk,
1716         .recalc         = &followparent_recalc,
1717 };
1718
1719 static struct clk i2c3_fck = {
1720         .name           = "i2c3_fck",
1721         .ops            = &clkops_omap2_dflt,
1722         .enable_reg     = OMAP4430_CM_L4PER_I2C3_CLKCTRL,
1723         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1724         .clkdm_name     = "l4_per_clkdm",
1725         .parent         = &func_96m_fclk,
1726         .recalc         = &followparent_recalc,
1727 };
1728
1729 static struct clk i2c4_fck = {
1730         .name           = "i2c4_fck",
1731         .ops            = &clkops_omap2_dflt,
1732         .enable_reg     = OMAP4430_CM_L4PER_I2C4_CLKCTRL,
1733         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1734         .clkdm_name     = "l4_per_clkdm",
1735         .parent         = &func_96m_fclk,
1736         .recalc         = &followparent_recalc,
1737 };
1738
1739 static struct clk ipu_fck = {
1740         .name           = "ipu_fck",
1741         .ops            = &clkops_omap2_dflt,
1742         .enable_reg     = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
1743         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1744         .clkdm_name     = "ducati_clkdm",
1745         .parent         = &ducati_clk_mux_ck,
1746         .recalc         = &followparent_recalc,
1747 };
1748
1749 static struct clk iss_ctrlclk = {
1750         .name           = "iss_ctrlclk",
1751         .ops            = &clkops_omap2_dflt,
1752         .enable_reg     = OMAP4430_CM_CAM_ISS_CLKCTRL,
1753         .enable_bit     = OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT,
1754         .clkdm_name     = "iss_clkdm",
1755         .parent         = &func_96m_fclk,
1756         .recalc         = &followparent_recalc,
1757 };
1758
1759 static struct clk iss_fck = {
1760         .name           = "iss_fck",
1761         .ops            = &clkops_omap2_dflt,
1762         .enable_reg     = OMAP4430_CM_CAM_ISS_CLKCTRL,
1763         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1764         .clkdm_name     = "iss_clkdm",
1765         .parent         = &ducati_clk_mux_ck,
1766         .recalc         = &followparent_recalc,
1767 };
1768
1769 static struct clk iva_fck = {
1770         .name           = "iva_fck",
1771         .ops            = &clkops_omap2_dflt,
1772         .enable_reg     = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
1773         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1774         .clkdm_name     = "ivahd_clkdm",
1775         .parent         = &dpll_iva_m5x2_ck,
1776         .recalc         = &followparent_recalc,
1777 };
1778
1779 static struct clk kbd_fck = {
1780         .name           = "kbd_fck",
1781         .ops            = &clkops_omap2_dflt,
1782         .enable_reg     = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
1783         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1784         .clkdm_name     = "l4_wkup_clkdm",
1785         .parent         = &sys_32k_ck,
1786         .recalc         = &followparent_recalc,
1787 };
1788
1789 static struct clk l3_instr_ick = {
1790         .name           = "l3_instr_ick",
1791         .ops            = &clkops_omap2_dflt,
1792         .enable_reg     = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL,
1793         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1794         .flags          = ENABLE_ON_INIT,
1795         .clkdm_name     = "l3_instr_clkdm",
1796         .parent         = &l3_div_ck,
1797         .recalc         = &followparent_recalc,
1798 };
1799
1800 static struct clk l3_main_3_ick = {
1801         .name           = "l3_main_3_ick",
1802         .ops            = &clkops_omap2_dflt,
1803         .enable_reg     = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL,
1804         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1805         .flags          = ENABLE_ON_INIT,
1806         .clkdm_name     = "l3_instr_clkdm",
1807         .parent         = &l3_div_ck,
1808         .recalc         = &followparent_recalc,
1809 };
1810
1811 static struct clk mcasp_sync_mux_ck = {
1812         .name           = "mcasp_sync_mux_ck",
1813         .parent         = &abe_24m_fclk,
1814         .clksel         = dmic_sync_mux_sel,
1815         .init           = &omap2_init_clksel_parent,
1816         .clksel_reg     = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1817         .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1818         .ops            = &clkops_null,
1819         .recalc         = &omap2_clksel_recalc,
1820 };
1821
1822 static const struct clksel func_mcasp_abe_gfclk_sel[] = {
1823         { .parent = &mcasp_sync_mux_ck, .rates = div_1_0_rates },
1824         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1825         { .parent = &slimbus_clk, .rates = div_1_2_rates },
1826         { .parent = NULL },
1827 };
1828
1829 /* Merged func_mcasp_abe_gfclk into mcasp */
1830 static struct clk mcasp_fck = {
1831         .name           = "mcasp_fck",
1832         .parent         = &mcasp_sync_mux_ck,
1833         .clksel         = func_mcasp_abe_gfclk_sel,
1834         .init           = &omap2_init_clksel_parent,
1835         .clksel_reg     = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1836         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
1837         .ops            = &clkops_omap2_dflt,
1838         .recalc         = &omap2_clksel_recalc,
1839         .enable_reg     = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1840         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1841         .clkdm_name     = "abe_clkdm",
1842 };
1843
1844 static struct clk mcbsp1_sync_mux_ck = {
1845         .name           = "mcbsp1_sync_mux_ck",
1846         .parent         = &abe_24m_fclk,
1847         .clksel         = dmic_sync_mux_sel,
1848         .init           = &omap2_init_clksel_parent,
1849         .clksel_reg     = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1850         .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1851         .ops            = &clkops_null,
1852         .recalc         = &omap2_clksel_recalc,
1853 };
1854
1855 static const struct clksel func_mcbsp1_gfclk_sel[] = {
1856         { .parent = &mcbsp1_sync_mux_ck, .rates = div_1_0_rates },
1857         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1858         { .parent = &slimbus_clk, .rates = div_1_2_rates },
1859         { .parent = NULL },
1860 };
1861
1862 /* Merged func_mcbsp1_gfclk into mcbsp1 */
1863 static struct clk mcbsp1_fck = {
1864         .name           = "mcbsp1_fck",
1865         .parent         = &mcbsp1_sync_mux_ck,
1866         .clksel         = func_mcbsp1_gfclk_sel,
1867         .init           = &omap2_init_clksel_parent,
1868         .clksel_reg     = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1869         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
1870         .ops            = &clkops_omap2_dflt,
1871         .recalc         = &omap2_clksel_recalc,
1872         .enable_reg     = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1873         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1874         .clkdm_name     = "abe_clkdm",
1875 };
1876
1877 static struct clk mcbsp2_sync_mux_ck = {
1878         .name           = "mcbsp2_sync_mux_ck",
1879         .parent         = &abe_24m_fclk,
1880         .clksel         = dmic_sync_mux_sel,
1881         .init           = &omap2_init_clksel_parent,
1882         .clksel_reg     = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1883         .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1884         .ops            = &clkops_null,
1885         .recalc         = &omap2_clksel_recalc,
1886 };
1887
1888 static const struct clksel func_mcbsp2_gfclk_sel[] = {
1889         { .parent = &mcbsp2_sync_mux_ck, .rates = div_1_0_rates },
1890         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1891         { .parent = &slimbus_clk, .rates = div_1_2_rates },
1892         { .parent = NULL },
1893 };
1894
1895 /* Merged func_mcbsp2_gfclk into mcbsp2 */
1896 static struct clk mcbsp2_fck = {
1897         .name           = "mcbsp2_fck",
1898         .parent         = &mcbsp2_sync_mux_ck,
1899         .clksel         = func_mcbsp2_gfclk_sel,
1900         .init           = &omap2_init_clksel_parent,
1901         .clksel_reg     = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1902         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
1903         .ops            = &clkops_omap2_dflt,
1904         .recalc         = &omap2_clksel_recalc,
1905         .enable_reg     = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1906         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1907         .clkdm_name     = "abe_clkdm",
1908 };
1909
1910 static struct clk mcbsp3_sync_mux_ck = {
1911         .name           = "mcbsp3_sync_mux_ck",
1912         .parent         = &abe_24m_fclk,
1913         .clksel         = dmic_sync_mux_sel,
1914         .init           = &omap2_init_clksel_parent,
1915         .clksel_reg     = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
1916         .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1917         .ops            = &clkops_null,
1918         .recalc         = &omap2_clksel_recalc,
1919 };
1920
1921 static const struct clksel func_mcbsp3_gfclk_sel[] = {
1922         { .parent = &mcbsp3_sync_mux_ck, .rates = div_1_0_rates },
1923         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1924         { .parent = &slimbus_clk, .rates = div_1_2_rates },
1925         { .parent = NULL },
1926 };
1927
1928 /* Merged func_mcbsp3_gfclk into mcbsp3 */
1929 static struct clk mcbsp3_fck = {
1930         .name           = "mcbsp3_fck",
1931         .parent         = &mcbsp3_sync_mux_ck,
1932         .clksel         = func_mcbsp3_gfclk_sel,
1933         .init           = &omap2_init_clksel_parent,
1934         .clksel_reg     = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
1935         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
1936         .ops            = &clkops_omap2_dflt,
1937         .recalc         = &omap2_clksel_recalc,
1938         .enable_reg     = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
1939         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1940         .clkdm_name     = "abe_clkdm",
1941 };
1942
1943 static const struct clksel mcbsp4_sync_mux_sel[] = {
1944         { .parent = &func_96m_fclk, .rates = div_1_0_rates },
1945         { .parent = &per_abe_nc_fclk, .rates = div_1_1_rates },
1946         { .parent = NULL },
1947 };
1948
1949 static struct clk mcbsp4_sync_mux_ck = {
1950         .name           = "mcbsp4_sync_mux_ck",
1951         .parent         = &func_96m_fclk,
1952         .clksel         = mcbsp4_sync_mux_sel,
1953         .init           = &omap2_init_clksel_parent,
1954         .clksel_reg     = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
1955         .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1956         .ops            = &clkops_null,
1957         .recalc         = &omap2_clksel_recalc,
1958 };
1959
1960 static const struct clksel per_mcbsp4_gfclk_sel[] = {
1961         { .parent = &mcbsp4_sync_mux_ck, .rates = div_1_0_rates },
1962         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1963         { .parent = NULL },
1964 };
1965
1966 /* Merged per_mcbsp4_gfclk into mcbsp4 */
1967 static struct clk mcbsp4_fck = {
1968         .name           = "mcbsp4_fck",
1969         .parent         = &mcbsp4_sync_mux_ck,
1970         .clksel         = per_mcbsp4_gfclk_sel,
1971         .init           = &omap2_init_clksel_parent,
1972         .clksel_reg     = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
1973         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_24_24_MASK,
1974         .ops            = &clkops_omap2_dflt,
1975         .recalc         = &omap2_clksel_recalc,
1976         .enable_reg     = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
1977         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1978         .clkdm_name     = "l4_per_clkdm",
1979 };
1980
1981 static struct clk mcpdm_fck = {
1982         .name           = "mcpdm_fck",
1983         .ops            = &clkops_omap2_dflt,
1984         .enable_reg     = OMAP4430_CM1_ABE_PDM_CLKCTRL,
1985         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1986         .clkdm_name     = "abe_clkdm",
1987         .parent         = &pad_clks_ck,
1988         .recalc         = &followparent_recalc,
1989 };
1990
1991 static struct clk mcspi1_fck = {
1992         .name           = "mcspi1_fck",
1993         .ops            = &clkops_omap2_dflt,
1994         .enable_reg     = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
1995         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1996         .clkdm_name     = "l4_per_clkdm",
1997         .parent         = &func_48m_fclk,
1998         .recalc         = &followparent_recalc,
1999 };
2000
2001 static struct clk mcspi2_fck = {
2002         .name           = "mcspi2_fck",
2003         .ops            = &clkops_omap2_dflt,
2004         .enable_reg     = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
2005         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2006         .clkdm_name     = "l4_per_clkdm",
2007         .parent         = &func_48m_fclk,
2008         .recalc         = &followparent_recalc,
2009 };
2010
2011 static struct clk mcspi3_fck = {
2012         .name           = "mcspi3_fck",
2013         .ops            = &clkops_omap2_dflt,
2014         .enable_reg     = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
2015         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2016         .clkdm_name     = "l4_per_clkdm",
2017         .parent         = &func_48m_fclk,
2018         .recalc         = &followparent_recalc,
2019 };
2020
2021 static struct clk mcspi4_fck = {
2022         .name           = "mcspi4_fck",
2023         .ops            = &clkops_omap2_dflt,
2024         .enable_reg     = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
2025         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2026         .clkdm_name     = "l4_per_clkdm",
2027         .parent         = &func_48m_fclk,
2028         .recalc         = &followparent_recalc,
2029 };
2030
2031 static const struct clksel hsmmc1_fclk_sel[] = {
2032         { .parent = &func_64m_fclk, .rates = div_1_0_rates },
2033         { .parent = &func_96m_fclk, .rates = div_1_1_rates },
2034         { .parent = NULL },
2035 };
2036
2037 /* Merged hsmmc1_fclk into mmc1 */
2038 static struct clk mmc1_fck = {
2039         .name           = "mmc1_fck",
2040         .parent         = &func_64m_fclk,
2041         .clksel         = hsmmc1_fclk_sel,
2042         .init           = &omap2_init_clksel_parent,
2043         .clksel_reg     = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
2044         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2045         .ops            = &clkops_omap2_dflt,
2046         .recalc         = &omap2_clksel_recalc,
2047         .enable_reg     = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
2048         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2049         .clkdm_name     = "l3_init_clkdm",
2050 };
2051
2052 /* Merged hsmmc2_fclk into mmc2 */
2053 static struct clk mmc2_fck = {
2054         .name           = "mmc2_fck",
2055         .parent         = &func_64m_fclk,
2056         .clksel         = hsmmc1_fclk_sel,
2057         .init           = &omap2_init_clksel_parent,
2058         .clksel_reg     = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
2059         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2060         .ops            = &clkops_omap2_dflt,
2061         .recalc         = &omap2_clksel_recalc,
2062         .enable_reg     = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
2063         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2064         .clkdm_name     = "l3_init_clkdm",
2065 };
2066
2067 static struct clk mmc3_fck = {
2068         .name           = "mmc3_fck",
2069         .ops            = &clkops_omap2_dflt,
2070         .enable_reg     = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL,
2071         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2072         .clkdm_name     = "l4_per_clkdm",
2073         .parent         = &func_48m_fclk,
2074         .recalc         = &followparent_recalc,
2075 };
2076
2077 static struct clk mmc4_fck = {
2078         .name           = "mmc4_fck",
2079         .ops            = &clkops_omap2_dflt,
2080         .enable_reg     = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL,
2081         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2082         .clkdm_name     = "l4_per_clkdm",
2083         .parent         = &func_48m_fclk,
2084         .recalc         = &followparent_recalc,
2085 };
2086
2087 static struct clk mmc5_fck = {
2088         .name           = "mmc5_fck",
2089         .ops            = &clkops_omap2_dflt,
2090         .enable_reg     = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL,
2091         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2092         .clkdm_name     = "l4_per_clkdm",
2093         .parent         = &func_48m_fclk,
2094         .recalc         = &followparent_recalc,
2095 };
2096
2097 static struct clk ocp2scp_usb_phy_phy_48m = {
2098         .name           = "ocp2scp_usb_phy_phy_48m",
2099         .ops            = &clkops_omap2_dflt,
2100         .enable_reg     = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
2101         .enable_bit     = OMAP4430_OPTFCLKEN_PHY_48M_SHIFT,
2102         .clkdm_name     = "l3_init_clkdm",
2103         .parent         = &func_48m_fclk,
2104         .recalc         = &followparent_recalc,
2105 };
2106
2107 static struct clk ocp2scp_usb_phy_ick = {
2108         .name           = "ocp2scp_usb_phy_ick",
2109         .ops            = &clkops_omap2_dflt,
2110         .enable_reg     = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
2111         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2112         .clkdm_name     = "l3_init_clkdm",
2113         .parent         = &l4_div_ck,
2114         .recalc         = &followparent_recalc,
2115 };
2116
2117 static struct clk ocp_wp_noc_ick = {
2118         .name           = "ocp_wp_noc_ick",
2119         .ops            = &clkops_omap2_dflt,
2120         .enable_reg     = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL,
2121         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2122         .flags          = ENABLE_ON_INIT,
2123         .clkdm_name     = "l3_instr_clkdm",
2124         .parent         = &l3_div_ck,
2125         .recalc         = &followparent_recalc,
2126 };
2127
2128 static struct clk rng_ick = {
2129         .name           = "rng_ick",
2130         .ops            = &clkops_omap2_dflt,
2131         .enable_reg     = OMAP4430_CM_L4SEC_RNG_CLKCTRL,
2132         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2133         .clkdm_name     = "l4_secure_clkdm",
2134         .parent         = &l4_div_ck,
2135         .recalc         = &followparent_recalc,
2136 };
2137
2138 static struct clk sha2md5_fck = {
2139         .name           = "sha2md5_fck",
2140         .ops            = &clkops_omap2_dflt,
2141         .enable_reg     = OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL,
2142         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2143         .clkdm_name     = "l4_secure_clkdm",
2144         .parent         = &l3_div_ck,
2145         .recalc         = &followparent_recalc,
2146 };
2147
2148 static struct clk sl2if_ick = {
2149         .name           = "sl2if_ick",
2150         .ops            = &clkops_omap2_dflt,
2151         .enable_reg     = OMAP4430_CM_IVAHD_SL2_CLKCTRL,
2152         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2153         .clkdm_name     = "ivahd_clkdm",
2154         .parent         = &dpll_iva_m5x2_ck,
2155         .recalc         = &followparent_recalc,
2156 };
2157
2158 static struct clk slimbus1_fclk_1 = {
2159         .name           = "slimbus1_fclk_1",
2160         .ops            = &clkops_omap2_dflt,
2161         .enable_reg     = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2162         .enable_bit     = OMAP4430_OPTFCLKEN_FCLK1_SHIFT,
2163         .clkdm_name     = "abe_clkdm",
2164         .parent         = &func_24m_clk,
2165         .recalc         = &followparent_recalc,
2166 };
2167
2168 static struct clk slimbus1_fclk_0 = {
2169         .name           = "slimbus1_fclk_0",
2170         .ops            = &clkops_omap2_dflt,
2171         .enable_reg     = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2172         .enable_bit     = OMAP4430_OPTFCLKEN_FCLK0_SHIFT,
2173         .clkdm_name     = "abe_clkdm",
2174         .parent         = &abe_24m_fclk,
2175         .recalc         = &followparent_recalc,
2176 };
2177
2178 static struct clk slimbus1_fclk_2 = {
2179         .name           = "slimbus1_fclk_2",
2180         .ops            = &clkops_omap2_dflt,
2181         .enable_reg     = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2182         .enable_bit     = OMAP4430_OPTFCLKEN_FCLK2_SHIFT,
2183         .clkdm_name     = "abe_clkdm",
2184         .parent         = &pad_clks_ck,
2185         .recalc         = &followparent_recalc,
2186 };
2187
2188 static struct clk slimbus1_slimbus_clk = {
2189         .name           = "slimbus1_slimbus_clk",
2190         .ops            = &clkops_omap2_dflt,
2191         .enable_reg     = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2192         .enable_bit     = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT,
2193         .clkdm_name     = "abe_clkdm",
2194         .parent         = &slimbus_clk,
2195         .recalc         = &followparent_recalc,
2196 };
2197
2198 static struct clk slimbus1_fck = {
2199         .name           = "slimbus1_fck",
2200         .ops            = &clkops_omap2_dflt,
2201         .enable_reg     = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2202         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2203         .clkdm_name     = "abe_clkdm",
2204         .parent         = &ocp_abe_iclk,
2205         .recalc         = &followparent_recalc,
2206 };
2207
2208 static struct clk slimbus2_fclk_1 = {
2209         .name           = "slimbus2_fclk_1",
2210         .ops            = &clkops_omap2_dflt,
2211         .enable_reg     = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2212         .enable_bit     = OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT,
2213         .clkdm_name     = "l4_per_clkdm",
2214         .parent         = &per_abe_24m_fclk,
2215         .recalc         = &followparent_recalc,
2216 };
2217
2218 static struct clk slimbus2_fclk_0 = {
2219         .name           = "slimbus2_fclk_0",
2220         .ops            = &clkops_omap2_dflt,
2221         .enable_reg     = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2222         .enable_bit     = OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT,
2223         .clkdm_name     = "l4_per_clkdm",
2224         .parent         = &func_24mc_fclk,
2225         .recalc         = &followparent_recalc,
2226 };
2227
2228 static struct clk slimbus2_slimbus_clk = {
2229         .name           = "slimbus2_slimbus_clk",
2230         .ops            = &clkops_omap2_dflt,
2231         .enable_reg     = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2232         .enable_bit     = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT,
2233         .clkdm_name     = "l4_per_clkdm",
2234         .parent         = &pad_slimbus_core_clks_ck,
2235         .recalc         = &followparent_recalc,
2236 };
2237
2238 static struct clk slimbus2_fck = {
2239         .name           = "slimbus2_fck",
2240         .ops            = &clkops_omap2_dflt,
2241         .enable_reg     = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2242         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2243         .clkdm_name     = "l4_per_clkdm",
2244         .parent         = &l4_div_ck,
2245         .recalc         = &followparent_recalc,
2246 };
2247
2248 static struct clk smartreflex_core_fck = {
2249         .name           = "smartreflex_core_fck",
2250         .ops            = &clkops_omap2_dflt,
2251         .enable_reg     = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
2252         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2253         .clkdm_name     = "l4_ao_clkdm",
2254         .parent         = &l4_wkup_clk_mux_ck,
2255         .recalc         = &followparent_recalc,
2256 };
2257
2258 static struct clk smartreflex_iva_fck = {
2259         .name           = "smartreflex_iva_fck",
2260         .ops            = &clkops_omap2_dflt,
2261         .enable_reg     = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
2262         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2263         .clkdm_name     = "l4_ao_clkdm",
2264         .parent         = &l4_wkup_clk_mux_ck,
2265         .recalc         = &followparent_recalc,
2266 };
2267
2268 static struct clk smartreflex_mpu_fck = {
2269         .name           = "smartreflex_mpu_fck",
2270         .ops            = &clkops_omap2_dflt,
2271         .enable_reg     = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
2272         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2273         .clkdm_name     = "l4_ao_clkdm",
2274         .parent         = &l4_wkup_clk_mux_ck,
2275         .recalc         = &followparent_recalc,
2276 };
2277
2278 /* Merged dmt1_clk_mux into timer1 */
2279 static struct clk timer1_fck = {
2280         .name           = "timer1_fck",
2281         .parent         = &sys_clkin_ck,
2282         .clksel         = abe_dpll_bypass_clk_mux_sel,
2283         .init           = &omap2_init_clksel_parent,
2284         .clksel_reg     = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
2285         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2286         .ops            = &clkops_omap2_dflt,
2287         .recalc         = &omap2_clksel_recalc,
2288         .enable_reg     = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
2289         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2290         .clkdm_name     = "l4_wkup_clkdm",
2291 };
2292
2293 /* Merged cm2_dm10_mux into timer10 */
2294 static struct clk timer10_fck = {
2295         .name           = "timer10_fck",
2296         .parent         = &sys_clkin_ck,
2297         .clksel         = abe_dpll_bypass_clk_mux_sel,
2298         .init           = &omap2_init_clksel_parent,
2299         .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
2300         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2301         .ops            = &clkops_omap2_dflt,
2302         .recalc         = &omap2_clksel_recalc,
2303         .enable_reg     = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
2304         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2305         .clkdm_name     = "l4_per_clkdm",
2306 };
2307
2308 /* Merged cm2_dm11_mux into timer11 */
2309 static struct clk timer11_fck = {
2310         .name           = "timer11_fck",
2311         .parent         = &sys_clkin_ck,
2312         .clksel         = abe_dpll_bypass_clk_mux_sel,
2313         .init           = &omap2_init_clksel_parent,
2314         .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
2315         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2316         .ops            = &clkops_omap2_dflt,
2317         .recalc         = &omap2_clksel_recalc,
2318         .enable_reg     = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
2319         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2320         .clkdm_name     = "l4_per_clkdm",
2321 };
2322
2323 /* Merged cm2_dm2_mux into timer2 */
2324 static struct clk timer2_fck = {
2325         .name           = "timer2_fck",
2326         .parent         = &sys_clkin_ck,
2327         .clksel         = abe_dpll_bypass_clk_mux_sel,
2328         .init           = &omap2_init_clksel_parent,
2329         .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
2330         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2331         .ops            = &clkops_omap2_dflt,
2332         .recalc         = &omap2_clksel_recalc,
2333         .enable_reg     = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
2334         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2335         .clkdm_name     = "l4_per_clkdm",
2336 };
2337
2338 /* Merged cm2_dm3_mux into timer3 */
2339 static struct clk timer3_fck = {
2340         .name           = "timer3_fck",
2341         .parent         = &sys_clkin_ck,
2342         .clksel         = abe_dpll_bypass_clk_mux_sel,
2343         .init           = &omap2_init_clksel_parent,
2344         .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
2345         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2346         .ops            = &clkops_omap2_dflt,
2347         .recalc         = &omap2_clksel_recalc,
2348         .enable_reg     = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
2349         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2350         .clkdm_name     = "l4_per_clkdm",
2351 };
2352
2353 /* Merged cm2_dm4_mux into timer4 */
2354 static struct clk timer4_fck = {
2355         .name           = "timer4_fck",
2356         .parent         = &sys_clkin_ck,
2357         .clksel         = abe_dpll_bypass_clk_mux_sel,
2358         .init           = &omap2_init_clksel_parent,
2359         .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
2360         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2361         .ops            = &clkops_omap2_dflt,
2362         .recalc         = &omap2_clksel_recalc,
2363         .enable_reg     = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
2364         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2365         .clkdm_name     = "l4_per_clkdm",
2366 };
2367
2368 static const struct clksel timer5_sync_mux_sel[] = {
2369         { .parent = &syc_clk_div_ck, .rates = div_1_0_rates },
2370         { .parent = &sys_32k_ck, .rates = div_1_1_rates },
2371         { .parent = NULL },
2372 };
2373
2374 /* Merged timer5_sync_mux into timer5 */
2375 static struct clk timer5_fck = {
2376         .name           = "timer5_fck",
2377         .parent         = &syc_clk_div_ck,
2378         .clksel         = timer5_sync_mux_sel,
2379         .init           = &omap2_init_clksel_parent,
2380         .clksel_reg     = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
2381         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2382         .ops            = &clkops_omap2_dflt,
2383         .recalc         = &omap2_clksel_recalc,
2384         .enable_reg     = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
2385         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2386         .clkdm_name     = "abe_clkdm",
2387 };
2388
2389 /* Merged timer6_sync_mux into timer6 */
2390 static struct clk timer6_fck = {
2391         .name           = "timer6_fck",
2392         .parent         = &syc_clk_div_ck,
2393         .clksel         = timer5_sync_mux_sel,
2394         .init           = &omap2_init_clksel_parent,
2395         .clksel_reg     = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
2396         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2397         .ops            = &clkops_omap2_dflt,
2398         .recalc         = &omap2_clksel_recalc,
2399         .enable_reg     = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
2400         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2401         .clkdm_name     = "abe_clkdm",
2402 };
2403
2404 /* Merged timer7_sync_mux into timer7 */
2405 static struct clk timer7_fck = {
2406         .name           = "timer7_fck",
2407         .parent         = &syc_clk_div_ck,
2408         .clksel         = timer5_sync_mux_sel,
2409         .init           = &omap2_init_clksel_parent,
2410         .clksel_reg     = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
2411         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2412         .ops            = &clkops_omap2_dflt,
2413         .recalc         = &omap2_clksel_recalc,
2414         .enable_reg     = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
2415         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2416         .clkdm_name     = "abe_clkdm",
2417 };
2418
2419 /* Merged timer8_sync_mux into timer8 */
2420 static struct clk timer8_fck = {
2421         .name           = "timer8_fck",
2422         .parent         = &syc_clk_div_ck,
2423         .clksel         = timer5_sync_mux_sel,
2424         .init           = &omap2_init_clksel_parent,
2425         .clksel_reg     = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
2426         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2427         .ops            = &clkops_omap2_dflt,
2428         .recalc         = &omap2_clksel_recalc,
2429         .enable_reg     = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
2430         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2431         .clkdm_name     = "abe_clkdm",
2432 };
2433
2434 /* Merged cm2_dm9_mux into timer9 */
2435 static struct clk timer9_fck = {
2436         .name           = "timer9_fck",
2437         .parent         = &sys_clkin_ck,
2438         .clksel         = abe_dpll_bypass_clk_mux_sel,
2439         .init           = &omap2_init_clksel_parent,
2440         .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
2441         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2442         .ops            = &clkops_omap2_dflt,
2443         .recalc         = &omap2_clksel_recalc,
2444         .enable_reg     = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
2445         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2446         .clkdm_name     = "l4_per_clkdm",
2447 };
2448
2449 static struct clk uart1_fck = {
2450         .name           = "uart1_fck",
2451         .ops            = &clkops_omap2_dflt,
2452         .enable_reg     = OMAP4430_CM_L4PER_UART1_CLKCTRL,
2453         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2454         .clkdm_name     = "l4_per_clkdm",
2455         .parent         = &func_48m_fclk,
2456         .recalc         = &followparent_recalc,
2457 };
2458
2459 static struct clk uart2_fck = {
2460         .name           = "uart2_fck",
2461         .ops            = &clkops_omap2_dflt,
2462         .enable_reg     = OMAP4430_CM_L4PER_UART2_CLKCTRL,
2463         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2464         .clkdm_name     = "l4_per_clkdm",
2465         .parent         = &func_48m_fclk,
2466         .recalc         = &followparent_recalc,
2467 };
2468
2469 static struct clk uart3_fck = {
2470         .name           = "uart3_fck",
2471         .ops            = &clkops_omap2_dflt,
2472         .enable_reg     = OMAP4430_CM_L4PER_UART3_CLKCTRL,
2473         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2474         .clkdm_name     = "l4_per_clkdm",
2475         .parent         = &func_48m_fclk,
2476         .recalc         = &followparent_recalc,
2477 };
2478
2479 static struct clk uart4_fck = {
2480         .name           = "uart4_fck",
2481         .ops            = &clkops_omap2_dflt,
2482         .enable_reg     = OMAP4430_CM_L4PER_UART4_CLKCTRL,
2483         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2484         .clkdm_name     = "l4_per_clkdm",
2485         .parent         = &func_48m_fclk,
2486         .recalc         = &followparent_recalc,
2487 };
2488
2489 static struct clk usb_host_fs_fck = {
2490         .name           = "usb_host_fs_fck",
2491         .ops            = &clkops_omap2_dflt,
2492         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL,
2493         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2494         .clkdm_name     = "l3_init_clkdm",
2495         .parent         = &func_48mc_fclk,
2496         .recalc         = &followparent_recalc,
2497 };
2498
2499 static const struct clksel utmi_p1_gfclk_sel[] = {
2500         { .parent = &init_60m_fclk, .rates = div_1_0_rates },
2501         { .parent = &xclk60mhsp1_ck, .rates = div_1_1_rates },
2502         { .parent = NULL },
2503 };
2504
2505 static struct clk utmi_p1_gfclk = {
2506         .name           = "utmi_p1_gfclk",
2507         .parent         = &init_60m_fclk,
2508         .clksel         = utmi_p1_gfclk_sel,
2509         .init           = &omap2_init_clksel_parent,
2510         .clksel_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2511         .clksel_mask    = OMAP4430_CLKSEL_UTMI_P1_MASK,
2512         .ops            = &clkops_null,
2513         .recalc         = &omap2_clksel_recalc,
2514 };
2515
2516 static struct clk usb_host_hs_utmi_p1_clk = {
2517         .name           = "usb_host_hs_utmi_p1_clk",
2518         .ops            = &clkops_omap2_dflt,
2519         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2520         .enable_bit     = OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT,
2521         .clkdm_name     = "l3_init_clkdm",
2522         .parent         = &utmi_p1_gfclk,
2523         .recalc         = &followparent_recalc,
2524 };
2525
2526 static const struct clksel utmi_p2_gfclk_sel[] = {
2527         { .parent = &init_60m_fclk, .rates = div_1_0_rates },
2528         { .parent = &xclk60mhsp2_ck, .rates = div_1_1_rates },
2529         { .parent = NULL },
2530 };
2531
2532 static struct clk utmi_p2_gfclk = {
2533         .name           = "utmi_p2_gfclk",
2534         .parent         = &init_60m_fclk,
2535         .clksel         = utmi_p2_gfclk_sel,
2536         .init           = &omap2_init_clksel_parent,
2537         .clksel_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2538         .clksel_mask    = OMAP4430_CLKSEL_UTMI_P2_MASK,
2539         .ops            = &clkops_null,
2540         .recalc         = &omap2_clksel_recalc,
2541 };
2542
2543 static struct clk usb_host_hs_utmi_p2_clk = {
2544         .name           = "usb_host_hs_utmi_p2_clk",
2545         .ops            = &clkops_omap2_dflt,
2546         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2547         .enable_bit     = OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT,
2548         .clkdm_name     = "l3_init_clkdm",
2549         .parent         = &utmi_p2_gfclk,
2550         .recalc         = &followparent_recalc,
2551 };
2552
2553 static struct clk usb_host_hs_utmi_p3_clk = {
2554         .name           = "usb_host_hs_utmi_p3_clk",
2555         .ops            = &clkops_omap2_dflt,
2556         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2557         .enable_bit     = OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT,
2558         .clkdm_name     = "l3_init_clkdm",
2559         .parent         = &init_60m_fclk,
2560         .recalc         = &followparent_recalc,
2561 };
2562
2563 static struct clk usb_host_hs_hsic480m_p1_clk = {
2564         .name           = "usb_host_hs_hsic480m_p1_clk",
2565         .ops            = &clkops_omap2_dflt,
2566         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2567         .enable_bit     = OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT,
2568         .clkdm_name     = "l3_init_clkdm",
2569         .parent         = &dpll_usb_m2_ck,
2570         .recalc         = &followparent_recalc,
2571 };
2572
2573 static struct clk usb_host_hs_hsic60m_p1_clk = {
2574         .name           = "usb_host_hs_hsic60m_p1_clk",
2575         .ops            = &clkops_omap2_dflt,
2576         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2577         .enable_bit     = OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT,
2578         .clkdm_name     = "l3_init_clkdm",
2579         .parent         = &init_60m_fclk,
2580         .recalc         = &followparent_recalc,
2581 };
2582
2583 static struct clk usb_host_hs_hsic60m_p2_clk = {
2584         .name           = "usb_host_hs_hsic60m_p2_clk",
2585         .ops            = &clkops_omap2_dflt,
2586         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2587         .enable_bit     = OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT,
2588         .clkdm_name     = "l3_init_clkdm",
2589         .parent         = &init_60m_fclk,
2590         .recalc         = &followparent_recalc,
2591 };
2592
2593 static struct clk usb_host_hs_hsic480m_p2_clk = {
2594         .name           = "usb_host_hs_hsic480m_p2_clk",
2595         .ops            = &clkops_omap2_dflt,
2596         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2597         .enable_bit     = OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT,
2598         .clkdm_name     = "l3_init_clkdm",
2599         .parent         = &dpll_usb_m2_ck,
2600         .recalc         = &followparent_recalc,
2601 };
2602
2603 static struct clk usb_host_hs_func48mclk = {
2604         .name           = "usb_host_hs_func48mclk",
2605         .ops            = &clkops_omap2_dflt,
2606         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2607         .enable_bit     = OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT,
2608         .clkdm_name     = "l3_init_clkdm",
2609         .parent         = &func_48mc_fclk,
2610         .recalc         = &followparent_recalc,
2611 };
2612
2613 static struct clk usb_host_hs_fck = {
2614         .name           = "usb_host_hs_fck",
2615         .ops            = &clkops_omap2_dflt,
2616         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2617         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2618         .clkdm_name     = "l3_init_clkdm",
2619         .parent         = &init_60m_fclk,
2620         .recalc         = &followparent_recalc,
2621 };
2622
2623 static const struct clksel otg_60m_gfclk_sel[] = {
2624         { .parent = &utmi_phy_clkout_ck, .rates = div_1_0_rates },
2625         { .parent = &xclk60motg_ck, .rates = div_1_1_rates },
2626         { .parent = NULL },
2627 };
2628
2629 static struct clk otg_60m_gfclk = {
2630         .name           = "otg_60m_gfclk",
2631         .parent         = &utmi_phy_clkout_ck,
2632         .clksel         = otg_60m_gfclk_sel,
2633         .init           = &omap2_init_clksel_parent,
2634         .clksel_reg     = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2635         .clksel_mask    = OMAP4430_CLKSEL_60M_MASK,
2636         .ops            = &clkops_null,
2637         .recalc         = &omap2_clksel_recalc,
2638 };
2639
2640 static struct clk usb_otg_hs_xclk = {
2641         .name           = "usb_otg_hs_xclk",
2642         .ops            = &clkops_omap2_dflt,
2643         .enable_reg     = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2644         .enable_bit     = OMAP4430_OPTFCLKEN_XCLK_SHIFT,
2645         .clkdm_name     = "l3_init_clkdm",
2646         .parent         = &otg_60m_gfclk,
2647         .recalc         = &followparent_recalc,
2648 };
2649
2650 static struct clk usb_otg_hs_ick = {
2651         .name           = "usb_otg_hs_ick",
2652         .ops            = &clkops_omap2_dflt,
2653         .enable_reg     = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2654         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2655         .clkdm_name     = "l3_init_clkdm",
2656         .parent         = &l3_div_ck,
2657         .recalc         = &followparent_recalc,
2658 };
2659
2660 static struct clk usb_phy_cm_clk32k = {
2661         .name           = "usb_phy_cm_clk32k",
2662         .ops            = &clkops_omap2_dflt,
2663         .enable_reg     = OMAP4430_CM_ALWON_USBPHY_CLKCTRL,
2664         .enable_bit     = OMAP4430_OPTFCLKEN_CLK32K_SHIFT,
2665         .clkdm_name     = "l4_ao_clkdm",
2666         .parent         = &sys_32k_ck,
2667         .recalc         = &followparent_recalc,
2668 };
2669
2670 static struct clk usb_tll_hs_usb_ch2_clk = {
2671         .name           = "usb_tll_hs_usb_ch2_clk",
2672         .ops            = &clkops_omap2_dflt,
2673         .enable_reg     = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2674         .enable_bit     = OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT,
2675         .clkdm_name     = "l3_init_clkdm",
2676         .parent         = &init_60m_fclk,
2677         .recalc         = &followparent_recalc,
2678 };
2679
2680 static struct clk usb_tll_hs_usb_ch0_clk = {
2681         .name           = "usb_tll_hs_usb_ch0_clk",
2682         .ops            = &clkops_omap2_dflt,
2683         .enable_reg     = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2684         .enable_bit     = OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT,
2685         .clkdm_name     = "l3_init_clkdm",
2686         .parent         = &init_60m_fclk,
2687         .recalc         = &followparent_recalc,
2688 };
2689
2690 static struct clk usb_tll_hs_usb_ch1_clk = {
2691         .name           = "usb_tll_hs_usb_ch1_clk",
2692         .ops            = &clkops_omap2_dflt,
2693         .enable_reg     = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2694         .enable_bit     = OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT,
2695         .clkdm_name     = "l3_init_clkdm",
2696         .parent         = &init_60m_fclk,
2697         .recalc         = &followparent_recalc,
2698 };
2699
2700 static struct clk usb_tll_hs_ick = {
2701         .name           = "usb_tll_hs_ick",
2702         .ops            = &clkops_omap2_dflt,
2703         .enable_reg     = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2704         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2705         .clkdm_name     = "l3_init_clkdm",
2706         .parent         = &l4_div_ck,
2707         .recalc         = &followparent_recalc,
2708 };
2709
2710 static const struct clksel_rate div2_14to18_rates[] = {
2711         { .div = 14, .val = 0, .flags = RATE_IN_4430 },
2712         { .div = 18, .val = 1, .flags = RATE_IN_4430 },
2713         { .div = 0 },
2714 };
2715
2716 static const struct clksel usim_fclk_div[] = {
2717         { .parent = &dpll_per_m4x2_ck, .rates = div2_14to18_rates },
2718         { .parent = NULL },
2719 };
2720
2721 static struct clk usim_ck = {
2722         .name           = "usim_ck",
2723         .parent         = &dpll_per_m4x2_ck,
2724         .clksel         = usim_fclk_div,
2725         .clksel_reg     = OMAP4430_CM_WKUP_USIM_CLKCTRL,
2726         .clksel_mask    = OMAP4430_CLKSEL_DIV_MASK,
2727         .ops            = &clkops_null,
2728         .recalc         = &omap2_clksel_recalc,
2729         .round_rate     = &omap2_clksel_round_rate,
2730         .set_rate       = &omap2_clksel_set_rate,
2731 };
2732
2733 static struct clk usim_fclk = {
2734         .name           = "usim_fclk",
2735         .ops            = &clkops_omap2_dflt,
2736         .enable_reg     = OMAP4430_CM_WKUP_USIM_CLKCTRL,
2737         .enable_bit     = OMAP4430_OPTFCLKEN_FCLK_SHIFT,
2738         .clkdm_name     = "l4_wkup_clkdm",
2739         .parent         = &usim_ck,
2740         .recalc         = &followparent_recalc,
2741 };
2742
2743 static struct clk usim_fck = {
2744         .name           = "usim_fck",
2745         .ops            = &clkops_omap2_dflt,
2746         .enable_reg     = OMAP4430_CM_WKUP_USIM_CLKCTRL,
2747         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2748         .clkdm_name     = "l4_wkup_clkdm",
2749         .parent         = &sys_32k_ck,
2750         .recalc         = &followparent_recalc,
2751 };
2752
2753 static struct clk wd_timer2_fck = {
2754         .name           = "wd_timer2_fck",
2755         .ops            = &clkops_omap2_dflt,
2756         .enable_reg     = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
2757         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2758         .clkdm_name     = "l4_wkup_clkdm",
2759         .parent         = &sys_32k_ck,
2760         .recalc         = &followparent_recalc,
2761 };
2762
2763 static struct clk wd_timer3_fck = {
2764         .name           = "wd_timer3_fck",
2765         .ops            = &clkops_omap2_dflt,
2766         .enable_reg     = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
2767         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2768         .clkdm_name     = "abe_clkdm",
2769         .parent         = &sys_32k_ck,
2770         .recalc         = &followparent_recalc,
2771 };
2772
2773 /* Remaining optional clocks */
2774 static const struct clksel stm_clk_div_div[] = {
2775         { .parent = &pmd_stm_clock_mux_ck, .rates = div3_1to4_rates },
2776         { .parent = NULL },
2777 };
2778
2779 static struct clk stm_clk_div_ck = {
2780         .name           = "stm_clk_div_ck",
2781         .parent         = &pmd_stm_clock_mux_ck,
2782         .clksel         = stm_clk_div_div,
2783         .clksel_reg     = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
2784         .clksel_mask    = OMAP4430_CLKSEL_PMD_STM_CLK_MASK,
2785         .ops            = &clkops_null,
2786         .recalc         = &omap2_clksel_recalc,
2787         .round_rate     = &omap2_clksel_round_rate,
2788         .set_rate       = &omap2_clksel_set_rate,
2789 };
2790
2791 static const struct clksel trace_clk_div_div[] = {
2792         { .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates },
2793         { .parent = NULL },
2794 };
2795
2796 static struct clk trace_clk_div_ck = {
2797         .name           = "trace_clk_div_ck",
2798         .parent         = &pmd_trace_clk_mux_ck,
2799         .clksel         = trace_clk_div_div,
2800         .clksel_reg     = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
2801         .clksel_mask    = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK,
2802         .ops            = &clkops_null,
2803         .recalc         = &omap2_clksel_recalc,
2804         .round_rate     = &omap2_clksel_round_rate,
2805         .set_rate       = &omap2_clksel_set_rate,
2806 };
2807
2808 /* SCRM aux clk nodes */
2809
2810 static const struct clksel auxclk_sel[] = {
2811         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
2812         { .parent = &dpll_core_m3x2_ck, .rates = div_1_1_rates },
2813         { .parent = &dpll_per_m3x2_ck, .rates = div_1_2_rates },
2814         { .parent = NULL },
2815 };
2816
2817 static struct clk auxclk0_ck = {
2818         .name           = "auxclk0_ck",
2819         .parent         = &sys_clkin_ck,
2820         .init           = &omap2_init_clksel_parent,
2821         .ops            = &clkops_omap2_dflt,
2822         .clksel         = auxclk_sel,
2823         .clksel_reg     = OMAP4_SCRM_AUXCLK0,
2824         .clksel_mask    = OMAP4_SRCSELECT_MASK,
2825         .recalc         = &omap2_clksel_recalc,
2826         .enable_reg     = OMAP4_SCRM_AUXCLK0,
2827         .enable_bit     = OMAP4_ENABLE_SHIFT,
2828 };
2829
2830 static struct clk auxclk1_ck = {
2831         .name           = "auxclk1_ck",
2832         .parent         = &sys_clkin_ck,
2833         .init           = &omap2_init_clksel_parent,
2834         .ops            = &clkops_omap2_dflt,
2835         .clksel         = auxclk_sel,
2836         .clksel_reg     = OMAP4_SCRM_AUXCLK1,
2837         .clksel_mask    = OMAP4_SRCSELECT_MASK,
2838         .recalc         = &omap2_clksel_recalc,
2839         .enable_reg     = OMAP4_SCRM_AUXCLK1,
2840         .enable_bit     = OMAP4_ENABLE_SHIFT,
2841 };
2842
2843 static struct clk auxclk2_ck = {
2844         .name           = "auxclk2_ck",
2845         .parent         = &sys_clkin_ck,
2846         .init           = &omap2_init_clksel_parent,
2847         .ops            = &clkops_omap2_dflt,
2848         .clksel         = auxclk_sel,
2849         .clksel_reg     = OMAP4_SCRM_AUXCLK2,
2850         .clksel_mask    = OMAP4_SRCSELECT_MASK,
2851         .recalc         = &omap2_clksel_recalc,
2852         .enable_reg     = OMAP4_SCRM_AUXCLK2,
2853         .enable_bit     = OMAP4_ENABLE_SHIFT,
2854 };
2855
2856 static struct clk auxclk3_ck = {
2857         .name           = "auxclk3_ck",
2858         .parent         = &sys_clkin_ck,
2859         .init           = &omap2_init_clksel_parent,
2860         .ops            = &clkops_omap2_dflt,
2861         .clksel         = auxclk_sel,
2862         .clksel_reg     = OMAP4_SCRM_AUXCLK3,
2863         .clksel_mask    = OMAP4_SRCSELECT_MASK,
2864         .recalc         = &omap2_clksel_recalc,
2865         .enable_reg     = OMAP4_SCRM_AUXCLK3,
2866         .enable_bit     = OMAP4_ENABLE_SHIFT,
2867 };
2868
2869 static struct clk auxclk4_ck = {
2870         .name           = "auxclk4_ck",
2871         .parent         = &sys_clkin_ck,
2872         .init           = &omap2_init_clksel_parent,
2873         .ops            = &clkops_omap2_dflt,
2874         .clksel         = auxclk_sel,
2875         .clksel_reg     = OMAP4_SCRM_AUXCLK4,
2876         .clksel_mask    = OMAP4_SRCSELECT_MASK,
2877         .recalc         = &omap2_clksel_recalc,
2878         .enable_reg     = OMAP4_SCRM_AUXCLK4,
2879         .enable_bit     = OMAP4_ENABLE_SHIFT,
2880 };
2881
2882 static struct clk auxclk5_ck = {
2883         .name           = "auxclk5_ck",
2884         .parent         = &sys_clkin_ck,
2885         .init           = &omap2_init_clksel_parent,
2886         .ops            = &clkops_omap2_dflt,
2887         .clksel         = auxclk_sel,
2888         .clksel_reg     = OMAP4_SCRM_AUXCLK5,
2889         .clksel_mask    = OMAP4_SRCSELECT_MASK,
2890         .recalc         = &omap2_clksel_recalc,
2891         .enable_reg     = OMAP4_SCRM_AUXCLK5,
2892         .enable_bit     = OMAP4_ENABLE_SHIFT,
2893 };
2894
2895 static const struct clksel auxclkreq_sel[] = {
2896         { .parent = &auxclk0_ck, .rates = div_1_0_rates },
2897         { .parent = &auxclk1_ck, .rates = div_1_1_rates },
2898         { .parent = &auxclk2_ck, .rates = div_1_2_rates },
2899         { .parent = &auxclk3_ck, .rates = div_1_3_rates },
2900         { .parent = &auxclk4_ck, .rates = div_1_4_rates },
2901         { .parent = &auxclk5_ck, .rates = div_1_5_rates },
2902         { .parent = NULL },
2903 };
2904
2905 static struct clk auxclkreq0_ck = {
2906         .name           = "auxclkreq0_ck",
2907         .parent         = &auxclk0_ck,
2908         .init           = &omap2_init_clksel_parent,
2909         .ops            = &clkops_null,
2910         .clksel         = auxclkreq_sel,
2911         .clksel_reg     = OMAP4_SCRM_AUXCLKREQ0,
2912         .clksel_mask    = OMAP4_MAPPING_MASK,
2913         .recalc         = &omap2_clksel_recalc,
2914 };
2915
2916 static struct clk auxclkreq1_ck = {
2917         .name           = "auxclkreq1_ck",
2918         .parent         = &auxclk1_ck,
2919         .init           = &omap2_init_clksel_parent,
2920         .ops            = &clkops_null,
2921         .clksel         = auxclkreq_sel,
2922         .clksel_reg     = OMAP4_SCRM_AUXCLKREQ1,
2923         .clksel_mask    = OMAP4_MAPPING_MASK,
2924         .recalc         = &omap2_clksel_recalc,
2925 };
2926
2927 static struct clk auxclkreq2_ck = {
2928         .name           = "auxclkreq2_ck",
2929         .parent         = &auxclk2_ck,
2930         .init           = &omap2_init_clksel_parent,
2931         .ops            = &clkops_null,
2932         .clksel         = auxclkreq_sel,
2933         .clksel_reg     = OMAP4_SCRM_AUXCLKREQ2,
2934         .clksel_mask    = OMAP4_MAPPING_MASK,
2935         .recalc         = &omap2_clksel_recalc,
2936 };
2937
2938 static struct clk auxclkreq3_ck = {
2939         .name           = "auxclkreq3_ck",
2940         .parent         = &auxclk3_ck,
2941         .init           = &omap2_init_clksel_parent,
2942         .ops            = &clkops_null,
2943         .clksel         = auxclkreq_sel,
2944         .clksel_reg     = OMAP4_SCRM_AUXCLKREQ3,
2945         .clksel_mask    = OMAP4_MAPPING_MASK,
2946         .recalc         = &omap2_clksel_recalc,
2947 };
2948
2949 static struct clk auxclkreq4_ck = {
2950         .name           = "auxclkreq4_ck",
2951         .parent         = &auxclk4_ck,
2952         .init           = &omap2_init_clksel_parent,
2953         .ops            = &clkops_null,
2954         .clksel         = auxclkreq_sel,
2955         .clksel_reg     = OMAP4_SCRM_AUXCLKREQ4,
2956         .clksel_mask    = OMAP4_MAPPING_MASK,
2957         .recalc         = &omap2_clksel_recalc,
2958 };
2959
2960 static struct clk auxclkreq5_ck = {
2961         .name           = "auxclkreq5_ck",
2962         .parent         = &auxclk5_ck,
2963         .init           = &omap2_init_clksel_parent,
2964         .ops            = &clkops_null,
2965         .clksel         = auxclkreq_sel,
2966         .clksel_reg     = OMAP4_SCRM_AUXCLKREQ5,
2967         .clksel_mask    = OMAP4_MAPPING_MASK,
2968         .recalc         = &omap2_clksel_recalc,
2969 };
2970
2971 /*
2972  * clkdev
2973  */
2974
2975 static struct omap_clk omap44xx_clks[] = {
2976         CLK(NULL,       "extalt_clkin_ck",              &extalt_clkin_ck,       CK_443X),
2977         CLK(NULL,       "pad_clks_ck",                  &pad_clks_ck,   CK_443X),
2978         CLK(NULL,       "pad_slimbus_core_clks_ck",     &pad_slimbus_core_clks_ck,      CK_443X),
2979         CLK(NULL,       "secure_32k_clk_src_ck",        &secure_32k_clk_src_ck, CK_443X),
2980         CLK(NULL,       "slimbus_clk",                  &slimbus_clk,   CK_443X),
2981         CLK(NULL,       "sys_32k_ck",                   &sys_32k_ck,    CK_443X),
2982         CLK(NULL,       "virt_12000000_ck",             &virt_12000000_ck,      CK_443X),
2983         CLK(NULL,       "virt_13000000_ck",             &virt_13000000_ck,      CK_443X),
2984         CLK(NULL,       "virt_16800000_ck",             &virt_16800000_ck,      CK_443X),
2985         CLK(NULL,       "virt_19200000_ck",             &virt_19200000_ck,      CK_443X),
2986         CLK(NULL,       "virt_26000000_ck",             &virt_26000000_ck,      CK_443X),
2987         CLK(NULL,       "virt_27000000_ck",             &virt_27000000_ck,      CK_443X),
2988         CLK(NULL,       "virt_38400000_ck",             &virt_38400000_ck,      CK_443X),
2989         CLK(NULL,       "sys_clkin_ck",                 &sys_clkin_ck,  CK_443X),
2990         CLK(NULL,       "tie_low_clock_ck",             &tie_low_clock_ck,      CK_443X),
2991         CLK(NULL,       "utmi_phy_clkout_ck",           &utmi_phy_clkout_ck,    CK_443X),
2992         CLK(NULL,       "xclk60mhsp1_ck",               &xclk60mhsp1_ck,        CK_443X),
2993         CLK(NULL,       "xclk60mhsp2_ck",               &xclk60mhsp2_ck,        CK_443X),
2994         CLK(NULL,       "xclk60motg_ck",                &xclk60motg_ck, CK_443X),
2995         CLK(NULL,       "abe_dpll_bypass_clk_mux_ck",   &abe_dpll_bypass_clk_mux_ck,    CK_443X),
2996         CLK(NULL,       "abe_dpll_refclk_mux_ck",       &abe_dpll_refclk_mux_ck,        CK_443X),
2997         CLK(NULL,       "dpll_abe_ck",                  &dpll_abe_ck,   CK_443X),
2998         CLK(NULL,       "dpll_abe_x2_ck",               &dpll_abe_x2_ck,        CK_443X),
2999         CLK(NULL,       "dpll_abe_m2x2_ck",             &dpll_abe_m2x2_ck,      CK_443X),
3000         CLK(NULL,       "abe_24m_fclk",                 &abe_24m_fclk,  CK_443X),
3001         CLK(NULL,       "abe_clk",                      &abe_clk,       CK_443X),
3002         CLK(NULL,       "aess_fclk",                    &aess_fclk,     CK_443X),
3003         CLK(NULL,       "dpll_abe_m3x2_ck",             &dpll_abe_m3x2_ck,      CK_443X),
3004         CLK(NULL,       "core_hsd_byp_clk_mux_ck",      &core_hsd_byp_clk_mux_ck,       CK_443X),
3005         CLK(NULL,       "dpll_core_ck",                 &dpll_core_ck,  CK_443X),
3006         CLK(NULL,       "dpll_core_x2_ck",              &dpll_core_x2_ck,       CK_443X),
3007         CLK(NULL,       "dpll_core_m6x2_ck",            &dpll_core_m6x2_ck,     CK_443X),
3008         CLK(NULL,       "dbgclk_mux_ck",                &dbgclk_mux_ck, CK_443X),
3009         CLK(NULL,       "dpll_core_m2_ck",              &dpll_core_m2_ck,       CK_443X),
3010         CLK(NULL,       "ddrphy_ck",                    &ddrphy_ck,     CK_443X),
3011         CLK(NULL,       "dpll_core_m5x2_ck",            &dpll_core_m5x2_ck,     CK_443X),
3012         CLK(NULL,       "div_core_ck",                  &div_core_ck,   CK_443X),
3013         CLK(NULL,       "div_iva_hs_clk",               &div_iva_hs_clk,        CK_443X),
3014         CLK(NULL,       "div_mpu_hs_clk",               &div_mpu_hs_clk,        CK_443X),
3015         CLK(NULL,       "dpll_core_m4x2_ck",            &dpll_core_m4x2_ck,     CK_443X),
3016         CLK(NULL,       "dll_clk_div_ck",               &dll_clk_div_ck,        CK_443X),
3017         CLK(NULL,       "dpll_abe_m2_ck",               &dpll_abe_m2_ck,        CK_443X),
3018         CLK(NULL,       "dpll_core_m3x2_ck",            &dpll_core_m3x2_ck,     CK_443X),
3019         CLK(NULL,       "dpll_core_m7x2_ck",            &dpll_core_m7x2_ck,     CK_443X),
3020         CLK(NULL,       "iva_hsd_byp_clk_mux_ck",       &iva_hsd_byp_clk_mux_ck,        CK_443X),
3021         CLK(NULL,       "dpll_iva_ck",                  &dpll_iva_ck,   CK_443X),
3022         CLK(NULL,       "dpll_iva_x2_ck",               &dpll_iva_x2_ck,        CK_443X),
3023         CLK(NULL,       "dpll_iva_m4x2_ck",             &dpll_iva_m4x2_ck,      CK_443X),
3024         CLK(NULL,       "dpll_iva_m5x2_ck",             &dpll_iva_m5x2_ck,      CK_443X),
3025         CLK(NULL,       "dpll_mpu_ck",                  &dpll_mpu_ck,   CK_443X),
3026         CLK(NULL,       "dpll_mpu_m2_ck",               &dpll_mpu_m2_ck,        CK_443X),
3027         CLK(NULL,       "per_hs_clk_div_ck",            &per_hs_clk_div_ck,     CK_443X),
3028         CLK(NULL,       "per_hsd_byp_clk_mux_ck",       &per_hsd_byp_clk_mux_ck,        CK_443X),
3029         CLK(NULL,       "dpll_per_ck",                  &dpll_per_ck,   CK_443X),
3030         CLK(NULL,       "dpll_per_m2_ck",               &dpll_per_m2_ck,        CK_443X),
3031         CLK(NULL,       "dpll_per_x2_ck",               &dpll_per_x2_ck,        CK_443X),
3032         CLK(NULL,       "dpll_per_m2x2_ck",             &dpll_per_m2x2_ck,      CK_443X),
3033         CLK(NULL,       "dpll_per_m3x2_ck",             &dpll_per_m3x2_ck,      CK_443X),
3034         CLK(NULL,       "dpll_per_m4x2_ck",             &dpll_per_m4x2_ck,      CK_443X),
3035         CLK(NULL,       "dpll_per_m5x2_ck",             &dpll_per_m5x2_ck,      CK_443X),
3036         CLK(NULL,       "dpll_per_m6x2_ck",             &dpll_per_m6x2_ck,      CK_443X),
3037         CLK(NULL,       "dpll_per_m7x2_ck",             &dpll_per_m7x2_ck,      CK_443X),
3038         CLK(NULL,       "usb_hs_clk_div_ck",            &usb_hs_clk_div_ck,     CK_443X),
3039         CLK(NULL,       "dpll_usb_ck",                  &dpll_usb_ck,   CK_443X),
3040         CLK(NULL,       "dpll_usb_clkdcoldo_ck",        &dpll_usb_clkdcoldo_ck, CK_443X),
3041         CLK(NULL,       "dpll_usb_m2_ck",               &dpll_usb_m2_ck,        CK_443X),
3042         CLK(NULL,       "ducati_clk_mux_ck",            &ducati_clk_mux_ck,     CK_443X),
3043         CLK(NULL,       "func_12m_fclk",                &func_12m_fclk, CK_443X),
3044         CLK(NULL,       "func_24m_clk",                 &func_24m_clk,  CK_443X),
3045         CLK(NULL,       "func_24mc_fclk",               &func_24mc_fclk,        CK_443X),
3046         CLK(NULL,       "func_48m_fclk",                &func_48m_fclk, CK_443X),
3047         CLK(NULL,       "func_48mc_fclk",               &func_48mc_fclk,        CK_443X),
3048         CLK(NULL,       "func_64m_fclk",                &func_64m_fclk, CK_443X),
3049         CLK(NULL,       "func_96m_fclk",                &func_96m_fclk, CK_443X),
3050         CLK(NULL,       "init_60m_fclk",                &init_60m_fclk, CK_443X),
3051         CLK(NULL,       "l3_div_ck",                    &l3_div_ck,     CK_443X),
3052         CLK(NULL,       "l4_div_ck",                    &l4_div_ck,     CK_443X),
3053         CLK(NULL,       "lp_clk_div_ck",                &lp_clk_div_ck, CK_443X),
3054         CLK(NULL,       "l4_wkup_clk_mux_ck",           &l4_wkup_clk_mux_ck,    CK_443X),
3055         CLK(NULL,       "ocp_abe_iclk",                 &ocp_abe_iclk,  CK_443X),
3056         CLK(NULL,       "per_abe_24m_fclk",             &per_abe_24m_fclk,      CK_443X),
3057         CLK(NULL,       "per_abe_nc_fclk",              &per_abe_nc_fclk,       CK_443X),
3058         CLK(NULL,       "pmd_stm_clock_mux_ck",         &pmd_stm_clock_mux_ck,  CK_443X),
3059         CLK(NULL,       "pmd_trace_clk_mux_ck",         &pmd_trace_clk_mux_ck,  CK_443X),
3060         CLK(NULL,       "syc_clk_div_ck",               &syc_clk_div_ck,        CK_443X),
3061         CLK(NULL,       "aes1_fck",                     &aes1_fck,      CK_443X),
3062         CLK(NULL,       "aes2_fck",                     &aes2_fck,      CK_443X),
3063         CLK(NULL,       "aess_fck",                     &aess_fck,      CK_443X),
3064         CLK(NULL,       "bandgap_fclk",                 &bandgap_fclk,  CK_443X),
3065         CLK(NULL,       "bandgap_ts_fclk",              &bandgap_ts_fclk,       CK_446X),
3066         CLK(NULL,       "des3des_fck",                  &des3des_fck,   CK_443X),
3067         CLK(NULL,       "div_ts_ck",                    &div_ts_ck,     CK_446X),
3068         CLK(NULL,       "dmic_sync_mux_ck",             &dmic_sync_mux_ck,      CK_443X),
3069         CLK(NULL,       "dmic_fck",                     &dmic_fck,      CK_443X),
3070         CLK(NULL,       "dsp_fck",                      &dsp_fck,       CK_443X),
3071         CLK("omapdss_dss",      "sys_clk",                      &dss_sys_clk,   CK_443X),
3072         CLK("omapdss_dss",      "tv_clk",                       &dss_tv_clk,    CK_443X),
3073         CLK("omapdss_dss",      "video_clk",                    &dss_48mhz_clk, CK_443X),
3074         CLK("omapdss_dss",      "fck",                          &dss_dss_clk,   CK_443X),
3075         CLK("omapdss_dss",      "ick",                          &dss_fck,       CK_443X),
3076         CLK(NULL,       "efuse_ctrl_cust_fck",          &efuse_ctrl_cust_fck,   CK_443X),
3077         CLK(NULL,       "emif1_fck",                    &emif1_fck,     CK_443X),
3078         CLK(NULL,       "emif2_fck",                    &emif2_fck,     CK_443X),
3079         CLK(NULL,       "fdif_fck",                     &fdif_fck,      CK_443X),
3080         CLK(NULL,       "fpka_fck",                     &fpka_fck,      CK_443X),
3081         CLK(NULL,       "gpio1_dbclk",                  &gpio1_dbclk,   CK_443X),
3082         CLK(NULL,       "gpio1_ick",                    &gpio1_ick,     CK_443X),
3083         CLK(NULL,       "gpio2_dbclk",                  &gpio2_dbclk,   CK_443X),
3084         CLK(NULL,       "gpio2_ick",                    &gpio2_ick,     CK_443X),
3085         CLK(NULL,       "gpio3_dbclk",                  &gpio3_dbclk,   CK_443X),
3086         CLK(NULL,       "gpio3_ick",                    &gpio3_ick,     CK_443X),
3087         CLK(NULL,       "gpio4_dbclk",                  &gpio4_dbclk,   CK_443X),
3088         CLK(NULL,       "gpio4_ick",                    &gpio4_ick,     CK_443X),
3089         CLK(NULL,       "gpio5_dbclk",                  &gpio5_dbclk,   CK_443X),
3090         CLK(NULL,       "gpio5_ick",                    &gpio5_ick,     CK_443X),
3091  &nbs