Merge master.kernel.org:/home/rmk/linux-2.6-arm
[linux-2.6.git] / arch / arm / mach-omap1 / pm.c
1 /*
2  * linux/arch/arm/mach-omap1/pm.c
3  *
4  * OMAP Power Management Routines
5  *
6  * Original code for the SA11x0:
7  * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
8  *
9  * Modified for the PXA250 by Nicolas Pitre:
10  * Copyright (c) 2002 Monta Vista Software, Inc.
11  *
12  * Modified for the OMAP1510 by David Singleton:
13  * Copyright (c) 2002 Monta Vista Software, Inc.
14  *
15  * Cleanup 2004 for OMAP1510/1610 by Dirk Behme <dirk.behme@de.bosch.com>
16  *
17  * This program is free software; you can redistribute it and/or modify it
18  * under the terms of the GNU General Public License as published by the
19  * Free Software Foundation; either version 2 of the License, or (at your
20  * option) any later version.
21  *
22  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
23  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32  *
33  * You should have received a copy of the GNU General Public License along
34  * with this program; if not, write to the Free Software Foundation, Inc.,
35  * 675 Mass Ave, Cambridge, MA 02139, USA.
36  */
37
38 #include <linux/pm.h>
39 #include <linux/sched.h>
40 #include <linux/proc_fs.h>
41 #include <linux/pm.h>
42 #include <linux/interrupt.h>
43 #include <linux/sysfs.h>
44 #include <linux/module.h>
45
46 #include <asm/io.h>
47 #include <asm/irq.h>
48 #include <asm/atomic.h>
49 #include <asm/mach/time.h>
50 #include <asm/mach/irq.h>
51 #include <asm/mach-types.h>
52
53 #include <asm/arch/cpu.h>
54 #include <asm/arch/irqs.h>
55 #include <asm/arch/clock.h>
56 #include <asm/arch/sram.h>
57 #include <asm/arch/tc.h>
58 #include <asm/arch/pm.h>
59 #include <asm/arch/mux.h>
60 #include <asm/arch/dma.h>
61 #include <asm/arch/dsp_common.h>
62 #include <asm/arch/dmtimer.h>
63
64 static unsigned int arm_sleep_save[ARM_SLEEP_SAVE_SIZE];
65 static unsigned short dsp_sleep_save[DSP_SLEEP_SAVE_SIZE];
66 static unsigned short ulpd_sleep_save[ULPD_SLEEP_SAVE_SIZE];
67 static unsigned int mpui730_sleep_save[MPUI730_SLEEP_SAVE_SIZE];
68 static unsigned int mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_SIZE];
69 static unsigned int mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_SIZE];
70
71 static unsigned short enable_dyn_sleep = 1;
72
73 static ssize_t omap_pm_sleep_while_idle_show(struct kset *kset, char *buf)
74 {
75         return sprintf(buf, "%hu\n", enable_dyn_sleep);
76 }
77
78 static ssize_t omap_pm_sleep_while_idle_store(struct kset *kset,
79                                               const char * buf,
80                                               size_t n)
81 {
82         unsigned short value;
83         if (sscanf(buf, "%hu", &value) != 1 ||
84             (value != 0 && value != 1)) {
85                 printk(KERN_ERR "idle_sleep_store: Invalid value\n");
86                 return -EINVAL;
87         }
88         enable_dyn_sleep = value;
89         return n;
90 }
91
92 static struct subsys_attribute sleep_while_idle_attr = {
93         .attr   = {
94                 .name = __stringify(sleep_while_idle),
95                 .mode = 0644,
96         },
97         .show   = omap_pm_sleep_while_idle_show,
98         .store  = omap_pm_sleep_while_idle_store,
99 };
100
101 extern struct kset power_subsys;
102 static void (*omap_sram_idle)(void) = NULL;
103 static void (*omap_sram_suspend)(unsigned long r0, unsigned long r1) = NULL;
104
105 /*
106  * Let's power down on idle, but only if we are really
107  * idle, because once we start down the path of
108  * going idle we continue to do idle even if we get
109  * a clock tick interrupt . .
110  */
111 void omap_pm_idle(void)
112 {
113         extern __u32 arm_idlect1_mask;
114         __u32 use_idlect1 = arm_idlect1_mask;
115 #ifndef CONFIG_OMAP_MPU_TIMER
116         int do_sleep;
117 #endif
118
119         local_irq_disable();
120         local_fiq_disable();
121         if (need_resched()) {
122                 local_fiq_enable();
123                 local_irq_enable();
124                 return;
125         }
126
127         /*
128          * Since an interrupt may set up a timer, we don't want to
129          * reprogram the hardware timer with interrupts enabled.
130          * Re-enable interrupts only after returning from idle.
131          */
132         timer_dyn_reprogram();
133
134 #ifdef CONFIG_OMAP_MPU_TIMER
135 #warning Enable 32kHz OS timer in order to allow sleep states in idle
136         use_idlect1 = use_idlect1 & ~(1 << 9);
137 #else
138
139         do_sleep = 0;
140         while (enable_dyn_sleep) {
141
142 #ifdef CONFIG_CBUS_TAHVO_USB
143                 extern int vbus_active;
144                 /* Clock requirements? */
145                 if (vbus_active)
146                         break;
147 #endif
148                 do_sleep = 1;
149                 break;
150         }
151
152 #ifdef CONFIG_OMAP_DM_TIMER
153         use_idlect1 = omap_dm_timer_modify_idlect_mask(use_idlect1);
154 #endif
155
156         if (omap_dma_running()) {
157                 use_idlect1 &= ~(1 << 6);
158                 if (omap_lcd_dma_ext_running())
159                         use_idlect1 &= ~(1 << 12);
160         }
161
162         /* We should be able to remove the do_sleep variable and multiple
163          * tests above as soon as drivers, timer and DMA code have been fixed.
164          * Even the sleep block count should become obsolete. */
165         if ((use_idlect1 != ~0) || !do_sleep) {
166
167                 __u32 saved_idlect1 = omap_readl(ARM_IDLECT1);
168                 if (cpu_is_omap15xx())
169                         use_idlect1 &= OMAP1510_BIG_SLEEP_REQUEST;
170                 else
171                         use_idlect1 &= OMAP1610_IDLECT1_SLEEP_VAL;
172                 omap_writel(use_idlect1, ARM_IDLECT1);
173                 __asm__ volatile ("mcr  p15, 0, r0, c7, c0, 4");
174                 omap_writel(saved_idlect1, ARM_IDLECT1);
175
176                 local_fiq_enable();
177                 local_irq_enable();
178                 return;
179         }
180         omap_sram_suspend(omap_readl(ARM_IDLECT1),
181                           omap_readl(ARM_IDLECT2));
182 #endif
183
184         local_fiq_enable();
185         local_irq_enable();
186 }
187
188 /*
189  * Configuration of the wakeup event is board specific. For the
190  * moment we put it into this helper function. Later it may move
191  * to board specific files.
192  */
193 static void omap_pm_wakeup_setup(void)
194 {
195         u32 level1_wake = 0;
196         u32 level2_wake = OMAP_IRQ_BIT(INT_UART2);
197
198         /*
199          * Turn off all interrupts except GPIO bank 1, L1-2nd level cascade,
200          * and the L2 wakeup interrupts: keypad and UART2. Note that the
201          * drivers must still separately call omap_set_gpio_wakeup() to
202          * wake up to a GPIO interrupt.
203          */
204         if (cpu_is_omap730())
205                 level1_wake = OMAP_IRQ_BIT(INT_730_GPIO_BANK1) |
206                         OMAP_IRQ_BIT(INT_730_IH2_IRQ);
207         else if (cpu_is_omap15xx())
208                 level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
209                         OMAP_IRQ_BIT(INT_1510_IH2_IRQ);
210         else if (cpu_is_omap16xx())
211                 level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
212                         OMAP_IRQ_BIT(INT_1610_IH2_IRQ);
213
214         omap_writel(~level1_wake, OMAP_IH1_MIR);
215
216         if (cpu_is_omap730()) {
217                 omap_writel(~level2_wake, OMAP_IH2_0_MIR);
218                 omap_writel(~(OMAP_IRQ_BIT(INT_730_WAKE_UP_REQ) |
219                                 OMAP_IRQ_BIT(INT_730_MPUIO_KEYPAD)),
220                                 OMAP_IH2_1_MIR);
221         } else if (cpu_is_omap15xx()) {
222                 level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
223                 omap_writel(~level2_wake,  OMAP_IH2_MIR);
224         } else if (cpu_is_omap16xx()) {
225                 level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
226                 omap_writel(~level2_wake, OMAP_IH2_0_MIR);
227
228                 /* INT_1610_WAKE_UP_REQ is needed for GPIO wakeup... */
229                 omap_writel(~OMAP_IRQ_BIT(INT_1610_WAKE_UP_REQ),
230                             OMAP_IH2_1_MIR);
231                 omap_writel(~0x0, OMAP_IH2_2_MIR);
232                 omap_writel(~0x0, OMAP_IH2_3_MIR);
233         }
234
235         /*  New IRQ agreement, recalculate in cascade order */
236         omap_writel(1, OMAP_IH2_CONTROL);
237         omap_writel(1, OMAP_IH1_CONTROL);
238 }
239
240 #define EN_DSPCK        13      /* ARM_CKCTL */
241 #define EN_APICK        6       /* ARM_IDLECT2 */
242 #define DSP_EN          1       /* ARM_RSTCT1 */
243
244 void omap_pm_suspend(void)
245 {
246         unsigned long arg0 = 0, arg1 = 0;
247
248         printk("PM: OMAP%x is trying to enter deep sleep...\n", system_rev);
249
250         omap_serial_wake_trigger(1);
251
252         if (!cpu_is_omap15xx())
253                 omap_writew(0xffff, ULPD_SOFT_DISABLE_REQ_REG);
254
255         /*
256          * Step 1: turn off interrupts (FIXME: NOTE: already disabled)
257          */
258
259         local_irq_disable();
260         local_fiq_disable();
261
262         /*
263          * Step 2: save registers
264          *
265          * The omap is a strange/beautiful device. The caches, memory
266          * and register state are preserved across power saves.
267          * We have to save and restore very little register state to
268          * idle the omap.
269          *
270          * Save interrupt, MPUI, ARM and UPLD control registers.
271          */
272
273         if (cpu_is_omap730()) {
274                 MPUI730_SAVE(OMAP_IH1_MIR);
275                 MPUI730_SAVE(OMAP_IH2_0_MIR);
276                 MPUI730_SAVE(OMAP_IH2_1_MIR);
277                 MPUI730_SAVE(MPUI_CTRL);
278                 MPUI730_SAVE(MPUI_DSP_BOOT_CONFIG);
279                 MPUI730_SAVE(MPUI_DSP_API_CONFIG);
280                 MPUI730_SAVE(EMIFS_CONFIG);
281                 MPUI730_SAVE(EMIFF_SDRAM_CONFIG);
282
283         } else if (cpu_is_omap15xx()) {
284                 MPUI1510_SAVE(OMAP_IH1_MIR);
285                 MPUI1510_SAVE(OMAP_IH2_MIR);
286                 MPUI1510_SAVE(MPUI_CTRL);
287                 MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
288                 MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
289                 MPUI1510_SAVE(EMIFS_CONFIG);
290                 MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
291         } else if (cpu_is_omap16xx()) {
292                 MPUI1610_SAVE(OMAP_IH1_MIR);
293                 MPUI1610_SAVE(OMAP_IH2_0_MIR);
294                 MPUI1610_SAVE(OMAP_IH2_1_MIR);
295                 MPUI1610_SAVE(OMAP_IH2_2_MIR);
296                 MPUI1610_SAVE(OMAP_IH2_3_MIR);
297                 MPUI1610_SAVE(MPUI_CTRL);
298                 MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
299                 MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
300                 MPUI1610_SAVE(EMIFS_CONFIG);
301                 MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
302         }
303
304         ARM_SAVE(ARM_CKCTL);
305         ARM_SAVE(ARM_IDLECT1);
306         ARM_SAVE(ARM_IDLECT2);
307         if (!(cpu_is_omap15xx()))
308                 ARM_SAVE(ARM_IDLECT3);
309         ARM_SAVE(ARM_EWUPCT);
310         ARM_SAVE(ARM_RSTCT1);
311         ARM_SAVE(ARM_RSTCT2);
312         ARM_SAVE(ARM_SYSST);
313         ULPD_SAVE(ULPD_CLOCK_CTRL);
314         ULPD_SAVE(ULPD_STATUS_REQ);
315
316         /* (Step 3 removed - we now allow deep sleep by default) */
317
318         /*
319          * Step 4: OMAP DSP Shutdown
320          */
321
322         /* stop DSP */
323         omap_writew(omap_readw(ARM_RSTCT1) & ~(1 << DSP_EN), ARM_RSTCT1);
324
325                 /* shut down dsp_ck */
326         if (!cpu_is_omap730())
327                 omap_writew(omap_readw(ARM_CKCTL) & ~(1 << EN_DSPCK), ARM_CKCTL);
328
329         /* temporarily enabling api_ck to access DSP registers */
330         omap_writew(omap_readw(ARM_IDLECT2) | 1 << EN_APICK, ARM_IDLECT2);
331
332         /* save DSP registers */
333         DSP_SAVE(DSP_IDLECT2);
334
335         /* Stop all DSP domain clocks */
336         __raw_writew(0, DSP_IDLECT2);
337
338         /*
339          * Step 5: Wakeup Event Setup
340          */
341
342         omap_pm_wakeup_setup();
343
344         /*
345          * Step 6: ARM and Traffic controller shutdown
346          */
347
348         /* disable ARM watchdog */
349         omap_writel(0x00F5, OMAP_WDT_TIMER_MODE);
350         omap_writel(0x00A0, OMAP_WDT_TIMER_MODE);
351
352         /*
353          * Step 6b: ARM and Traffic controller shutdown
354          *
355          * Step 6 continues here. Prepare jump to power management
356          * assembly code in internal SRAM.
357          *
358          * Since the omap_cpu_suspend routine has been copied to
359          * SRAM, we'll do an indirect procedure call to it and pass the
360          * contents of arm_idlect1 and arm_idlect2 so it can restore
361          * them when it wakes up and it will return.
362          */
363
364         arg0 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT1];
365         arg1 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT2];
366
367         /*
368          * Step 6c: ARM and Traffic controller shutdown
369          *
370          * Jump to assembly code. The processor will stay there
371          * until wake up.
372          */
373         omap_sram_suspend(arg0, arg1);
374
375         /*
376          * If we are here, processor is woken up!
377          */
378
379         /*
380          * Restore DSP clocks
381          */
382
383         /* again temporarily enabling api_ck to access DSP registers */
384         omap_writew(omap_readw(ARM_IDLECT2) | 1 << EN_APICK, ARM_IDLECT2);
385
386         /* Restore DSP domain clocks */
387         DSP_RESTORE(DSP_IDLECT2);
388
389         /*
390          * Restore ARM state, except ARM_IDLECT1/2 which omap_cpu_suspend did
391          */
392
393         if (!(cpu_is_omap15xx()))
394                 ARM_RESTORE(ARM_IDLECT3);
395         ARM_RESTORE(ARM_CKCTL);
396         ARM_RESTORE(ARM_EWUPCT);
397         ARM_RESTORE(ARM_RSTCT1);
398         ARM_RESTORE(ARM_RSTCT2);
399         ARM_RESTORE(ARM_SYSST);
400         ULPD_RESTORE(ULPD_CLOCK_CTRL);
401         ULPD_RESTORE(ULPD_STATUS_REQ);
402
403         if (cpu_is_omap730()) {
404                 MPUI730_RESTORE(EMIFS_CONFIG);
405                 MPUI730_RESTORE(EMIFF_SDRAM_CONFIG);
406                 MPUI730_RESTORE(OMAP_IH1_MIR);
407                 MPUI730_RESTORE(OMAP_IH2_0_MIR);
408                 MPUI730_RESTORE(OMAP_IH2_1_MIR);
409         } else if (cpu_is_omap15xx()) {
410                 MPUI1510_RESTORE(MPUI_CTRL);
411                 MPUI1510_RESTORE(MPUI_DSP_BOOT_CONFIG);
412                 MPUI1510_RESTORE(MPUI_DSP_API_CONFIG);
413                 MPUI1510_RESTORE(EMIFS_CONFIG);
414                 MPUI1510_RESTORE(EMIFF_SDRAM_CONFIG);
415                 MPUI1510_RESTORE(OMAP_IH1_MIR);
416                 MPUI1510_RESTORE(OMAP_IH2_MIR);
417         } else if (cpu_is_omap16xx()) {
418                 MPUI1610_RESTORE(MPUI_CTRL);
419                 MPUI1610_RESTORE(MPUI_DSP_BOOT_CONFIG);
420                 MPUI1610_RESTORE(MPUI_DSP_API_CONFIG);
421                 MPUI1610_RESTORE(EMIFS_CONFIG);
422                 MPUI1610_RESTORE(EMIFF_SDRAM_CONFIG);
423
424                 MPUI1610_RESTORE(OMAP_IH1_MIR);
425                 MPUI1610_RESTORE(OMAP_IH2_0_MIR);
426                 MPUI1610_RESTORE(OMAP_IH2_1_MIR);
427                 MPUI1610_RESTORE(OMAP_IH2_2_MIR);
428                 MPUI1610_RESTORE(OMAP_IH2_3_MIR);
429         }
430
431         if (!cpu_is_omap15xx())
432                 omap_writew(0, ULPD_SOFT_DISABLE_REQ_REG);
433
434         /*
435          * Re-enable interrupts
436          */
437
438         local_irq_enable();
439         local_fiq_enable();
440
441         omap_serial_wake_trigger(0);
442
443         printk("PM: OMAP%x is re-starting from deep sleep...\n", system_rev);
444 }
445
446 #if defined(DEBUG) && defined(CONFIG_PROC_FS)
447 static int g_read_completed;
448
449 /*
450  * Read system PM registers for debugging
451  */
452 static int omap_pm_read_proc(
453         char *page_buffer,
454         char **my_first_byte,
455         off_t virtual_start,
456         int length,
457         int *eof,
458         void *data)
459 {
460         int my_buffer_offset = 0;
461         char * const my_base = page_buffer;
462
463         ARM_SAVE(ARM_CKCTL);
464         ARM_SAVE(ARM_IDLECT1);
465         ARM_SAVE(ARM_IDLECT2);
466         if (!(cpu_is_omap15xx()))
467                 ARM_SAVE(ARM_IDLECT3);
468         ARM_SAVE(ARM_EWUPCT);
469         ARM_SAVE(ARM_RSTCT1);
470         ARM_SAVE(ARM_RSTCT2);
471         ARM_SAVE(ARM_SYSST);
472
473         ULPD_SAVE(ULPD_IT_STATUS);
474         ULPD_SAVE(ULPD_CLOCK_CTRL);
475         ULPD_SAVE(ULPD_SOFT_REQ);
476         ULPD_SAVE(ULPD_STATUS_REQ);
477         ULPD_SAVE(ULPD_DPLL_CTRL);
478         ULPD_SAVE(ULPD_POWER_CTRL);
479
480         if (cpu_is_omap730()) {
481                 MPUI730_SAVE(MPUI_CTRL);
482                 MPUI730_SAVE(MPUI_DSP_STATUS);
483                 MPUI730_SAVE(MPUI_DSP_BOOT_CONFIG);
484                 MPUI730_SAVE(MPUI_DSP_API_CONFIG);
485                 MPUI730_SAVE(EMIFF_SDRAM_CONFIG);
486                 MPUI730_SAVE(EMIFS_CONFIG);
487         } else if (cpu_is_omap15xx()) {
488                 MPUI1510_SAVE(MPUI_CTRL);
489                 MPUI1510_SAVE(MPUI_DSP_STATUS);
490                 MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
491                 MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
492                 MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
493                 MPUI1510_SAVE(EMIFS_CONFIG);
494         } else if (cpu_is_omap16xx()) {
495                 MPUI1610_SAVE(MPUI_CTRL);
496                 MPUI1610_SAVE(MPUI_DSP_STATUS);
497                 MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
498                 MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
499                 MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
500                 MPUI1610_SAVE(EMIFS_CONFIG);
501         }
502
503         if (virtual_start == 0) {
504                 g_read_completed = 0;
505
506                 my_buffer_offset += sprintf(my_base + my_buffer_offset,
507                    "ARM_CKCTL_REG:            0x%-8x     \n"
508                    "ARM_IDLECT1_REG:          0x%-8x     \n"
509                    "ARM_IDLECT2_REG:          0x%-8x     \n"
510                    "ARM_IDLECT3_REG:          0x%-8x     \n"
511                    "ARM_EWUPCT_REG:           0x%-8x     \n"
512                    "ARM_RSTCT1_REG:           0x%-8x     \n"
513                    "ARM_RSTCT2_REG:           0x%-8x     \n"
514                    "ARM_SYSST_REG:            0x%-8x     \n"
515                    "ULPD_IT_STATUS_REG:       0x%-4x     \n"
516                    "ULPD_CLOCK_CTRL_REG:      0x%-4x     \n"
517                    "ULPD_SOFT_REQ_REG:        0x%-4x     \n"
518                    "ULPD_DPLL_CTRL_REG:       0x%-4x     \n"
519                    "ULPD_STATUS_REQ_REG:      0x%-4x     \n"
520                    "ULPD_POWER_CTRL_REG:      0x%-4x     \n",
521                    ARM_SHOW(ARM_CKCTL),
522                    ARM_SHOW(ARM_IDLECT1),
523                    ARM_SHOW(ARM_IDLECT2),
524                    ARM_SHOW(ARM_IDLECT3),
525                    ARM_SHOW(ARM_EWUPCT),
526                    ARM_SHOW(ARM_RSTCT1),
527                    ARM_SHOW(ARM_RSTCT2),
528                    ARM_SHOW(ARM_SYSST),
529                    ULPD_SHOW(ULPD_IT_STATUS),
530                    ULPD_SHOW(ULPD_CLOCK_CTRL),
531                    ULPD_SHOW(ULPD_SOFT_REQ),
532                    ULPD_SHOW(ULPD_DPLL_CTRL),
533                    ULPD_SHOW(ULPD_STATUS_REQ),
534                    ULPD_SHOW(ULPD_POWER_CTRL));
535
536                 if (cpu_is_omap730()) {
537                         my_buffer_offset += sprintf(my_base + my_buffer_offset,
538                            "MPUI730_CTRL_REG         0x%-8x \n"
539                            "MPUI730_DSP_STATUS_REG:      0x%-8x \n"
540                            "MPUI730_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
541                            "MPUI730_DSP_API_CONFIG_REG:  0x%-8x \n"
542                            "MPUI730_SDRAM_CONFIG_REG:    0x%-8x \n"
543                            "MPUI730_EMIFS_CONFIG_REG:    0x%-8x \n",
544                            MPUI730_SHOW(MPUI_CTRL),
545                            MPUI730_SHOW(MPUI_DSP_STATUS),
546                            MPUI730_SHOW(MPUI_DSP_BOOT_CONFIG),
547                            MPUI730_SHOW(MPUI_DSP_API_CONFIG),
548                            MPUI730_SHOW(EMIFF_SDRAM_CONFIG),
549                            MPUI730_SHOW(EMIFS_CONFIG));
550                 } else if (cpu_is_omap15xx()) {
551                         my_buffer_offset += sprintf(my_base + my_buffer_offset,
552                            "MPUI1510_CTRL_REG             0x%-8x \n"
553                            "MPUI1510_DSP_STATUS_REG:      0x%-8x \n"
554                            "MPUI1510_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
555                            "MPUI1510_DSP_API_CONFIG_REG:  0x%-8x \n"
556                            "MPUI1510_SDRAM_CONFIG_REG:    0x%-8x \n"
557                            "MPUI1510_EMIFS_CONFIG_REG:    0x%-8x \n",
558                            MPUI1510_SHOW(MPUI_CTRL),
559                            MPUI1510_SHOW(MPUI_DSP_STATUS),
560                            MPUI1510_SHOW(MPUI_DSP_BOOT_CONFIG),
561                            MPUI1510_SHOW(MPUI_DSP_API_CONFIG),
562                            MPUI1510_SHOW(EMIFF_SDRAM_CONFIG),
563                            MPUI1510_SHOW(EMIFS_CONFIG));
564                 } else if (cpu_is_omap16xx()) {
565                         my_buffer_offset += sprintf(my_base + my_buffer_offset,
566                            "MPUI1610_CTRL_REG             0x%-8x \n"
567                            "MPUI1610_DSP_STATUS_REG:      0x%-8x \n"
568                            "MPUI1610_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
569                            "MPUI1610_DSP_API_CONFIG_REG:  0x%-8x \n"
570                            "MPUI1610_SDRAM_CONFIG_REG:    0x%-8x \n"
571                            "MPUI1610_EMIFS_CONFIG_REG:    0x%-8x \n",
572                            MPUI1610_SHOW(MPUI_CTRL),
573                            MPUI1610_SHOW(MPUI_DSP_STATUS),
574                            MPUI1610_SHOW(MPUI_DSP_BOOT_CONFIG),
575                            MPUI1610_SHOW(MPUI_DSP_API_CONFIG),
576                            MPUI1610_SHOW(EMIFF_SDRAM_CONFIG),
577                            MPUI1610_SHOW(EMIFS_CONFIG));
578                 }
579
580                 g_read_completed++;
581         } else if (g_read_completed >= 1) {
582                  *eof = 1;
583                  return 0;
584         }
585         g_read_completed++;
586
587         *my_first_byte = page_buffer;
588         return  my_buffer_offset;
589 }
590
591 static void omap_pm_init_proc(void)
592 {
593         struct proc_dir_entry *entry;
594
595         entry = create_proc_read_entry("driver/omap_pm",
596                                        S_IWUSR | S_IRUGO, NULL,
597                                        omap_pm_read_proc, NULL);
598 }
599
600 #endif /* DEBUG && CONFIG_PROC_FS */
601
602 static void (*saved_idle)(void) = NULL;
603
604 /*
605  *      omap_pm_prepare - Do preliminary suspend work.
606  *      @state:         suspend state we're entering.
607  *
608  */
609 static int omap_pm_prepare(suspend_state_t state)
610 {
611         int error = 0;
612
613         /* We cannot sleep in idle until we have resumed */
614         saved_idle = pm_idle;
615         pm_idle = NULL;
616
617         switch (state)
618         {
619         case PM_SUSPEND_STANDBY:
620         case PM_SUSPEND_MEM:
621                 break;
622         default:
623                 return -EINVAL;
624         }
625
626         return error;
627 }
628
629
630 /*
631  *      omap_pm_enter - Actually enter a sleep state.
632  *      @state:         State we're entering.
633  *
634  */
635
636 static int omap_pm_enter(suspend_state_t state)
637 {
638         switch (state)
639         {
640         case PM_SUSPEND_STANDBY:
641         case PM_SUSPEND_MEM:
642                 omap_pm_suspend();
643                 break;
644         default:
645                 return -EINVAL;
646         }
647
648         return 0;
649 }
650
651
652 /**
653  *      omap_pm_finish - Finish up suspend sequence.
654  *      @state:         State we're coming out of.
655  *
656  *      This is called after we wake back up (or if entering the sleep state
657  *      failed).
658  */
659
660 static int omap_pm_finish(suspend_state_t state)
661 {
662         pm_idle = saved_idle;
663         return 0;
664 }
665
666
667 static irqreturn_t  omap_wakeup_interrupt(int irq, void *dev)
668 {
669         return IRQ_HANDLED;
670 }
671
672 static struct irqaction omap_wakeup_irq = {
673         .name           = "peripheral wakeup",
674         .flags          = IRQF_DISABLED,
675         .handler        = omap_wakeup_interrupt
676 };
677
678
679
680 static struct pm_ops omap_pm_ops ={
681         .prepare        = omap_pm_prepare,
682         .enter          = omap_pm_enter,
683         .finish         = omap_pm_finish,
684         .valid          = pm_valid_only_mem,
685 };
686
687 static int __init omap_pm_init(void)
688 {
689         int error;
690
691         printk("Power Management for TI OMAP.\n");
692
693         /*
694          * We copy the assembler sleep/wakeup routines to SRAM.
695          * These routines need to be in SRAM as that's the only
696          * memory the MPU can see when it wakes up.
697          */
698         if (cpu_is_omap730()) {
699                 omap_sram_idle = omap_sram_push(omap730_idle_loop_suspend,
700                                                 omap730_idle_loop_suspend_sz);
701                 omap_sram_suspend = omap_sram_push(omap730_cpu_suspend,
702                                                    omap730_cpu_suspend_sz);
703         } else if (cpu_is_omap15xx()) {
704                 omap_sram_idle = omap_sram_push(omap1510_idle_loop_suspend,
705                                                 omap1510_idle_loop_suspend_sz);
706                 omap_sram_suspend = omap_sram_push(omap1510_cpu_suspend,
707                                                    omap1510_cpu_suspend_sz);
708         } else if (cpu_is_omap16xx()) {
709                 omap_sram_idle = omap_sram_push(omap1610_idle_loop_suspend,
710                                                 omap1610_idle_loop_suspend_sz);
711                 omap_sram_suspend = omap_sram_push(omap1610_cpu_suspend,
712                                                    omap1610_cpu_suspend_sz);
713         }
714
715         if (omap_sram_idle == NULL || omap_sram_suspend == NULL) {
716                 printk(KERN_ERR "PM not initialized: Missing SRAM support\n");
717                 return -ENODEV;
718         }
719
720         pm_idle = omap_pm_idle;
721
722         if (cpu_is_omap730())
723                 setup_irq(INT_730_WAKE_UP_REQ, &omap_wakeup_irq);
724         else if (cpu_is_omap16xx())
725                 setup_irq(INT_1610_WAKE_UP_REQ, &omap_wakeup_irq);
726
727         /* Program new power ramp-up time
728          * (0 for most boards since we don't lower voltage when in deep sleep)
729          */
730         omap_writew(ULPD_SETUP_ANALOG_CELL_3_VAL, ULPD_SETUP_ANALOG_CELL_3);
731
732         /* Setup ULPD POWER_CTRL_REG - enter deep sleep whenever possible */
733         omap_writew(ULPD_POWER_CTRL_REG_VAL, ULPD_POWER_CTRL);
734
735         /* Configure IDLECT3 */
736         if (cpu_is_omap730())
737                 omap_writel(OMAP730_IDLECT3_VAL, OMAP730_IDLECT3);
738         else if (cpu_is_omap16xx())
739                 omap_writel(OMAP1610_IDLECT3_VAL, OMAP1610_IDLECT3);
740
741         pm_set_ops(&omap_pm_ops);
742
743 #if defined(DEBUG) && defined(CONFIG_PROC_FS)
744         omap_pm_init_proc();
745 #endif
746
747         error = subsys_create_file(&power_subsys, &sleep_while_idle_attr);
748         if (error)
749                 printk(KERN_ERR "subsys_create_file failed: %d\n", error);
750
751         if (cpu_is_omap16xx()) {
752                 /* configure LOW_PWR pin */
753                 omap_cfg_reg(T20_1610_LOW_PWR);
754         }
755
756         return 0;
757 }
758 __initcall(omap_pm_init);