memory: tegra: wait correct DLL state for dll update

At the end of the DLL disable/enable sequence, it needs to wait on
update of bit CFG_DLL_EN of the EMC_CFG_DIG_DLL shadowed register.
Currently the enable seqneuce also waits on DISABLED state, this is
causing long time elapsed in wait_for_update() and eventually bails
out due to timeout.
This patch fix the above issue.

Bug 2378628
Bug 2403305

Change-Id: Ied2e8be1babd62f703495682b0d17b422ab17cb6
Signed-off-by: Ken Chang <kenc@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1917223
(cherry picked from commit dd1c10f635df58419edf5183c512cfc5d7714605)
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1928629
GVS: Gerrit_Virtual_Submit
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

diff --git a/drivers/memory/tegra/tegra210-emc.c b/drivers/memory/tegra/tegra210-emc.c
index 9995d74d548a269ec5bcc2124241ef4e281cd8f1..b59ab92632ce37b447d506debb38a0f036b40945 100644 (file)
--- a/drivers/memory/tegra/tegra210-emc.c
+++ b/drivers/memory/tegra/tegra210-emc.c
@@ -1241,16 +1241,18 @@ void tegra210_reset_dram_clktree_values(struct emc_table *table)
        __RESET_CLKTREE(table, 1, 1, 1);
 }
 
-static void update_dll_control(u32 emc_cfg_dig_dll, int channel_mode)
+static void update_dll_control(u32 emc_cfg_dig_dll,
+               int channel_mode, bool updated_state)
 {
        emc_writel(emc_cfg_dig_dll, EMC_CFG_DIG_DLL);
        emc_timing_update(channel_mode);
 
        wait_for_update(EMC_CFG_DIG_DLL, EMC_CFG_DIG_DLL_CFG_DLL_EN,
-                       0, REG_EMC);
+                       updated_state, REG_EMC);
        if (channel_mode == DUAL_CHANNEL)
                wait_for_update(EMC_CFG_DIG_DLL,
-                               EMC_CFG_DIG_DLL_CFG_DLL_EN, 0, REG_EMC1);
+                               EMC_CFG_DIG_DLL_CFG_DLL_EN,
+                               updated_state, REG_EMC1);
 }
 
 void tegra210_dll_disable(int channel_mode)
@@ -1260,7 +1262,7 @@ void tegra210_dll_disable(int channel_mode)
        emc_cfg_dig_dll = emc_readl(EMC_CFG_DIG_DLL);
        emc_cfg_dig_dll &= ~EMC_CFG_DIG_DLL_CFG_DLL_EN;
 
-       update_dll_control(emc_cfg_dig_dll, channel_mode);
+       update_dll_control(emc_cfg_dig_dll, channel_mode, false);
 }
 
 void tegra210_dll_enable(int channel_mode)
@@ -1270,7 +1272,7 @@ void tegra210_dll_enable(int channel_mode)
        emc_cfg_dig_dll = emc_readl(EMC_CFG_DIG_DLL);
        emc_cfg_dig_dll |= EMC_CFG_DIG_DLL_CFG_DLL_EN;
 
-       update_dll_control(emc_cfg_dig_dll, channel_mode);
+       update_dll_control(emc_cfg_dig_dll, channel_mode, true);
 }
 
 void tegra210_emc_timing_invalidate(void)