3 years ago[FOSS_TLK] Modify makefile to point to proper path master
Sharif Inamdar [Thu, 11 Jun 2015 12:39:07 +0000]
[FOSS_TLK] Modify makefile to point to proper path

Since secure_monitor is a separate repo, so modifying
the path to point to proper location of tools and build
directory.

Signed-off-by: Sharif Inamdar <isharif@nvidia.com>

3 years ago[FOSS_TLK][platform][tegra] update t210 cntfrq to 19.2Mhz
Bo Yan [Sun, 24 Aug 2014 01:50:23 +0000]
[FOSS_TLK][platform][tegra] update t210 cntfrq to 19.2Mhz

19.2Mhz is the clk-m frequency for t210 platforms, so update it

Change-Id: Ifad7d6f591cd8cedcbbc72db52aec9c48898bbf2

3 years ago[FOSS_TLK]lib: monitor: arm64: support for ARM Trusted Firmware's bootargs
Varun Wadekar [Wed, 27 May 2015 10:13:29 +0000]
[FOSS_TLK]lib: monitor: arm64: support for ARM Trusted Firmware's bootargs

This patch adds support for the ARM Trusted Firmware's BL2 boot parameters.
Here, BL2 is the bootloader running in the system whic loads the EL3/EL2
binaries. The bootloader passes two pointers to structs describing -

* the secure/non-secure world binaries (image size, entrypoints, etc)
* platform values (tzdram size, TLK boot args)

Register x3 contains a magic value used to identify the newer policy.

Change-Id: Ia68fda5e2f34252a9963f97b1da8984fd765cb54
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

3 years ago[FOSS_TLK]platform: tegra: set priority value for SPIs (before marking as NS)
Seth Eatinger [Wed, 20 May 2015 19:57:06 +0000]
[FOSS_TLK]platform: tegra: set priority value for SPIs (before marking as NS)

According to the GIC spec, “ARM recommends that, for a Group 1 interrupt,
bit[7] is set to 1“.  Essentially if a non-secure interrupt has priority <128,
you risk denial of service security attacks.

But the secure monitor starts by setting all interrupts as NS. The problem is
that the reset value for all IRQ priorities is zero.  The secure monitor does
not ever set the IRQ priorities for the NS interrupts, only the secure
interrupts.  We are relying on the untrusted software to set the IRQ
priorities for non-secure interrupts to something >= 128.

The proposed fix is to set the priority value for all interrupts to 128 (0x80)
before making all the IRQs non-secure.  Then, same as before, the secure
monitor will individually set some of the IRQs to secure and set their
priorities.

Change-Id: Icf0d287641298f3b13b3961cc77f0ec097cabd7e
Signed-off-by: Seth Eatinger <seatinger@nvidia.com>

3 years ago[FOSS_TLK]platform: tegra: Enable WRAP to INCR burst type conversion in MSELECT
Prashant Gaikwad [Tue, 12 May 2015 06:18:26 +0000]
[FOSS_TLK]platform: tegra: Enable WRAP to INCR burst type conversion in MSELECT

Problem Statement

APC, ACB and AFI do not support WRAP burst type and can cause system hangs if they are encountered in these layers.

WAR Statement

Enable WRAP to INCR burst type conversion in MSELECT
Turn bits 24:25 in MSELECT_CONFIG register off to disable error mechanism
Turn bits 29:27 in MSELECT_CONFIG register on to enable WRAP type conversion

Change-Id: I25f5ef42b7b4faf76bf4d7963dded42b9497b27b
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>

3 years ago[FOSS_TLK]tegra: monitor: add soc-specific sip callback
Peng Du [Wed, 8 Apr 2015 00:09:41 +0000]
[FOSS_TLK]tegra: monitor: add soc-specific sip callback

Change-Id: Ief088782823b57ded3d99b5c09408395c60b449b

3 years ago[FOSS_TLK]arm64: start: new policy to get boot params from BL
Varun Wadekar [Tue, 28 Apr 2015 10:20:08 +0000]
[FOSS_TLK]arm64: start: new policy to get boot params from BL

The bootloader now uses a new policy to pass input parameters for the
monitor and Trusted OS. According to this policy, we use the following
CPU registers:

x0 = TZ-DRAM aperture size
x1 = NS entry point
x2 = boot args
x3 = magic value to indicate new policy

Change-Id: I806a68602478515ff9b01baab5a4dcf09d470385
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

3 years ago[FOSS_TLK]secure_monitor: Enable building securemon for foundation
Vishal Annapurve [Wed, 22 Apr 2015 05:57:30 +0000]
[FOSS_TLK]secure_monitor: Enable building securemon for foundation

This change adds support for enabling build of secure monitor
under embedded-foundation umbrella

Change-Id: I969d33cac4e0dcca05c4651fa8f035242eab6c60

3 years ago[FOSS_TLK]platform: tegra: mc initialize function.
Harvey Hsieh [Thu, 23 Apr 2015 12:27:00 +0000]
[FOSS_TLK]platform: tegra: mc initialize function.

Change-Id: I131f8478181823ad16ca87f92da7829b30662523

3 years ago[FOSS_TLK]monitor: build: Add embedded-qnx build support
Poojan Shah [Thu, 23 Apr 2015 18:28:51 +0000]
[FOSS_TLK]monitor: build: Add embedded-qnx build support

Change-Id: Ia0b19d538dc2e6b35dc4d7ebc41037e8c561327c

3 years ago[FOSS_TLK]arm64: cache_helpers: force csw for cisw operations
Varun Wadekar [Mon, 6 Apr 2015 11:31:23 +0000]
[FOSS_TLK]arm64: cache_helpers: force csw for cisw operations

As per ARM, it turns out that for A15/A57, DC CSW targeting L2 will only
push dirty data from L2. L1 remains untouched, so if it has dirty data in
L1, wont be pushed to L2.

The work-around is to issue DC CISW for DC CSW operations.

Change-Id: Ia2653bdaf6c36ccc2a8927ba41a379f1736fc3ea
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

3 years ago[FOSS_TLK]platform: tegra124: create a "true" monitor for ARMv7
Varun Wadekar [Wed, 18 Mar 2015 08:30:33 +0000]
[FOSS_TLK]platform: tegra124: create a "true" monitor for ARMv7

In the past, TLK has been holding the monitor code for ARMv7 CPUs. With
this patch, we move all the files from TLK to create a standalone monitor
library. TLK will still link to this library to generate the final image.

The following features have been implemented:

* Separate monitor code for ARM CPUs; resides under lib/monitor/arm
* PSCI - CPU on, off, suspend, LP2, cluster switch
* Separate monitor per-CPU stack
* fastcall_frame is not required, as we use the per-CPU monitor stack
  instead
* Fastcalls are handled by the monitor now
* CPU boot, suspend, resume code moved to the monitor
* Monitor vectors reside in the monitor now and route the standard
  calls to TLK
* The monitor expects the linux driver to register the IRAM vector
  address for LP0 entry

Change-Id: I1295dd6aa3bc0f1ddf41f414372cb31e33cdf4a0
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

3 years ago[FOSS_TLK]lib: monitor: arm64: pass SMC args/results using CPU regs (x0-x7)
Varun Wadekar [Wed, 1 Apr 2015 12:40:48 +0000]
[FOSS_TLK]lib: monitor: arm64: pass SMC args/results using CPU regs (x0-x7)

This patch removes the need for a shared buffer between the EL3 and S-EL1
for passing SMC args/results. Since the S-EL1 binary is a 32-bit one, we
use the CPU registers (x0-x7) instead. This translates to r0-r7 for the 32
bit Trusted OS.

Change-Id: Ic52f7f198ecf0d6ff329c4a3d192d3a47680d8ae
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

3 years ago[FOSS_TLK]lib: monitor: arm64: Don't restore debug registers on boot
Mustafa Yigit Bilgen [Wed, 18 Mar 2015 01:26:07 +0000]
[FOSS_TLK]lib: monitor: arm64: Don't restore debug registers on boot

On boot, the call to mon_cpu_dbg_restore does not follow a mon_cpu_dbg_save,
which results in zeros to be written to various debug and config registers.

This patch sets a flag in memory on mon_cpu_dbg_save, and only restores the
context if the flag is set. Therefore, all such registers will retain their
reset values.

Change-Id: I62260d01f476c91041df16aa8713d8a77f876913

3 years ago[FOSS_TLK]secure_monitor: header file for libvrr to compile.
Marvin Zhang [Fri, 20 Mar 2015 01:11:18 +0000]
[FOSS_TLK]secure_monitor: header file for libvrr to compile.

Make sure the monitor does not include standard headers/libs
which would've caught usage of stdarg.h (not knowing where
it was coming from).

Rework headers, so libraries don't need to include #defines
to have the compile complete successfully.

Change-Id: Iab56932287f63341d08899f1931091b8630c4211

3 years ago[FOSS_TLK]secure_monitor: link to libvrr if exists
Mitch Luban [Fri, 13 Mar 2015 00:48:54 +0000]
[FOSS_TLK]secure_monitor: link to libvrr if exists

Change-Id: Ib4dad0d718531e9ab7ff1707a9f5dacb05bab12e

3 years ago[FOSS_TLK]fastcall: add weak platform_vrr_fastcall.
Chris Johnson [Thu, 19 Feb 2015 03:10:48 +0000]
[FOSS_TLK]fastcall: add weak platform_vrr_fastcall.

This a weak implementation of the VRR monitor fastcall.
Add secure VRR support.

Change-Id: I51921215787fa5c9f332ecab531271d5eb26261d
Signed-off-by: Marvin Zhang <mzhang@nvidia.com>

3 years ago[FOSS_TLK]secure_monitor: fix errors in platform_psci_cpu_on
Seth Eatinger [Thu, 19 Mar 2015 15:35:26 +0000]
[FOSS_TLK]secure_monitor: fix errors in platform_psci_cpu_on

Change PMC_PWRGATE_STATUS offset to 0x38 (not 0x2c)
Reading PMC_PWRGATE_STATUS is 1 when ungated (not 0)
Fix 2 instances of PWRGATE_STATUS query [amended]

Change-Id: Iaa88ab16be689cf4ae86f954fdb9f255dcf0b5b9

3 years ago[FOSS_TLK]platform: tegra: SoC-specific "reset vectors programming"
Varun Wadekar [Mon, 16 Feb 2015 05:22:05 +0000]
[FOSS_TLK]platform: tegra: SoC-specific "reset vectors programming"

This patch adds support to program the reset vectors per-chip, rather
than lumping everything together and then separating it with per-SoC
macros. This makes sense, since the registers for storing reset vectors
keep changing for newer chips.

Change-Id: I2daf73b096b5f043e1ca5a8c74c5fbd1c000e032
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

3 years ago[FOSS_TLK]arm: include: add psci header to common location
Varun Wadekar [Mon, 16 Feb 2015 05:19:45 +0000]
[FOSS_TLK]arm: include: add psci header to common location

PSCI header defines the interface for ARM/ARM64 and so should
reside in the top-level ARM directory for both the archs to use.

Change-Id: I32822e28c7a47fbb4a45ab206b932b3777593bd4
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

3 years ago[FOSS_TLK]platform: tegra: psci: Fix target_cpu check
Aaron Gamble [Fri, 6 Mar 2015 23:10:34 +0000]
[FOSS_TLK]platform: tegra: psci: Fix target_cpu check

Coverity id : 29599

Change-Id: I79df95e9744a7c21153b3e1b9f2a5ecc102475ff

3 years ago[FOSS_TLK]secure_monitor: remove incorrect T132 register access
Matt Craighead [Thu, 5 Mar 2015 20:23:20 +0000]
[FOSS_TLK]secure_monitor: remove incorrect T132 register access

The LEGACYFIQ bit in this flow controller register only exists
in T210.  It does not exist in earlier chips.

Change-Id: If89bc719de016cba1ca588248b86e3614f207b80
Signed-off-by: Matt Craighead <mcraighead@nvidia.com>

3 years ago[FOSS_TLK]monitor: arm64: enable hvc instruction
Peter Newman [Wed, 25 Feb 2015 18:53:20 +0000]
[FOSS_TLK]monitor: arm64: enable hvc instruction

Set SCR_EL3.HCE when returning to non-secure state to enable the HVC
instruction.

Change-Id: I4f877de1e4084218f2bf0a8908b227a2c25b6651

3 years ago[FOSS_TLK]platform: tegra: map WDT_CPU to CPU 0-3
Allen Yu [Tue, 10 Mar 2015 02:14:48 +0000]
[FOSS_TLK]platform: tegra: map WDT_CPU to CPU 0-3

Map WDT_CPU to CPU 0-3 so that the FIQ can be presented to all
online cores since WDT_CPU is configured to be level-sensitive.
This helps us get debug information on all online cores in t124
platforms when lockup detected.

Change-Id: Ib0171f19f873e8b8ca55f0804f9707be208e89fb
Signed-off-by: Allen Yu <alleny@nvidia.com>

3 years ago[FOSS_TLK]monitor: disable dual-issue for cortex-a53
Bo Yan [Fri, 7 Nov 2014 21:59:16 +0000]
[FOSS_TLK]monitor: disable dual-issue for cortex-a53

The t210 slow cluster has 4 Cortex-A53 which suffer from ARM HW bug
Erratum #835769. Disabling dual issue will prevent failure from
happening, but it has performance impact.

Since this is fixed in HW in A02, check REVIDR_EL1 register, apply
the WAR only if A53 rev id is not 0xFC, which is the rev ID of A02.

Change-Id: I1b6ce06094faf326915000684f64291d11a641fd
Signed-off-by: Bo Yan <byan@nvidia.com>

3 years ago[FOSS_TLK]secure_monitor: fix flow controller register access
Matt Craighead [Thu, 5 Mar 2015 20:02:23 +0000]
[FOSS_TLK]secure_monitor: fix flow controller register access

This code was erroneously using a 64-bit load/store to access a
32-bit MMIO register in the flow controller.  Use a 32-bit (w)
register instead of a 64-bit (x) register.

Change-Id: I64feaad5defce1903d332d699cea8b98c449ff9c
Signed-off-by: Matt Craighead <mcraighead@nvidia.com>

3 years ago[FOSS_TLK]platform: tegra: make FIQ debugger cross calls
Chris Johnson [Sat, 24 Jan 2015 00:14:19 +0000]
[FOSS_TLK]platform: tegra: make FIQ debugger cross calls

Change-Id: I60610184d92017f394575a55fb812ff736bda13a
Signed-off-by: Allen Yu <alleny@nvidia.com>

3 years ago[FOSS_TLK]platform: tegra: psci: sanity check CPU # during CPU_ON
Varun Wadekar [Mon, 2 Mar 2015 11:55:18 +0000]
[FOSS_TLK]platform: tegra: psci: sanity check CPU # during CPU_ON

In order to avoid arbitrary memory accesses, always sanity check the
CPU # before using it to store the CPU boot address.

Change-Id: I8abcd7fd5ac44dd367815ee39e3de04ce9e0e1a8
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

3 years ago[FOSS_TLK]lib: monitor: arm64: clean-invalidate d$ from FIQ handler
Varun Wadekar [Thu, 11 Dec 2014 05:34:46 +0000]
[FOSS_TLK]lib: monitor: arm64: clean-invalidate d$ from FIQ handler

We want the d$ to be flushed out to the DRAM before the FIQ debugger
reboots the system. This will allow us to get the correct previous
state of the system after reboot.

Change-Id: I18eef502f050e1ed35825e931ef50fdf6ce9065f
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

3 years ago[FOSS_TLK]lib: monitor: arm64: enable nLEGACYFIQ PPI for the FIQ debugger
Varun Wadekar [Tue, 9 Dec 2014 11:14:11 +0000]
[FOSS_TLK]lib: monitor: arm64: enable nLEGACYFIQ PPI for the FIQ debugger

Enable nLEGACYFIQ as the interrupt to trigger the FIQ debugger. We
program the watchdog timer to assert WDT_FIQ on its 2nd expiry,
which acts as the trigger for the FIQ debugger dump. Remove the
previous GIC settings where we used the 1st expiry as the trigger
instead.

Change-Id: If3c1f5fd036355bc085a208125a5f8fc500cb3b4
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

3 years ago[FOSS_TLK]monitor: arm64: generate function symbols
Bo Yan [Wed, 18 Feb 2015 18:52:52 +0000]
[FOSS_TLK]monitor: arm64: generate function symbols

Compiler treats functions in assembly as elf symbols of type
STT_NOTYPE. This confuses tools for stack analysis.

Force functions to be treated as STT_FUNC in elf and give them
proper size in symbol table.

Change-Id: I79f16308c36856f430e7de73b25cb46ebec33c28
Signed-off-by: Bo Yan <byan@nvidia.com>

3 years ago[FOSS_TLK]secure_monitor: remove unpredictable arm insn
Seth Eatinger [Tue, 3 Feb 2015 17:11:35 +0000]
[FOSS_TLK]secure_monitor: remove unpredictable arm insn

Remove unpredicable arm instruction usage
DDI0487A_b_armv8_arm.pdf, page 507

Change-Id: I24c1154472f510193ec72f6adb9f787d9e4a33e2
Signed-off-by: Seth Eatinger <seatinger@nvidia.com>

3 years ago[FOSS_TLK]platform: tegra: memory: don't write T210 register on T132
Matt Craighead [Wed, 14 Jan 2015 19:17:32 +0000]
[FOSS_TLK]platform: tegra: memory: don't write T210 register on T132

Change-Id: I38c6ac91a294aac4d90f556f5bacb03074108ef4
Signed-off-by: Matt Craighead <mcraighead@nvidia.com>

3 years ago[FOSS_TLK]secure_callbacks: merge preempted_by_irq/fs SMCs
Varun Wadekar [Mon, 5 Jan 2015 07:51:55 +0000]
[FOSS_TLK]secure_callbacks: merge preempted_by_irq/fs SMCs

Instead of having two function ids for the "preempted" scenario,
use a common SMC_TOS_PREEMPTED id. The error code passed by the
secure world will be used by the NS driver to differentiate
between scenarios.

Change-Id: I81e8693c48b6c4d5ff6fcfa6dcb2c1bcf98b747f
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

3 years ago[FOSS_TLK]secure_monitor: enable warnings as errors
Matt Craighead [Wed, 7 Jan 2015 00:27:23 +0000]
[FOSS_TLK]secure_monitor: enable warnings as errors

Change-Id: I6116bf9552e91848f78b6e689e046077734499db
Signed-off-by: Matt Craighead <mcraighead@nvidia.com>

3 years ago[FOSS_TLK]lib: monitor: arm64: enable retention support
Bo Yan [Tue, 16 Dec 2014 18:53:34 +0000]
[FOSS_TLK]lib: monitor: arm64: enable retention support

Enable processor retention by programming CPUECTLR_EL1 and
L2ECTLR_EL1 registers when CPU powers up.

This is currently done for Cortex-A53/A57 only. Denver has
its own way to enter retention.

Change-Id: Iaca15a337b05b205468df66ac242d44c9fda05a9
Signed-off-by: Bo Yan <byan@nvidia.com>

3 years agosecure_monitor: upgrade to gcc 4.9
Matt Craighead [Mon, 5 Jan 2015 21:53:32 +0000]
secure_monitor: upgrade to gcc 4.9

Change-Id: I3a1ae3ee92c2ed51d3ea96fb381fdc46c74aa5c0
Signed-off-by: Matt Craighead <mcraighead@nvidia.com>

3 years ago[FOSS_TLK]tegra: monitor: add mmio/reset plat specific fn's
Adeel Raza [Sat, 6 Dec 2014 00:17:52 +0000]
[FOSS_TLK]tegra: monitor: add mmio/reset plat specific fn's

Add the following platform specific functions:
  - platform_map_mmio()
  - platform_psci_init_reset_vector()

Change-Id: I46c1b607e97ba97d163db927618004cee00ae198

3 years ago[FOSS_TLK]platform: tegra: monitor: enable PSCI support for T132
Varun Wadekar [Wed, 19 Nov 2014 10:01:59 +0000]
[FOSS_TLK]platform: tegra: monitor: enable PSCI support for T132

Support to respect PSCI ON/OFF/SUSPEND calls. Right now, we only
support LP0 for SUSPEND. T132 expects suport for C6/C7 for CPU OFF.
In order to boot CPU1 on LP0 exit, we have to power it in the CPU
ON PSCI handler.

We have to move the code to stop MTS background work to the monitor
code so that it is one of the last thing the CPU does before calling
"wfi".

Make the code more scalable by splitting the platform specific code
into their own files. PSCI code resides in psci_<platform>.c now.
While we are at it, also create a platform_common_init() which takes
care of common tasks per platform. The MMIO setup code now becomes
more generic and scalable with the MMIO ranges now being converted
to makefile variables. Targets can over-ride them depending on their
needs.

Change-Id: I7c1a3b7d1945941ee48365ae22ffb7d0c0e79dd9
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

3 years ago[FOSS_TLK]platform: tegra: fix FIQ debugger registration and handling
Varun Wadekar [Thu, 27 Nov 2014 12:25:01 +0000]
[FOSS_TLK]platform: tegra: fix FIQ debugger registration and handling

* Remove the redundant SCR settings from mon_handle_get_fiq_regs
* Remove WDT_AVP usage. We use watchdogd daemon to pet the dog instead.
* Remove unused __mon_cpu_fiq_ns_stack variable.

Change-Id: Id9fc62a341da4c523deac0ddf5500874e3430301
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

3 years ago[FOSS_TLK]platform: ignore flow control programming on sims
Alex Van Brunt [Fri, 21 Nov 2014 18:14:38 +0000]
[FOSS_TLK]platform: ignore flow control programming on sims

Simulators do not support the flow controller. So, don't touch it.

Change-Id: I2b15a3d7fadd430648cad917e9fc8e9b57f5dd9f

3 years ago[FOSS_TLK]platform: tegra: psci: implement system reset functionality
Varun Wadekar [Mon, 17 Nov 2014 07:28:59 +0000]
[FOSS_TLK]platform: tegra: psci: implement system reset functionality

PSCI v0.2 introduced "system reset" function ID which expects the
monitor to reboot the system.

Change-Id: I9e7394b013ce829ab2145d121940d4aacd8cbf21
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

3 years ago[FOSS_TLK]platform: tegra: monitor: support PSCI_AFFINITY_INFO and PSCI_VERSION
Varun Wadekar [Thu, 13 Nov 2014 10:18:16 +0000]
[FOSS_TLK]platform: tegra: monitor: support PSCI_AFFINITY_INFO and PSCI_VERSION

PSCI v0.2 introduced the AFFINITY_INFO function ID in order to query
individual CPU states i.e. ON, ON_PENDING, OFF. The PSCI_VERSION call
return v0.2 to indicate support for PSCIv0.2 spec.

The PSCI kernel driver for v0.2 will follow this change soon as it
requires these basic function IDs to be supported by the monitor.

Change-Id: I27b8806e6392275790bbd57751c881184b2d9b03
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

3 years ago[FOSS_TLK]platform: tegra: psci: add debug print for sc7 exit
Prashant Gaikwad [Sat, 8 Nov 2014 06:45:34 +0000]
[FOSS_TLK]platform: tegra: psci: add debug print for sc7 exit

Change-Id: Id17ad2d265f376cba7fb81511263a2042c2687ad
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>

3 years ago[FOSS_TLK]platform: tegra: psci: new function IDs for pre/actual cluster switch
Varun Wadekar [Fri, 31 Oct 2014 11:12:05 +0000]
[FOSS_TLK]platform: tegra: psci: new function IDs for pre/actual cluster switch

According to the PSCI spec, during CPU suspend, every CPU must set the target
affinity level to the maximum that it can tolerate.

Since we use the cpu_suspend entry point during cluster switch, it means we
must set the target affinity level as 1 for all CPUs. In our current code,
during cluster switch, we send the same power state ID from all CPUs and use
the target affinity level to get to the last standing CPU. But if we have
to follow the above PSCI requirement, then we cannot use the target affinity
level for this purpose. Instead, we can use distinct power state IDs.

The last standing CPU will use power state ID = 31, while the other CPUs
will use power state ID = 30. This allows us to simplify the entire
cluster switch process and also comply with the PSCI spec.

Until the linux kernel driver gets in sync with the monitor code, we have
to keep the previous code path alive. Once the kernel driver is in sync,
we can remove "afflvl = 0" handling from plat_cluster_switch().

Verification:
============

"adb shell bpmp_sanity" PASSED for this change.

<snip>

heap: start 4000c680, len 3980, free 3060, max chunk 2bd0, low 252c
completed in 87 seconds
max retry count is 12
[pass: test_heap_end]
---------------
total subtests: 27
total failures: 0

<snip>

Change-Id: I2ac288b1fc4bc64c15480a68d02e126943970c8a
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

3 years ago[FOSS_TLK]monitor: restore debug after mmu init
Bo Yan [Thu, 30 Oct 2014 17:33:19 +0000]
[FOSS_TLK]monitor: restore debug after mmu init

L1 is flushed during CPU power down, so the previously saved debug
context only goes to L2. At power up, debug context restore is done
by reading from physical memory before MMU init, so it is not
successful.

Instead, restore debug context after MMU init, then it can be read
out of L2, which contains the previously saved context.

The side effect is that the first restore is no longer done at first
reset after CPU0 power up. This is acceptable, and much simpler than
running a cache clean to point of coherency with virtual address.

Change-Id: I120c7bfa8e4f86cf58602c75dd70c17b737b277e
Signed-off-by: Bo Yan <byan@nvidia.com>

3 years ago[FOSS_TLK][platform][tegra] do not prevent hvc/cc4 in c7
Sivaram Nair [Wed, 29 Oct 2014 02:06:59 +0000]
[FOSS_TLK][platform][tegra] do not prevent hvc/cc4 in c7

hvc/cc4 with all/some cores in c7 is a valid state - do not prevent it
(by overriding what kernel has setup).

Change-Id: Ib98a4c418a60661252fa25cf6e002aa4d37ba67f
Signed-off-by: Sivaram Nair <sivaramn@nvidia.com>

3 years ago[FOSS_TLK]monitor: save & restore debug registers
Bo Yan [Fri, 17 Oct 2014 00:37:49 +0000]
[FOSS_TLK]monitor: save & restore debug registers

Save and restore HW breakpoints and watchpoints across power cycle.
This code follows the recommendation in ARM debug architecture.

Since Denver, Cortex-A57, and Cortex-A53 all have 6 HW breakpoints
and 4 HW watchpoints, statically allocate 200 bytes for each CPU.
This is enough to hold 10 value registers and 10 control registers
for each of them since register width is 8 bytes. This also reserves
space for 10 other debug registers recommended by ARM for save and
restore.

For CPU off path, save context as well. It's unclear what makes more
sense, whether to save & restore the old context, or just clear
everything before going offline. Practically speaking, it is probably
more useful to keep breakpoints and watchpoints in sync among all
CPUs, hence save & restore debug context even in case of CPU offline.

This is not enabled for Denver build. This change is introducing some
test failures for Denver, which might be related to the differences
in terms of debug architecture implementation. However, for Denver,
it will make more sense to save & restore these registers in its
native code instead of changing monitor.

Change-Id: I45f58da010dfd0076bc163caf34dc968e7dcccef
Signed-off-by: Bo Yan <byan@nvidia.com>

3 years ago[FOSS_TLK][target][t210] add new target for T210 based devices
Varun Wadekar [Tue, 25 Mar 2014 11:55:03 +0000]
[FOSS_TLK][target][t210] add new target for T210 based devices

Use tegra4 as the CPU for now, but we might have to change this
in the future. Start with MONCPUS=1 for now.

Change-Id: I5663e65c1376265e8f4e75ce0fade7559dab3819
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

3 years ago[FOSS_TLK] Add secure_monitor files from tlk repo
Sharif Inamdar [Thu, 11 Jun 2015 05:41:27 +0000]
[FOSS_TLK] Add secure_monitor files from tlk repo

Since we have secure_monitor as independent repo,
moving the files from tlk repo into secure_monitor
repo

Signed-off-by: Sharif Inamdar <isharif@nvidia.com>