video: tegra: host: nvdla: Avoid contiguos alloc
[linux-nvidia.git] / sound / soc / tegra-alt / tegra210_i2s_alt.c
1 /*
2  * tegra210_i2s.c - Tegra210 I2S driver
3  *
4  * Copyright (c) 2014-2019 NVIDIA CORPORATION.  All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
17  */
18
19 #include <linux/delay.h>
20 #include <linux/clk.h>
21 #include <linux/device.h>
22 #include <linux/io.h>
23 #include <linux/module.h>
24 #include <linux/of.h>
25 #include <linux/platform_device.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/regmap.h>
28 #include <sound/core.h>
29 #include <sound/pcm.h>
30 #include <sound/pcm_params.h>
31 #include <sound/soc.h>
32 #include <linux/pinctrl/pinconf-tegra.h>
33 #include <linux/regulator/consumer.h>
34 #include <linux/of_device.h>
35 #include <soc/tegra/chip-id.h>
36 #include <linux/pm_domain.h>
37
38 #include "tegra210_xbar_alt.h"
39 #include "tegra210_i2s_alt.h"
40
41 #define DRV_NAME "tegra210-i2s"
42
43
44 static const struct reg_default tegra210_i2s_reg_defaults[] = {
45         { TEGRA210_I2S_AXBAR_RX_INT_MASK, 0x00000003},
46         { TEGRA210_I2S_AXBAR_RX_CIF_CTRL, 0x00007700},
47         { TEGRA210_I2S_AXBAR_TX_INT_MASK, 0x00000003},
48         { TEGRA210_I2S_AXBAR_TX_CIF_CTRL, 0x00007700},
49         { TEGRA210_I2S_CG, 0x1},
50         { TEGRA210_I2S_TIMING, 0x0000001f},
51 };
52
53 static void tegra210_i2s_set_slot_ctrl(struct regmap *regmap,
54                                 unsigned int total_slots,
55                                 unsigned int tx_slot_mask,
56                                 unsigned int rx_slot_mask)
57 {
58         regmap_write(regmap, TEGRA210_I2S_SLOT_CTRL, total_slots - 1);
59         regmap_write(regmap, TEGRA210_I2S_AXBAR_TX_SLOT_CTRL,
60                 tx_slot_mask);
61         regmap_write(regmap, TEGRA210_I2S_AXBAR_RX_SLOT_CTRL,
62                 rx_slot_mask);
63 }
64
65 static int tegra210_i2s_set_clock_rate(struct device *dev, int clock_rate)
66 {
67         unsigned int val;
68         struct tegra210_i2s *i2s = dev_get_drvdata(dev);
69         int ret;
70
71         regmap_read(i2s->regmap, TEGRA210_I2S_CTRL, &val);
72         val &= TEGRA210_I2S_CTRL_MASTER_EN;
73
74         /* no need to set rates if I2S is being operated in slave */
75         if (!val)
76                 return 0;
77
78         /* skip for fpga units */
79         if (tegra_platform_is_unit_fpga() || tegra_platform_is_fpga())
80                 return 0;
81
82         ret = clk_set_rate(i2s->clk_i2s, clock_rate);
83         if (ret) {
84                 dev_err(dev, "Can't set I2S clock rate: %d\n", ret);
85                 return ret;
86         }
87
88         if (!IS_ERR(i2s->clk_sync_input)) {
89                 /*
90                  * other I/O modules in AHUB can use i2s bclk as reference
91                  * clock. Below sets sync input clock rate as per bclk,
92                  * which can be used as input to other I/O modules.
93                  */
94                 ret = clk_set_rate(i2s->clk_sync_input, clock_rate);
95                 if (ret) {
96                         dev_err(dev, "Can't set I2S sync input clock rate\n");
97                         return ret;
98                 }
99         }
100
101         return 0;
102 }
103
104 static int tegra210_i2s_sw_reset(struct tegra210_i2s *i2s,
105                                 int direction, int timeout)
106 {
107         unsigned int sw_reset_reg, sw_reset_mask, sw_reset_en, sw_reset_default;
108         unsigned int tx_cif_ctrl, rx_cif_ctrl, tx_ctrl, rx_ctrl, ctrl, val;
109         int wait = timeout;
110
111         regmap_read(i2s->regmap, TEGRA210_I2S_AXBAR_TX_CIF_CTRL, &tx_cif_ctrl);
112         regmap_read(i2s->regmap, TEGRA210_I2S_AXBAR_RX_CIF_CTRL, &rx_cif_ctrl);
113         regmap_read(i2s->regmap, TEGRA210_I2S_AXBAR_TX_CTRL, &tx_ctrl);
114         regmap_read(i2s->regmap, TEGRA210_I2S_AXBAR_RX_CTRL, &rx_ctrl);
115         regmap_read(i2s->regmap, TEGRA210_I2S_CTRL, &ctrl);
116
117         if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
118                 sw_reset_reg = TEGRA210_I2S_AXBAR_RX_SOFT_RESET;
119                 sw_reset_mask = TEGRA210_I2S_AXBAR_RX_SOFT_RESET_MASK;
120                 sw_reset_en = TEGRA210_I2S_AXBAR_RX_SOFT_RESET_EN;
121                 sw_reset_default = TEGRA210_I2S_AXBAR_RX_SOFT_RESET_DEFAULT;
122         } else {
123                 sw_reset_reg = TEGRA210_I2S_AXBAR_TX_SOFT_RESET;
124                 sw_reset_mask = TEGRA210_I2S_AXBAR_TX_SOFT_RESET_MASK;
125                 sw_reset_en = TEGRA210_I2S_AXBAR_TX_SOFT_RESET_EN;
126                 sw_reset_default = TEGRA210_I2S_AXBAR_TX_SOFT_RESET_DEFAULT;
127         }
128
129         regmap_update_bits(i2s->regmap, sw_reset_reg, sw_reset_mask, sw_reset_en);
130
131         do {
132                 regmap_read(i2s->regmap, sw_reset_reg, &val);
133                 wait--;
134                 if (!wait)
135                         return -EINVAL;
136         } while (val & sw_reset_mask);
137
138         regmap_update_bits(i2s->regmap, sw_reset_reg, sw_reset_mask, sw_reset_default);
139
140         regmap_write(i2s->regmap, TEGRA210_I2S_AXBAR_TX_CIF_CTRL, tx_cif_ctrl);
141         regmap_write(i2s->regmap, TEGRA210_I2S_AXBAR_RX_CIF_CTRL, rx_cif_ctrl);
142         regmap_write(i2s->regmap, TEGRA210_I2S_AXBAR_TX_CTRL, tx_ctrl);
143         regmap_write(i2s->regmap, TEGRA210_I2S_AXBAR_RX_CTRL, rx_ctrl);
144         regmap_write(i2s->regmap, TEGRA210_I2S_CTRL, ctrl);
145
146         return 0;
147 }
148
149 static int tegra210_i2s_get_status(struct tegra210_i2s *i2s,
150                                 int direction)
151 {
152         unsigned int status_reg, val;
153
154         status_reg = (direction == SNDRV_PCM_STREAM_PLAYBACK) ?
155                 TEGRA210_I2S_AXBAR_RX_STATUS :
156                 TEGRA210_I2S_AXBAR_TX_STATUS;
157
158         regmap_read(i2s->regmap, status_reg, &val);
159         val = val & 0x00000001;
160
161         return val;
162 }
163
164 static int tegra210_i2s_rx_stop(struct snd_soc_dapm_widget *w,
165                                 struct snd_kcontrol *kcontrol, int event)
166 {
167         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
168         struct device *dev = codec->dev;
169         struct tegra210_i2s *i2s = dev_get_drvdata(dev);
170         int dcnt = 10, ret;
171
172         /* wait until I2S RX status is disabled;
173         ADMAIF is first disabled followed by I2S */
174         while (tegra210_i2s_get_status(i2s, SNDRV_PCM_STREAM_CAPTURE) &&
175                         dcnt--)
176                 udelay(100);
177
178         /* HW needs sw reset to make sure previous transaction be clean */
179         ret = tegra210_i2s_sw_reset(i2s, SNDRV_PCM_STREAM_CAPTURE, 0xffff);
180         if (ret) {
181                 dev_err(dev, "Failed at I2S%d_RX sw reset\n", dev->id);
182                 return ret;
183         }
184         return 0;
185 }
186
187 static int tegra210_i2s_tx_stop(struct snd_soc_dapm_widget *w,
188                                 struct snd_kcontrol *kcontrol, int event)
189 {
190         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
191         struct device *dev = codec->dev;
192         struct tegra210_i2s *i2s = dev_get_drvdata(dev);
193         int dcnt = 10, ret;
194
195         /* wait until  I2S TX status is disabled;
196         ADMAIF is first disabled followed by I2S */
197         while (tegra210_i2s_get_status(i2s, SNDRV_PCM_STREAM_PLAYBACK) &&
198                         dcnt--)
199                 udelay(100);
200
201         /* HW needs sw reset to make sure previous transaction be clean */
202         ret = tegra210_i2s_sw_reset(i2s, SNDRV_PCM_STREAM_PLAYBACK, 0xffff);
203         if (ret) {
204                 dev_err(dev, "Failed at I2S%d_TX sw reset\n", dev->id);
205                 return ret;
206         }
207         return 0;
208 }
209
210 static int tegra210_i2s_runtime_suspend(struct device *dev)
211 {
212         struct tegra210_i2s *i2s = dev_get_drvdata(dev);
213
214         regcache_cache_only(i2s->regmap, true);
215         if (!(tegra_platform_is_unit_fpga() || tegra_platform_is_fpga())) {
216                 regcache_mark_dirty(i2s->regmap);
217                 clk_disable_unprepare(i2s->clk_i2s);
218         }
219
220         return 0;
221 }
222
223 static int tegra210_i2s_runtime_resume(struct device *dev)
224 {
225         struct tegra210_i2s *i2s = dev_get_drvdata(dev);
226         int ret;
227
228         if (!(tegra_platform_is_unit_fpga() || tegra_platform_is_fpga())) {
229                 ret = clk_prepare_enable(i2s->clk_i2s);
230                 if (ret) {
231                         dev_err(dev, "clk_enable failed: %d\n", ret);
232                         return ret;
233                 }
234         }
235
236         regcache_cache_only(i2s->regmap, false);
237         regcache_sync(i2s->regmap);
238
239         return 0;
240 }
241
242 static void tegra210_i2s_set_data_offset(struct tegra210_i2s *i2s,
243                                          unsigned int data_offset)
244 {
245         unsigned int reg, mask, shift;
246
247         reg = TEGRA210_I2S_AXBAR_TX_CTRL;
248         mask = TEGRA210_I2S_AXBAR_TX_CTRL_DATA_OFFSET_MASK;
249         shift = TEGRA210_I2S_AXBAR_TX_CTRL_DATA_OFFSET_SHIFT;
250         regmap_update_bits(i2s->regmap, reg, mask, data_offset << shift);
251
252         reg = TEGRA210_I2S_AXBAR_RX_CTRL;
253         mask = TEGRA210_I2S_AXBAR_RX_CTRL_DATA_OFFSET_MASK;
254         shift = TEGRA210_I2S_AXBAR_RX_CTRL_DATA_OFFSET_SHIFT;
255         regmap_update_bits(i2s->regmap, reg, mask, data_offset << shift);
256 }
257
258 static void tegra210_i2s_set_rjm_offset(struct tegra210_i2s *i2s,
259                                         unsigned int sample_size)
260 {
261         unsigned int data_offset;
262
263         if (i2s->bclk_ratio > 1)
264                 data_offset = sample_size * (i2s->bclk_ratio - 1);
265         else
266                 data_offset = 0;
267
268         tegra210_i2s_set_data_offset(i2s, data_offset);
269 }
270
271 static int tegra210_i2s_set_fmt(struct snd_soc_dai *dai,
272                                 unsigned int fmt)
273 {
274         struct tegra210_i2s *i2s = snd_soc_dai_get_drvdata(dai);
275         unsigned int mask, val;
276
277         mask = TEGRA210_I2S_CTRL_MASTER_EN_MASK;
278         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
279         case SND_SOC_DAIFMT_CBS_CFS:
280                 val = 0;
281                 break;
282         case SND_SOC_DAIFMT_CBM_CFM:
283                 val = TEGRA210_I2S_CTRL_MASTER_EN;
284                 break;
285         default:
286                 return -EINVAL;
287         }
288
289         mask |= TEGRA210_I2S_CTRL_FRAME_FORMAT_MASK |
290                 TEGRA210_I2S_CTRL_LRCK_POLARITY_MASK;
291         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
292         case SND_SOC_DAIFMT_DSP_A:
293                 val |= TEGRA210_I2S_CTRL_FRAME_FORMAT_FSYNC_MODE;
294                 val |= TEGRA210_I2S_CTRL_LRCK_POLARITY_HIGH;
295                 tegra210_i2s_set_data_offset(i2s, 1);
296                 break;
297         case SND_SOC_DAIFMT_DSP_B:
298                 val |= TEGRA210_I2S_CTRL_FRAME_FORMAT_FSYNC_MODE;
299                 val |= TEGRA210_I2S_CTRL_LRCK_POLARITY_HIGH;
300                 tegra210_i2s_set_data_offset(i2s, 0);
301                 break;
302         /* I2S mode has data offset of 1 */
303         case SND_SOC_DAIFMT_I2S:
304                 val |= TEGRA210_I2S_CTRL_FRAME_FORMAT_LRCK_MODE;
305                 val |= TEGRA210_I2S_CTRL_LRCK_POLARITY_LOW;
306                 tegra210_i2s_set_data_offset(i2s, 1);
307                 break;
308         /*
309          * For RJ mode data offset is dependent on the sample size
310          * and the bclk ratio, and so is set when hw_params is called.
311          */
312         case SND_SOC_DAIFMT_RIGHT_J:
313                 val |= TEGRA210_I2S_CTRL_FRAME_FORMAT_LRCK_MODE;
314                 val |= TEGRA210_I2S_CTRL_LRCK_POLARITY_HIGH;
315                 break;
316         case SND_SOC_DAIFMT_LEFT_J:
317                 val |= TEGRA210_I2S_CTRL_FRAME_FORMAT_LRCK_MODE;
318                 val |= TEGRA210_I2S_CTRL_LRCK_POLARITY_HIGH;
319                 tegra210_i2s_set_data_offset(i2s, 0);
320                 break;
321         default:
322                 return -EINVAL;
323         }
324
325         mask |= TEGRA210_I2S_CTRL_EDGE_CTRL_MASK;
326         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
327         case SND_SOC_DAIFMT_NB_NF:
328                 val |= TEGRA210_I2S_CTRL_EDGE_CTRL_POS_EDGE;
329                 break;
330         case SND_SOC_DAIFMT_NB_IF:
331                 val |= TEGRA210_I2S_CTRL_EDGE_CTRL_POS_EDGE;
332                 val ^= TEGRA210_I2S_CTRL_LRCK_POLARITY_MASK;
333                 break;
334         case SND_SOC_DAIFMT_IB_NF:
335                 val |= TEGRA210_I2S_CTRL_EDGE_CTRL_NEG_EDGE;
336                 break;
337         case SND_SOC_DAIFMT_IB_IF:
338                 val |= TEGRA210_I2S_CTRL_EDGE_CTRL_NEG_EDGE;
339                 val ^= TEGRA210_I2S_CTRL_LRCK_POLARITY_MASK;
340                 break;
341         default:
342                 return -EINVAL;
343         }
344
345         regmap_update_bits(i2s->regmap, TEGRA210_I2S_CTRL, mask, val);
346         /* FIXME: global enabling */
347         regmap_update_bits(i2s->regmap, TEGRA210_I2S_ENABLE,
348                                         TEGRA210_I2S_EN_MASK, TEGRA210_I2S_EN);
349         regmap_update_bits(i2s->regmap, TEGRA210_I2S_CTRL,
350                 TEGRA210_I2S_CTRL_FSYNC_WIDTH_MASK,
351                 i2s->fsync_width << TEGRA210_I2S_CTRL_FSYNC_WIDTH_SHIFT);
352
353         i2s->format = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
354
355         return 0;
356 }
357
358 static int tegra210_i2s_set_tdm_slot(struct snd_soc_dai *dai,
359                 unsigned int tx_mask, unsigned int rx_mask,
360                 int slots, int slot_width)
361 {
362         struct tegra210_i2s *i2s = snd_soc_dai_get_drvdata(dai);
363
364         /* copy the required tx and rx mask */
365         i2s->tx_mask = (tx_mask > 0xFFFF) ? 0xFFFF : tx_mask;
366         i2s->rx_mask = (rx_mask > 0xFFFF) ? 0xFFFF : rx_mask;
367
368         return 0;
369 }
370
371 static int tegra210_i2s_set_dai_bclk_ratio(struct snd_soc_dai *dai,
372                                            unsigned int ratio)
373 {
374         struct tegra210_i2s *i2s = snd_soc_dai_get_drvdata(dai);
375
376         i2s->bclk_ratio = ratio;
377
378         return 0;
379 }
380
381 static int tegra210_i2s_get_format(struct snd_kcontrol *kcontrol,
382         struct snd_ctl_elem_value *ucontrol)
383 {
384         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
385         struct tegra210_i2s *i2s = snd_soc_codec_get_drvdata(codec);
386
387         /* get the format control flag */
388         if (strstr(kcontrol->id.name, "input"))
389                 ucontrol->value.integer.value[0] = i2s->format_in;
390         else if (strstr(kcontrol->id.name, "codec"))
391                 ucontrol->value.integer.value[0] = i2s->codec_bit_format;
392         else if (strstr(kcontrol->id.name, "Sample Rate"))
393                 ucontrol->value.integer.value[0] = i2s->sample_rate_via_control;
394         else if (strstr(kcontrol->id.name, "Channels"))
395                 ucontrol->value.integer.value[0] = i2s->channels_via_control;
396         else if (strstr(kcontrol->id.name, "Capture stereo to mono"))
397                 ucontrol->value.integer.value[0] =
398                                         i2s->stereo_to_mono[I2S_TX_PATH];
399         else if (strstr(kcontrol->id.name, "Capture mono to stereo"))
400                 ucontrol->value.integer.value[0] =
401                                         i2s->mono_to_stereo[I2S_TX_PATH];
402         else if (strstr(kcontrol->id.name, "Playback stereo to mono"))
403                 ucontrol->value.integer.value[0] =
404                                         i2s->stereo_to_mono[I2S_RX_PATH];
405         else if (strstr(kcontrol->id.name, "Playback mono to stereo"))
406                 ucontrol->value.integer.value[0] =
407                                         i2s->mono_to_stereo[I2S_RX_PATH];
408         else if (strstr(kcontrol->id.name, "Playback FIFO threshold"))
409                 ucontrol->value.integer.value[0] = i2s->rx_fifo_th;
410         else if (strstr(kcontrol->id.name, "BCLK Ratio"))
411                 ucontrol->value.integer.value[0] = i2s->bclk_ratio;
412
413         return 0;
414 }
415
416 static int tegra210_i2s_put_format(struct snd_kcontrol *kcontrol,
417         struct snd_ctl_elem_value *ucontrol)
418 {
419         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
420         struct tegra210_i2s *i2s = snd_soc_codec_get_drvdata(codec);
421         int value = ucontrol->value.integer.value[0];
422
423         /* set the format control flag */
424         if (strstr(kcontrol->id.name, "input"))
425                 i2s->format_in = value;
426         else if (strstr(kcontrol->id.name, "codec"))
427                 i2s->codec_bit_format = value;
428         else if (strstr(kcontrol->id.name, "Sample Rate"))
429                 i2s->sample_rate_via_control = value;
430         else if (strstr(kcontrol->id.name, "Channels"))
431                 i2s->channels_via_control = value;
432         else if (strstr(kcontrol->id.name, "Capture stereo to mono"))
433                 i2s->stereo_to_mono[I2S_TX_PATH] = value;
434         else if (strstr(kcontrol->id.name, "Capture mono to stereo"))
435                 i2s->mono_to_stereo[I2S_TX_PATH] = value;
436         else if (strstr(kcontrol->id.name, "Playback stereo to mono"))
437                 i2s->stereo_to_mono[I2S_RX_PATH] = value;
438         else if (strstr(kcontrol->id.name, "Playback mono to stereo"))
439                 i2s->mono_to_stereo[I2S_RX_PATH] = value;
440         else if (strstr(kcontrol->id.name, "Playback FIFO threshold")) {
441                 if (value >= 0 && value < TEGRA210_I2S_RX_FIFO_DEPTH)
442                         i2s->rx_fifo_th = value;
443                 else
444                         return -EINVAL;
445         } else if (strstr(kcontrol->id.name, "BCLK Ratio"))
446                 i2s->bclk_ratio = value;
447
448         return 0;
449 }
450
451 static const char * const tegra210_i2s_format_text[] = {
452         "None",
453         "16",
454         "32",
455 };
456
457 static const int tegra210_i2s_fmt_values[] = {
458         0,
459         TEGRA210_AUDIOCIF_BITS_16,
460         TEGRA210_AUDIOCIF_BITS_32,
461 };
462
463 static const int tegra210_i2s_sample_size[] = {
464         0,
465         16,
466         32,
467 };
468
469 static const struct soc_enum tegra210_i2s_format_enum =
470         SOC_ENUM_SINGLE(SND_SOC_NOPM, 0,
471                 ARRAY_SIZE(tegra210_i2s_format_text),
472                 tegra210_i2s_format_text);
473
474 static int tegra210_i2s_startup(struct snd_pcm_substream *substream,
475                                  struct snd_soc_dai *dai)
476 {
477         struct device *dev = dai->dev;
478         struct tegra210_i2s *i2s = dev_get_drvdata(dev);
479         int ret;
480
481         if (!(tegra_platform_is_unit_fpga() || tegra_platform_is_fpga()) &&
482                                                         !i2s->loopback) {
483                 if (i2s->prod_name != NULL) {
484                         ret = tegra_pinctrl_config_prod(dev, i2s->prod_name);
485                         if (ret < 0) {
486                                 dev_warn(dev, "Failed to set %s setting\n",
487                                                 i2s->prod_name);
488                         }
489                 }
490
491                 if (i2s->num_supplies > 0) {
492                         ret = regulator_bulk_enable(i2s->num_supplies,
493                                                                 i2s->supplies);
494                         if (ret < 0)
495                                 dev_err(dev, "failed to enable i2s io regulator\n");
496                 }
497         }
498
499         return 0;
500 }
501
502 static void tegra210_i2s_shutdown(struct snd_pcm_substream *substream,
503                                  struct snd_soc_dai *dai)
504 {
505         struct device *dev = dai->dev;
506         struct tegra210_i2s *i2s = dev_get_drvdata(dev);
507         int ret;
508
509         if (!(tegra_platform_is_unit_fpga() || tegra_platform_is_fpga())) {
510                 if (i2s->num_supplies > 0) {
511                         ret = regulator_bulk_disable(i2s->num_supplies,
512                                                                 i2s->supplies);
513                         if (ret < 0) {
514                                 dev_err(dev,
515                                 "failed to disable i2s io regulator\n");
516                         }
517                 }
518         }
519 }
520
521 static int tegra210_i2s_hw_params(struct snd_pcm_substream *substream,
522                                  struct snd_pcm_hw_params *params,
523                                  struct snd_soc_dai *dai)
524 {
525         struct device *dev = dai->dev;
526         struct tegra210_i2s *i2s = snd_soc_dai_get_drvdata(dai);
527         unsigned int mask, val, reg, frame_format, rx_mask, tx_mask;
528         int ret, sample_size, channels, srate, i2sclock, bitcnt, max_th;
529         struct tegra210_xbar_cif_conf cif_conf;
530
531         memset(&cif_conf, 0, sizeof(struct tegra210_xbar_cif_conf));
532
533         channels = params_channels(params);
534         if (channels < 1) {
535                 dev_err(dev, "Doesn't support %d channels\n", channels);
536                 return -EINVAL;
537         }
538
539         mask = TEGRA210_I2S_CTRL_BIT_SIZE_MASK;
540         switch (params_format(params)) {
541         case SNDRV_PCM_FORMAT_S8:
542                 val = TEGRA210_I2S_CTRL_BIT_SIZE_8;
543                 sample_size = 8;
544                 cif_conf.audio_bits = TEGRA210_AUDIOCIF_BITS_8;
545                 cif_conf.client_bits = TEGRA210_AUDIOCIF_BITS_8;
546                 break;
547         case SNDRV_PCM_FORMAT_S16_LE:
548                 val = TEGRA210_I2S_CTRL_BIT_SIZE_16;
549                 sample_size = 16;
550                 cif_conf.audio_bits = TEGRA210_AUDIOCIF_BITS_16;
551                 cif_conf.client_bits = TEGRA210_AUDIOCIF_BITS_16;
552                 break;
553         case SNDRV_PCM_FORMAT_S24_LE:
554                 val = TEGRA210_I2S_CTRL_BIT_SIZE_24;
555                 sample_size = 24;
556                 cif_conf.audio_bits = TEGRA210_AUDIOCIF_BITS_24;
557                 cif_conf.client_bits = TEGRA210_AUDIOCIF_BITS_24;
558                 break;
559         case SNDRV_PCM_FORMAT_S32_LE:
560                 val = TEGRA210_I2S_CTRL_BIT_SIZE_32;
561                 sample_size = 32;
562                 cif_conf.audio_bits = TEGRA210_AUDIOCIF_BITS_32;
563                 cif_conf.client_bits = TEGRA210_AUDIOCIF_BITS_32;
564                 break;
565         default:
566                 dev_err(dev, "Wrong format!\n");
567                 return -EINVAL;
568         }
569
570         if (i2s->codec_bit_format) {
571                 val = tegra210_i2s_fmt_values[i2s->codec_bit_format];
572                 sample_size = tegra210_i2s_sample_size[i2s->codec_bit_format];
573                 cif_conf.client_bits = tegra210_i2s_fmt_values[i2s->codec_bit_format];
574         }
575
576         regmap_update_bits(i2s->regmap, TEGRA210_I2S_CTRL, mask, val);
577
578         srate = params_rate(params);
579
580         if (i2s->sample_rate_via_control)
581                 srate = i2s->sample_rate_via_control;
582
583         if (i2s->channels_via_control) {
584                 channels = i2s->channels_via_control;
585                 rx_mask = tx_mask = (1 << channels) - 1;
586         } else {
587                 rx_mask = i2s->rx_mask;
588                 tx_mask = i2s->tx_mask;
589         }
590
591         regmap_read(i2s->regmap, TEGRA210_I2S_CTRL, &val);
592
593         frame_format = val & TEGRA210_I2S_CTRL_FRAME_FORMAT_MASK;
594
595         if (frame_format == TEGRA210_I2S_CTRL_FRAME_FORMAT_FSYNC_MODE) {
596                 tegra210_i2s_set_slot_ctrl(i2s->regmap, channels, tx_mask,
597                                            rx_mask);
598                 cif_conf.audio_channels = channels;
599                 cif_conf.client_channels = channels;
600         } else {
601                 cif_conf.audio_channels = channels;
602                 cif_conf.client_channels = (channels == 1) ? 2 : channels;
603         }
604
605         i2sclock = srate * sample_size * cif_conf.client_channels;
606
607         if (i2s->bclk_ratio != 0)
608                 i2sclock *= i2s->bclk_ratio;
609
610         bitcnt = (i2sclock / srate) - 1;
611
612         if (frame_format == TEGRA210_I2S_FRAME_FORMAT_LRCK)
613                 bitcnt >>= 1;
614
615         if ((bitcnt < 0) ||
616                 (bitcnt > TEGRA210_I2S_TIMING_CHANNEL_BIT_CNT_MASK)) {
617                 dev_err(dev, "Can't set channel bit count\n");
618                 return -EINVAL;
619         }
620
621         ret = tegra210_i2s_set_clock_rate(dev, i2sclock);
622         if (ret) {
623                 dev_err(dev, "Can't set I2S clock rate: %d\n", ret);
624                 return ret;
625         }
626
627         val = bitcnt << TEGRA210_I2S_TIMING_CHANNEL_BIT_CNT_SHIFT;
628
629         if (i2sclock % (2 * srate))
630                 val |= TEGRA210_I2S_TIMING_NON_SYM_EN;
631
632         regmap_write(i2s->regmap, TEGRA210_I2S_TIMING, val);
633
634         /* As a COCEC DAI, CAPTURE is transmit */
635         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
636                 reg = TEGRA210_I2S_AXBAR_RX_CIF_CTRL;
637                 if (i2s->mono_to_stereo[I2S_RX_PATH] > 0) {
638                         cif_conf.audio_channels = 1;
639                         cif_conf.client_channels = 2;
640                         cif_conf.mono_conv =
641                                         i2s->mono_to_stereo[I2S_RX_PATH] - 1;
642                 } else if (i2s->stereo_to_mono[I2S_RX_PATH] > 0) {
643                         cif_conf.audio_channels = 2;
644                         cif_conf.client_channels = 1;
645                         cif_conf.stereo_conv =
646                                         i2s->stereo_to_mono[I2S_RX_PATH] - 1;
647                 }
648
649                 /* RX FIFO threshold interms of frames */
650                 max_th = (TEGRA210_I2S_RX_FIFO_DEPTH / channels) - 1;
651                 if (i2s->rx_fifo_th > max_th) { /* error handling */
652                         cif_conf.threshold = max_th;
653                         i2s->rx_fifo_th = max_th;
654                 } else
655                         cif_conf.threshold = i2s->rx_fifo_th;
656         } else {
657                 if (i2s->mono_to_stereo[I2S_TX_PATH] > 0) {
658                         cif_conf.audio_channels = 2;
659                         cif_conf.client_channels = 1;
660                         cif_conf.mono_conv =
661                                         i2s->mono_to_stereo[I2S_TX_PATH] - 1;
662                 } else if (i2s->stereo_to_mono[I2S_TX_PATH] > 0) {
663                         cif_conf.audio_channels = 1;
664                         cif_conf.client_channels = 2;
665                         cif_conf.stereo_conv =
666                                         i2s->stereo_to_mono[I2S_TX_PATH] - 1;
667                 }
668
669                 if (i2s->format_in)
670                         cif_conf.audio_bits =
671                                 tegra210_i2s_fmt_values[i2s->format_in];
672                 reg = TEGRA210_I2S_AXBAR_TX_CIF_CTRL;
673         }
674
675         tegra210_xbar_set_cif(i2s->regmap, reg, &cif_conf);
676
677         if (i2s->format == SND_SOC_DAIFMT_RIGHT_J)
678                 tegra210_i2s_set_rjm_offset(i2s, sample_size);
679
680         if (i2s->enable_cya)
681                 regmap_write(i2s->regmap, TEGRA210_I2S_CYA, 1);
682
683         return 0;
684 }
685
686 static struct snd_soc_dai_ops tegra210_i2s_dai_ops = {
687         .set_fmt        = tegra210_i2s_set_fmt,
688         .hw_params      = tegra210_i2s_hw_params,
689         .set_bclk_ratio = tegra210_i2s_set_dai_bclk_ratio,
690         .set_tdm_slot   = tegra210_i2s_set_tdm_slot,
691         .startup        = tegra210_i2s_startup,
692         .shutdown       = tegra210_i2s_shutdown,
693 };
694
695 static struct snd_soc_dai_driver tegra210_i2s_dais[] = {
696         {
697                 .name = "CIF",
698                 .playback = {
699                         .stream_name = "CIF Receive",
700                         .channels_min = 1,
701                         .channels_max = 16,
702                         .rates = SNDRV_PCM_RATE_8000_192000,
703                         .formats = SNDRV_PCM_FMTBIT_S8 |
704                                 SNDRV_PCM_FMTBIT_S16_LE |
705                                 SNDRV_PCM_FMTBIT_S24_LE |
706                                 SNDRV_PCM_FMTBIT_S32_LE,
707                 },
708                 .capture = {
709                         .stream_name = "CIF Transmit",
710                         .channels_min = 1,
711                         .channels_max = 16,
712                         .rates = SNDRV_PCM_RATE_8000_192000,
713                         .formats = SNDRV_PCM_FMTBIT_S8 |
714                                 SNDRV_PCM_FMTBIT_S16_LE |
715                                 SNDRV_PCM_FMTBIT_S24_LE |
716                                 SNDRV_PCM_FMTBIT_S32_LE,
717                 },
718         },
719         {
720                 .name = "DAP",
721                 .playback = {
722                         .stream_name = "DAP Receive",
723                         .channels_min = 1,
724                         .channels_max = 16,
725                         .rates = SNDRV_PCM_RATE_8000_192000,
726                         .formats = SNDRV_PCM_FMTBIT_S8 |
727                                 SNDRV_PCM_FMTBIT_S16_LE |
728                                 SNDRV_PCM_FMTBIT_S24_LE |
729                                 SNDRV_PCM_FMTBIT_S32_LE,
730                 },
731                 .capture = {
732                         .stream_name = "DAP Transmit",
733                         .channels_min = 1,
734                         .channels_max = 16,
735                         .rates = SNDRV_PCM_RATE_8000_192000,
736                         .formats = SNDRV_PCM_FMTBIT_S8 |
737                                 SNDRV_PCM_FMTBIT_S16_LE |
738                                 SNDRV_PCM_FMTBIT_S24_LE |
739                                 SNDRV_PCM_FMTBIT_S32_LE,
740                 },
741                 .ops = &tegra210_i2s_dai_ops,
742                 .symmetric_rates = 1,
743         }
744 };
745
746 static int tegra210_i2s_loopback_get(struct snd_kcontrol *kcontrol,
747         struct snd_ctl_elem_value *ucontrol)
748 {
749         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
750         struct tegra210_i2s *i2s = snd_soc_codec_get_drvdata(codec);
751
752         ucontrol->value.integer.value[0] = i2s->loopback;
753
754         return 0;
755 }
756
757 static int tegra210_i2s_loopback_put(struct snd_kcontrol *kcontrol,
758         struct snd_ctl_elem_value *ucontrol)
759 {
760         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
761         struct tegra210_i2s *i2s = snd_soc_codec_get_drvdata(codec);
762
763         i2s->loopback = ucontrol->value.integer.value[0];
764
765         regmap_update_bits(i2s->regmap, TEGRA210_I2S_CTRL,
766                 TEGRA210_I2S_CTRL_LPBK_MASK,
767                 i2s->loopback << TEGRA210_I2S_CTRL_LPBK_SHIFT);
768
769         return 0;
770 }
771
772 static int tegra210_i2s_get_bclk_ratio(struct snd_kcontrol *kcontrol,
773                                        struct snd_ctl_elem_value *ucontrol)
774 {
775         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
776         struct tegra210_i2s *i2s = snd_soc_codec_get_drvdata(codec);
777
778         ucontrol->value.integer.value[0] = i2s->bclk_ratio;
779
780         return 0;
781 }
782
783 static int tegra210_i2s_put_bclk_ratio(struct snd_kcontrol *kcontrol,
784                                        struct snd_ctl_elem_value *ucontrol)
785 {
786         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
787         struct tegra210_i2s *i2s = snd_soc_codec_get_drvdata(codec);
788
789         i2s->bclk_ratio = ucontrol->value.integer.value[0];
790
791         return 0;
792 }
793
794 static int tegra210_i2s_fsync_width_get(struct snd_kcontrol *kcontrol,
795                                         struct snd_ctl_elem_value *ucontrol)
796 {
797         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
798         struct tegra210_i2s *i2s = snd_soc_codec_get_drvdata(codec);
799
800         ucontrol->value.integer.value[0] = i2s->fsync_width;
801
802         return 0;
803 }
804
805 static int tegra210_i2s_fsync_width_put(struct snd_kcontrol *kcontrol,
806                                         struct snd_ctl_elem_value *ucontrol)
807 {
808         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
809         struct tegra210_i2s *i2s = snd_soc_codec_get_drvdata(codec);
810
811         i2s->fsync_width = ucontrol->value.integer.value[0];
812
813         regmap_update_bits(i2s->regmap, TEGRA210_I2S_CTRL,
814                            TEGRA210_I2S_CTRL_FSYNC_WIDTH_MASK,
815                            i2s->fsync_width <<
816                            TEGRA210_I2S_CTRL_FSYNC_WIDTH_SHIFT);
817
818         return 0;
819 }
820
821 static const char * const tegra210_i2s_stereo_conv_text[] = {
822         "None", "CH0", "CH1", "AVG",
823 };
824
825 static const char * const tegra210_i2s_mono_conv_text[] = {
826         "None", "ZERO", "COPY",
827 };
828
829 static const struct soc_enum tegra210_i2s_mono_conv_enum =
830         SOC_ENUM_SINGLE(SND_SOC_NOPM, 0,
831                 ARRAY_SIZE(tegra210_i2s_mono_conv_text),
832                 tegra210_i2s_mono_conv_text);
833
834 static const struct soc_enum tegra210_i2s_stereo_conv_enum =
835         SOC_ENUM_SINGLE(SND_SOC_NOPM, 0,
836                 ARRAY_SIZE(tegra210_i2s_stereo_conv_text),
837                 tegra210_i2s_stereo_conv_text);
838
839 #define NV_SOC_SINGLE_RANGE_EXT(xname, xmin, xmax, xget, xput) \
840 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
841         .info = snd_soc_info_xr_sx, .get = xget, .put = xput, \
842         .private_value = (unsigned long)&(struct soc_mixer_control) \
843                 {.invert = 0, .min = xmin, .max = xmax, \
844                 .platform_max = xmax}}
845
846 static const struct snd_kcontrol_new tegra210_i2s_controls[] = {
847         SOC_SINGLE_EXT("Loopback", SND_SOC_NOPM, 0, 1, 0,
848                 tegra210_i2s_loopback_get, tegra210_i2s_loopback_put),
849         SOC_ENUM_EXT("input bit format", tegra210_i2s_format_enum,
850                 tegra210_i2s_get_format, tegra210_i2s_put_format),
851         SOC_ENUM_EXT("codec bit format", tegra210_i2s_format_enum,
852                 tegra210_i2s_get_format, tegra210_i2s_put_format),
853         SOC_SINGLE_EXT("fsync width", SND_SOC_NOPM, 0, 255, 0,
854                 tegra210_i2s_fsync_width_get, tegra210_i2s_fsync_width_put),
855         SOC_SINGLE_EXT("Sample Rate", 0, 0, 192000, 0,
856                 tegra210_i2s_get_format, tegra210_i2s_put_format),
857         SOC_SINGLE_EXT("Channels", 0, 0, 16, 0,
858                 tegra210_i2s_get_format, tegra210_i2s_put_format),
859         SOC_SINGLE_EXT("BCLK Ratio", SND_SOC_NOPM, 0, INT_MAX, 0,
860                        tegra210_i2s_get_bclk_ratio,
861                        tegra210_i2s_put_bclk_ratio),
862         SOC_ENUM_EXT("Capture stereo to mono conv",
863                      tegra210_i2s_stereo_conv_enum, tegra210_i2s_get_format,
864                      tegra210_i2s_put_format),
865         SOC_ENUM_EXT("Capture mono to stereo conv",
866                      tegra210_i2s_mono_conv_enum, tegra210_i2s_get_format,
867                      tegra210_i2s_put_format),
868         SOC_ENUM_EXT("Playback stereo to mono conv",
869                      tegra210_i2s_stereo_conv_enum, tegra210_i2s_get_format,
870                      tegra210_i2s_put_format),
871         SOC_ENUM_EXT("Playback mono to stereo conv",
872                      tegra210_i2s_mono_conv_enum, tegra210_i2s_get_format,
873                      tegra210_i2s_put_format),
874         NV_SOC_SINGLE_RANGE_EXT("Playback FIFO threshold", 0,
875                                 TEGRA210_I2S_RX_FIFO_DEPTH - 1,
876                                 tegra210_i2s_get_format,
877                                 tegra210_i2s_put_format),
878 };
879
880 static const struct snd_soc_dapm_widget tegra210_i2s_widgets[] = {
881         SND_SOC_DAPM_AIF_IN("CIF RX", NULL, 0, SND_SOC_NOPM,
882                                 0, 0),
883         SND_SOC_DAPM_AIF_OUT("CIF TX", NULL, 0, SND_SOC_NOPM,
884                                 0, 0),
885         SND_SOC_DAPM_AIF_IN_E("DAP RX", NULL, 0, TEGRA210_I2S_AXBAR_TX_ENABLE,
886                                 TEGRA210_I2S_AXBAR_TX_EN_SHIFT, 0,
887                                 tegra210_i2s_rx_stop, SND_SOC_DAPM_PRE_PMU),
888         SND_SOC_DAPM_AIF_OUT_E("DAP TX", NULL, 0, TEGRA210_I2S_AXBAR_RX_ENABLE,
889                                 TEGRA210_I2S_AXBAR_RX_EN_SHIFT, 0,
890                                 tegra210_i2s_tx_stop, SND_SOC_DAPM_PRE_PMU),
891 };
892
893 static const struct snd_soc_dapm_route tegra210_i2s_routes[] = {
894         { "CIF RX",       NULL, "CIF Receive" },
895         { "DAP TX",       NULL, "CIF RX" },
896         { "DAP Transmit", NULL, "DAP TX" },
897
898         { "DAP RX",       NULL, "DAP Receive" },
899         { "CIF TX",       NULL, "DAP RX" },
900         { "CIF Transmit", NULL, "CIF TX" },
901 };
902
903 static struct snd_soc_codec_driver tegra210_i2s_codec = {
904         .idle_bias_off = 1,
905         .component_driver = {
906                 .dapm_widgets = tegra210_i2s_widgets,
907                 .num_dapm_widgets = ARRAY_SIZE(tegra210_i2s_widgets),
908                 .dapm_routes = tegra210_i2s_routes,
909                 .num_dapm_routes = ARRAY_SIZE(tegra210_i2s_routes),
910                 .controls = tegra210_i2s_controls,
911                 .num_controls = ARRAY_SIZE(tegra210_i2s_controls),
912         },
913 };
914
915 static bool tegra210_i2s_wr_reg(struct device *dev, unsigned int reg)
916 {
917         switch (reg) {
918         case TEGRA210_I2S_AXBAR_RX_ENABLE:
919         case TEGRA210_I2S_AXBAR_RX_SOFT_RESET:
920         case TEGRA210_I2S_AXBAR_RX_INT_MASK:
921         case TEGRA210_I2S_AXBAR_RX_INT_SET:
922         case TEGRA210_I2S_AXBAR_RX_INT_CLEAR:
923         case TEGRA210_I2S_AXBAR_RX_CIF_CTRL:
924         case TEGRA210_I2S_AXBAR_RX_CTRL:
925         case TEGRA210_I2S_AXBAR_RX_SLOT_CTRL:
926         case TEGRA210_I2S_AXBAR_RX_CLK_TRIM:
927         case TEGRA210_I2S_AXBAR_TX_ENABLE:
928         case TEGRA210_I2S_AXBAR_TX_SOFT_RESET:
929         case TEGRA210_I2S_AXBAR_TX_INT_MASK:
930         case TEGRA210_I2S_AXBAR_TX_INT_SET:
931         case TEGRA210_I2S_AXBAR_TX_INT_CLEAR:
932         case TEGRA210_I2S_AXBAR_TX_CIF_CTRL:
933         case TEGRA210_I2S_AXBAR_TX_CTRL:
934         case TEGRA210_I2S_AXBAR_TX_SLOT_CTRL:
935         case TEGRA210_I2S_AXBAR_TX_CLK_TRIM:
936         case TEGRA210_I2S_ENABLE:
937         case TEGRA210_I2S_SOFT_RESET:
938         case TEGRA210_I2S_CG:
939         case TEGRA210_I2S_CTRL:
940         case TEGRA210_I2S_TIMING:
941         case TEGRA210_I2S_SLOT_CTRL:
942         case TEGRA210_I2S_CLK_TRIM:
943         case TEGRA210_I2S_CYA:
944                 return true;
945         default:
946                 return false;
947         };
948 }
949
950 static bool tegra210_i2s_rd_reg(struct device *dev, unsigned int reg)
951 {
952         switch (reg) {
953         case TEGRA210_I2S_AXBAR_RX_STATUS:
954         case TEGRA210_I2S_AXBAR_RX_CIF_FIFO_STATUS:
955         case TEGRA210_I2S_AXBAR_RX_ENABLE:
956         case TEGRA210_I2S_AXBAR_RX_INT_MASK:
957         case TEGRA210_I2S_AXBAR_RX_INT_SET:
958         case TEGRA210_I2S_AXBAR_RX_INT_CLEAR:
959         case TEGRA210_I2S_AXBAR_RX_CIF_CTRL:
960         case TEGRA210_I2S_AXBAR_RX_CTRL:
961         case TEGRA210_I2S_AXBAR_RX_SLOT_CTRL:
962         case TEGRA210_I2S_AXBAR_RX_CLK_TRIM:
963         case TEGRA210_I2S_AXBAR_RX_INT_STATUS:
964         case TEGRA210_I2S_AXBAR_RX_SOFT_RESET:
965         case TEGRA210_I2S_AXBAR_TX_STATUS:
966         case TEGRA210_I2S_AXBAR_TX_CIF_FIFO_STATUS:
967         case TEGRA210_I2S_AXBAR_TX_ENABLE:
968         case TEGRA210_I2S_AXBAR_TX_INT_MASK:
969         case TEGRA210_I2S_AXBAR_TX_INT_SET:
970         case TEGRA210_I2S_AXBAR_TX_INT_CLEAR:
971         case TEGRA210_I2S_AXBAR_TX_CIF_CTRL:
972         case TEGRA210_I2S_AXBAR_TX_CTRL:
973         case TEGRA210_I2S_AXBAR_TX_SLOT_CTRL:
974         case TEGRA210_I2S_AXBAR_TX_CLK_TRIM:
975         case TEGRA210_I2S_AXBAR_TX_INT_STATUS:
976         case TEGRA210_I2S_AXBAR_TX_SOFT_RESET:
977         case TEGRA210_I2S_ENABLE:
978         case TEGRA210_I2S_STATUS:
979         case TEGRA210_I2S_SOFT_RESET:
980         case TEGRA210_I2S_CG:
981         case TEGRA210_I2S_CTRL:
982         case TEGRA210_I2S_TIMING:
983         case TEGRA210_I2S_SLOT_CTRL:
984         case TEGRA210_I2S_CLK_TRIM:
985         case TEGRA210_I2S_INT_STATUS:
986         case TEGRA210_I2S_CYA:
987                 return true;
988         default:
989                 return false;
990         };
991 }
992
993 static bool tegra210_i2s_volatile_reg(struct device *dev, unsigned int reg)
994 {
995         switch (reg) {
996         case TEGRA210_I2S_AXBAR_RX_INT_STATUS:
997         case TEGRA210_I2S_AXBAR_RX_STATUS:
998         case TEGRA210_I2S_AXBAR_TX_STATUS:
999         case TEGRA210_I2S_AXBAR_TX_INT_STATUS:
1000         case TEGRA210_I2S_INT_STATUS:
1001         case TEGRA210_I2S_AXBAR_RX_SOFT_RESET:
1002         case TEGRA210_I2S_AXBAR_TX_SOFT_RESET:
1003                 return true;
1004         default:
1005                 return false;
1006         };
1007 }
1008
1009 static const struct regmap_config tegra210_i2s_regmap_config = {
1010         .reg_bits = 32,
1011         .reg_stride = 4,
1012         .val_bits = 32,
1013         .max_register = TEGRA210_I2S_CYA,
1014         .writeable_reg = tegra210_i2s_wr_reg,
1015         .readable_reg = tegra210_i2s_rd_reg,
1016         .volatile_reg = tegra210_i2s_volatile_reg,
1017         .reg_defaults = tegra210_i2s_reg_defaults,
1018         .num_reg_defaults = ARRAY_SIZE(tegra210_i2s_reg_defaults),
1019         .cache_type = REGCACHE_FLAT,
1020 };
1021
1022 static const struct of_device_id tegra210_i2s_of_match[] = {
1023         { .compatible = "nvidia,tegra210-i2s" },
1024         {},
1025 };
1026
1027 static int tegra210_i2s_platform_probe(struct platform_device *pdev)
1028 {
1029         const struct of_device_id *match;
1030         struct device_node *np = pdev->dev.of_node;
1031         struct tegra210_i2s *i2s;
1032         struct resource *mem;
1033         struct property *prop;
1034         void __iomem *regs;
1035         int ret = 0, count = 0, num_supplies;
1036         const char *supply;
1037
1038         match = of_match_device(tegra210_i2s_of_match, &pdev->dev);
1039         if (!match) {
1040                 dev_err(&pdev->dev, "Error: No device match found\n");
1041                 return -ENODEV;
1042         }
1043
1044         i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
1045         if (!i2s)
1046                 return -ENOMEM;
1047
1048         i2s->tx_mask = i2s->rx_mask = 0xFFFF;
1049         i2s->enable_cya = false;
1050         i2s->loopback = 0;
1051         i2s->prod_name = NULL;
1052         /* default threshold settings */
1053         i2s->rx_fifo_th = 3;
1054         dev_set_drvdata(&pdev->dev, i2s);
1055
1056         if (!(tegra_platform_is_unit_fpga() || tegra_platform_is_fpga())) {
1057                 i2s->clk_i2s = devm_clk_get(&pdev->dev, "i2s");
1058                 if (IS_ERR(i2s->clk_i2s)) {
1059                         dev_err(&pdev->dev, "Can't retrieve i2s clock\n");
1060                         return PTR_ERR(i2s->clk_i2s);
1061                 }
1062                 i2s->clk_sync_input =
1063                         devm_clk_get(&pdev->dev, "clk_sync_input");
1064                 if (IS_ERR(i2s->clk_sync_input))
1065                         dev_dbg(&pdev->dev, "Can't get i2s sync input clock\n");
1066         }
1067
1068         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1069         regs = devm_ioremap_resource(&pdev->dev, mem);
1070         if (IS_ERR(regs))
1071                 return PTR_ERR(regs);
1072         i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
1073                                             &tegra210_i2s_regmap_config);
1074         if (IS_ERR(i2s->regmap)) {
1075                 dev_err(&pdev->dev, "regmap init failed\n");
1076                 return PTR_ERR(i2s->regmap);
1077         }
1078         regcache_cache_only(i2s->regmap, true);
1079
1080         ret = of_property_read_u32(np, "nvidia,ahub-i2s-id",
1081                                    &pdev->dev.id);
1082         if (ret < 0) {
1083                 dev_err(&pdev->dev, "Missing property nvidia,ahub-i2s-id\n");
1084                 return ret;
1085         }
1086
1087         if (of_property_read_u32(pdev->dev.of_node, "bclk-ratio",
1088                                  &i2s->bclk_ratio) < 0) {
1089                 dev_dbg(&pdev->dev, "Missing prop bclk-ratio for I2S%d\n",
1090                         pdev->dev.id);
1091                 i2s->bclk_ratio = 1;
1092         }
1093
1094         if (of_property_read_u32(pdev->dev.of_node,
1095                 "fsync-width", &i2s->fsync_width) < 0) {
1096                 dev_info(&pdev->dev, "Missing prop fsync-width for I2S%d\n",
1097                         pdev->dev.id);
1098                 i2s->fsync_width = 31;
1099         }
1100
1101         if (i2s->fsync_width > 255) {
1102                 dev_warn(&pdev->dev, "Default fsync-width to 31 for I2S%d\n",
1103                         pdev->dev.id);
1104                 i2s->fsync_width = 31;
1105         }
1106
1107         i2s->enable_cya = of_property_read_bool(pdev->dev.of_node,
1108                                                 "enable-cya");
1109
1110         if (!(tegra_platform_is_unit_fpga() || tegra_platform_is_fpga())) {
1111                 if (of_property_read_string(np, "prod-name",
1112                                             &i2s->prod_name) == 0)
1113                         tegra_pinctrl_config_prod(&pdev->dev, i2s->prod_name);
1114
1115                 num_supplies = of_property_count_strings(np,
1116                                                          "regulator-supplies");
1117                 if (num_supplies > 0) {
1118                         i2s->num_supplies = num_supplies;
1119                         i2s->supplies = devm_kzalloc(&pdev->dev, num_supplies *
1120                                                      sizeof(*i2s->supplies),
1121                                                      GFP_KERNEL);
1122                         if (!i2s->supplies)
1123                                 return -ENOMEM;
1124
1125                         of_property_for_each_string(np, "regulator-supplies",
1126                                                     prop, supply)
1127                                 i2s->supplies[count++].supply = supply;
1128
1129                         ret = devm_regulator_bulk_get(&pdev->dev,
1130                                                       i2s->num_supplies,
1131                                                       i2s->supplies);
1132                         if (ret) {
1133                                 dev_err(&pdev->dev,
1134                                         "Failed to get supplies: %d\n", ret);
1135                                 return ret;
1136                         }
1137                 }
1138         }
1139
1140         pm_runtime_enable(&pdev->dev);
1141         ret = snd_soc_register_codec(&pdev->dev, &tegra210_i2s_codec,
1142                                      tegra210_i2s_dais,
1143                                      ARRAY_SIZE(tegra210_i2s_dais));
1144         if (ret != 0) {
1145                 dev_err(&pdev->dev, "Could not register CODEC: %d\n", ret);
1146                 pm_runtime_disable(&pdev->dev);
1147                 return ret;
1148         }
1149
1150         return 0;
1151 }
1152
1153 static int tegra210_i2s_platform_remove(struct platform_device *pdev)
1154 {
1155         snd_soc_unregister_codec(&pdev->dev);
1156
1157         pm_runtime_disable(&pdev->dev);
1158         if (!pm_runtime_status_suspended(&pdev->dev))
1159                 tegra210_i2s_runtime_suspend(&pdev->dev);
1160
1161         return 0;
1162 }
1163
1164 static const struct dev_pm_ops tegra210_i2s_pm_ops = {
1165         SET_RUNTIME_PM_OPS(tegra210_i2s_runtime_suspend,
1166                            tegra210_i2s_runtime_resume, NULL)
1167         SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1168                                      pm_runtime_force_resume)
1169 };
1170
1171 static struct platform_driver tegra210_i2s_driver = {
1172         .driver = {
1173                 .name = DRV_NAME,
1174                 .owner = THIS_MODULE,
1175                 .of_match_table = tegra210_i2s_of_match,
1176                 .pm = &tegra210_i2s_pm_ops,
1177         },
1178         .probe = tegra210_i2s_platform_probe,
1179         .remove = tegra210_i2s_platform_remove,
1180 };
1181 module_platform_driver(tegra210_i2s_driver)
1182
1183 MODULE_AUTHOR("Songhee Baek <sbaek@nvidia.com>");
1184 MODULE_DESCRIPTION("Tegra210 I2S ASoC driver");
1185 MODULE_LICENSE("GPL");
1186 MODULE_ALIAS("platform:" DRV_NAME);
1187 MODULE_DEVICE_TABLE(of, tegra210_i2s_of_match);