[ARM] 3145/1: OMAP 3a/5: Add support for omap24xx
Tony Lindgren [Thu, 10 Nov 2005 14:26:51 +0000 (14:26 +0000)]
Patch from Tony Lindgren

This patch adds support for omap24xx series of processors.
The files live in arch/arm/mach-omap2, and share common
files with omap15xx and omap16xx processors in
arch/arm/plat-omap.

Omap24xx support was originally added for 2.6.9 by TI.
This code was then improved and integrated to share common
code with omap15xx and omap16xx processors by various
omap developers, such as Paul Mundt, Juha Yrjola, Imre Deak,
Tony Lindgren, Richard Woodruff, Nishant Menon, Komal Shah
et al.

Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

17 files changed:
arch/arm/Kconfig
arch/arm/Makefile
arch/arm/mach-omap2/Kconfig [new file with mode: 0644]
arch/arm/mach-omap2/Makefile [new file with mode: 0644]
arch/arm/mach-omap2/Makefile.boot [new file with mode: 0644]
arch/arm/mach-omap2/board-generic.c [new file with mode: 0644]
arch/arm/mach-omap2/board-h4.c [new file with mode: 0644]
arch/arm/mach-omap2/devices.c [new file with mode: 0644]
arch/arm/mach-omap2/id.c [new file with mode: 0644]
arch/arm/mach-omap2/io.c [new file with mode: 0644]
arch/arm/mach-omap2/irq.c [new file with mode: 0644]
arch/arm/mach-omap2/mux.c [new file with mode: 0644]
arch/arm/mach-omap2/prcm.h [new file with mode: 0644]
arch/arm/mach-omap2/serial.c [new file with mode: 0644]
arch/arm/mach-omap2/sram-fn.S [new file with mode: 0644]
arch/arm/mach-omap2/timer-gp.c [new file with mode: 0644]
arch/arm/mm/Kconfig

index ec77721..3df7cbd 100644 (file)
@@ -239,6 +239,8 @@ source "arch/arm/plat-omap/Kconfig"
 
 source "arch/arm/mach-omap1/Kconfig"
 
+source "arch/arm/mach-omap2/Kconfig"
+
 source "arch/arm/mach-s3c2410/Kconfig"
 
 source "arch/arm/mach-lh7a40x/Kconfig"
index 114cda7..81bd219 100644 (file)
@@ -93,6 +93,7 @@ textaddr-$(CONFIG_ARCH_FORTUNET)   := 0xc0008000
  machine-$(CONFIG_ARCH_IXP4XX)    := ixp4xx
  machine-$(CONFIG_ARCH_IXP2000)    := ixp2000
  machine-$(CONFIG_ARCH_OMAP1)     := omap1
+ machine-$(CONFIG_ARCH_OMAP2)     := omap2
   incdir-$(CONFIG_ARCH_OMAP)      := omap
  machine-$(CONFIG_ARCH_S3C2410)           := s3c2410
  machine-$(CONFIG_ARCH_LH7A40X)           := lh7a40x
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
new file mode 100644 (file)
index 0000000..5788809
--- /dev/null
@@ -0,0 +1,22 @@
+comment "OMAP Core Type"
+       depends on ARCH_OMAP2
+
+config ARCH_OMAP24XX
+       bool "OMAP24xx Based System"
+       depends on ARCH_OMAP2
+
+config ARCH_OMAP2420
+       bool "OMAP2420 support"
+       depends on ARCH_OMAP24XX
+
+comment "OMAP Board Type"
+       depends on ARCH_OMAP2
+
+config MACH_OMAP_GENERIC
+       bool "Generic OMAP board"
+       depends on ARCH_OMAP2 && ARCH_OMAP24XX
+
+config MACH_OMAP_H4
+       bool "OMAP 2420 H4 board"
+       depends on ARCH_OMAP2 && ARCH_OMAP24XX
+
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
new file mode 100644 (file)
index 0000000..4204116
--- /dev/null
@@ -0,0 +1,13 @@
+#
+# Makefile for the linux kernel.
+#
+
+# Common support
+obj-y := irq.o id.o io.o sram-fn.o clock.o mux.o devices.o serial.o
+
+obj-$(CONFIG_OMAP_MPU_TIMER)           += timer-gp.o
+
+# Specific board support
+obj-$(CONFIG_MACH_OMAP_GENERIC)                += board-generic.o
+obj-$(CONFIG_MACH_OMAP_H4)             += board-h4.o
+
diff --git a/arch/arm/mach-omap2/Makefile.boot b/arch/arm/mach-omap2/Makefile.boot
new file mode 100644 (file)
index 0000000..565aff7
--- /dev/null
@@ -0,0 +1,3 @@
+  zreladdr-y           := 0x80008000
+params_phys-y          := 0x80000100
+initrd_phys-y          := 0x80800000
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
new file mode 100644 (file)
index 0000000..c602e7a
--- /dev/null
@@ -0,0 +1,80 @@
+/*
+ * linux/arch/arm/mach-omap/omap2/board-generic.c
+ *
+ * Copyright (C) 2005 Nokia Corporation
+ * Author: Paul Mundt <paul.mundt@nokia.com>
+ *
+ * Modified from mach-omap/omap1/board-generic.c
+ *
+ * Code for generic OMAP2 board. Should work on many OMAP2 systems where
+ * the bootloader passes the board-specific data to the kernel.
+ * Do not put any board specific code to this file; create a new machine
+ * type if you need custom low-level initializations.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/device.h>
+
+#include <asm/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include <asm/arch/gpio.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/usb.h>
+#include <asm/arch/board.h>
+#include <asm/arch/common.h>
+
+static void __init omap_generic_init_irq(void)
+{
+       omap_init_irq();
+}
+
+static struct omap_uart_config generic_uart_config __initdata = {
+       .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)),
+};
+
+static struct omap_mmc_config generic_mmc_config __initdata = {
+       .mmc [0] = {
+               .enabled        = 0,
+               .wire4          = 0,
+               .wp_pin         = -1,
+               .power_pin      = -1,
+               .switch_pin     = -1,
+       },
+};
+
+static struct omap_board_config_kernel generic_config[] = {
+       { OMAP_TAG_UART,        &generic_uart_config },
+       { OMAP_TAG_MMC,         &generic_mmc_config },
+};
+
+static void __init omap_generic_init(void)
+{
+       omap_board_config = generic_config;
+       omap_board_config_size = ARRAY_SIZE(generic_config);
+       omap_serial_init();
+}
+
+static void __init omap_generic_map_io(void)
+{
+       omap_map_common_io();
+}
+
+MACHINE_START(OMAP_GENERIC, "Generic OMAP24xx")
+       /* Maintainer: Paul Mundt <paul.mundt@nokia.com> */
+       .phys_ram       = 0x80000000,
+       .phys_io        = 0x48000000,
+       .io_pg_offst    = ((0xd8000000) >> 18) & 0xfffc,
+       .boot_params    = 0x80000100,
+       .map_io         = omap_generic_map_io,
+       .init_irq       = omap_generic_init_irq,
+       .init_machine   = omap_generic_init,
+       .timer          = &omap_timer,
+MACHINE_END
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
new file mode 100644 (file)
index 0000000..f255446
--- /dev/null
@@ -0,0 +1,197 @@
+/*
+ * linux/arch/arm/mach-omap/omap2/board-h4.c
+ *
+ * Copyright (C) 2005 Nokia Corporation
+ * Author: Paul Mundt <paul.mundt@nokia.com>
+ *
+ * Modified from mach-omap/omap1/board-generic.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/delay.h>
+
+#include <asm/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/flash.h>
+
+#include <asm/arch/gpio.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/usb.h>
+#include <asm/arch/board.h>
+#include <asm/arch/common.h>
+#include <asm/arch/prcm.h>
+
+#include <asm/io.h>
+#include <asm/delay.h>
+
+static struct mtd_partition h4_partitions[] = {
+       /* bootloader (U-Boot, etc) in first sector */
+       {
+             .name             = "bootloader",
+             .offset           = 0,
+             .size             = SZ_128K,
+             .mask_flags       = MTD_WRITEABLE, /* force read-only */
+       },
+       /* bootloader params in the next sector */
+       {
+             .name             = "params",
+             .offset           = MTDPART_OFS_APPEND,
+             .size             = SZ_128K,
+             .mask_flags       = 0,
+       },
+       /* kernel */
+       {
+             .name             = "kernel",
+             .offset           = MTDPART_OFS_APPEND,
+             .size             = SZ_2M,
+             .mask_flags       = 0
+       },
+       /* file system */
+       {
+             .name             = "filesystem",
+             .offset           = MTDPART_OFS_APPEND,
+             .size             = MTDPART_SIZ_FULL,
+             .mask_flags       = 0
+       }
+};
+
+static struct flash_platform_data h4_flash_data = {
+       .map_name       = "cfi_probe",
+       .width          = 2,
+       .parts          = h4_partitions,
+       .nr_parts       = ARRAY_SIZE(h4_partitions),
+};
+
+static struct resource h4_flash_resource = {
+       .start          = H4_CS0_BASE,
+       .end            = H4_CS0_BASE + SZ_64M - 1,
+       .flags          = IORESOURCE_MEM,
+};
+
+static struct platform_device h4_flash_device = {
+       .name           = "omapflash",
+       .id             = 0,
+       .dev            = {
+               .platform_data  = &h4_flash_data,
+       },
+       .num_resources  = 1,
+       .resource       = &h4_flash_resource,
+};
+
+static struct resource h4_smc91x_resources[] = {
+       [0] = {
+               .start  = OMAP24XX_ETHR_START,          /* Physical */
+               .end    = OMAP24XX_ETHR_START + 0xf,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = OMAP_GPIO_IRQ(OMAP24XX_ETHR_GPIO_IRQ),
+               .end    = OMAP_GPIO_IRQ(OMAP24XX_ETHR_GPIO_IRQ),
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device h4_smc91x_device = {
+       .name           = "smc91x",
+       .id             = -1,
+       .num_resources  = ARRAY_SIZE(h4_smc91x_resources),
+       .resource       = h4_smc91x_resources,
+};
+
+static struct platform_device *h4_devices[] __initdata = {
+       &h4_smc91x_device,
+       &h4_flash_device,
+};
+
+static inline void __init h4_init_smc91x(void)
+{
+       /* Make sure CS1 timings are correct */
+       GPMC_CONFIG1_1 = 0x00011200;
+       GPMC_CONFIG2_1 = 0x001f1f01;
+       GPMC_CONFIG3_1 = 0x00080803;
+       GPMC_CONFIG4_1 = 0x1c091c09;
+       GPMC_CONFIG5_1 = 0x041f1f1f;
+       GPMC_CONFIG6_1 = 0x000004c4;
+       GPMC_CONFIG7_1 = 0x00000f40 | (0x08000000 >> 24);
+       udelay(100);
+
+       omap_cfg_reg(M15_24XX_GPIO92);
+       if (omap_request_gpio(OMAP24XX_ETHR_GPIO_IRQ) < 0) {
+               printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n",
+                       OMAP24XX_ETHR_GPIO_IRQ);
+               return;
+       }
+       omap_set_gpio_direction(OMAP24XX_ETHR_GPIO_IRQ, 1);
+}
+
+static void __init omap_h4_init_irq(void)
+{
+       omap_init_irq();
+       omap_gpio_init();
+       h4_init_smc91x();
+}
+
+static struct omap_uart_config h4_uart_config __initdata = {
+       .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)),
+};
+
+static struct omap_mmc_config h4_mmc_config __initdata = {
+       .mmc [0] = {
+               .enabled        = 1,
+               .wire4          = 1,
+               .wp_pin         = -1,
+               .power_pin      = -1,
+               .switch_pin     = -1,
+       },
+};
+
+static struct omap_lcd_config h4_lcd_config __initdata = {
+       .panel_name     = "h4",
+       .ctrl_name      = "internal",
+};
+
+static struct omap_board_config_kernel h4_config[] = {
+       { OMAP_TAG_UART,        &h4_uart_config },
+       { OMAP_TAG_MMC,         &h4_mmc_config },
+       { OMAP_TAG_LCD,         &h4_lcd_config },
+};
+
+static void __init omap_h4_init(void)
+{
+       /*
+        * Make sure the serial ports are muxed on at this point.
+        * You have to mux them off in device drivers later on
+        * if not needed.
+        */
+       platform_add_devices(h4_devices, ARRAY_SIZE(h4_devices));
+       omap_board_config = h4_config;
+       omap_board_config_size = ARRAY_SIZE(h4_config);
+       omap_serial_init();
+}
+
+static void __init omap_h4_map_io(void)
+{
+       omap_map_common_io();
+}
+
+MACHINE_START(OMAP_H4, "OMAP2420 H4 board")
+       /* Maintainer: Paul Mundt <paul.mundt@nokia.com> */
+       .phys_ram       = 0x80000000,
+       .phys_io        = 0x48000000,
+       .io_pg_offst    = ((0xd8000000) >> 18) & 0xfffc,
+       .boot_params    = 0x80000100,
+       .map_io         = omap_h4_map_io,
+       .init_irq       = omap_h4_init_irq,
+       .init_machine   = omap_h4_init,
+       .timer          = &omap_timer,
+MACHINE_END
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
new file mode 100644 (file)
index 0000000..7181edb
--- /dev/null
@@ -0,0 +1,89 @@
+/*
+ * linux/arch/arm/mach-omap2/devices.c
+ *
+ * OMAP2 platform device setup/initialization
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include <asm/mach-types.h>
+#include <asm/mach/map.h>
+
+#include <asm/arch/tc.h>
+#include <asm/arch/board.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/gpio.h>
+
+extern void omap_nop_release(struct device *dev);
+
+/*-------------------------------------------------------------------------*/
+
+#if    defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE)
+
+#define OMAP2_I2C_BASE2                0x48072000
+#define OMAP2_I2C_INT2         57
+
+static struct resource i2c_resources2[] = {
+       {
+               .start          = OMAP2_I2C_BASE2,
+               .end            = OMAP2_I2C_BASE2 + 0x3f,
+               .flags          = IORESOURCE_MEM,
+       },
+       {
+               .start          = OMAP2_I2C_INT2,
+               .flags          = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device omap_i2c_device2 = {
+        .name           = "i2c_omap",
+        .id             = 2,
+        .dev = {
+                .release        = omap_nop_release,
+        },
+       .num_resources  = ARRAY_SIZE(i2c_resources2),
+       .resource       = i2c_resources2,
+};
+
+/* See also arch/arm/plat-omap/devices.c for first I2C on 24xx */
+static void omap_init_i2c(void)
+{
+       /* REVISIT: Second I2C not in use on H4? */
+       if (machine_is_omap_h4())
+               return;
+
+       omap_cfg_reg(J15_24XX_I2C2_SCL);
+       omap_cfg_reg(H19_24XX_I2C2_SDA);
+       (void) platform_device_register(&omap_i2c_device2);
+}
+
+#else
+
+static void omap_init_i2c(void) {}
+
+#endif
+
+/*-------------------------------------------------------------------------*/
+
+static int __init omap2_init_devices(void)
+{
+       /* please keep these calls, and their implementations above,
+        * in alphabetical order so they're easier to sort through.
+        */
+       omap_init_i2c();
+
+       return 0;
+}
+arch_initcall(omap2_init_devices);
+
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
new file mode 100644 (file)
index 0000000..7618730
--- /dev/null
@@ -0,0 +1,124 @@
+/*
+ * linux/arch/arm/mach-omap2/id.c
+ *
+ * OMAP2 CPU identification code
+ *
+ * Copyright (C) 2005 Nokia Corporation
+ * Written by Tony Lindgren <tony@atomide.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include <asm/io.h>
+
+#define OMAP24XX_TAP_BASE      io_p2v(0x48014000)
+
+#define OMAP_TAP_IDCODE                0x0204
+#define OMAP_TAP_PROD_ID       0x0208
+
+#define OMAP_TAP_DIE_ID_0      0x0218
+#define OMAP_TAP_DIE_ID_1      0x021C
+#define OMAP_TAP_DIE_ID_2      0x0220
+#define OMAP_TAP_DIE_ID_3      0x0224
+
+/* system_rev fields for OMAP2 processors:
+ *   CPU id bits     [31:16],
+ *   CPU device type [15:12], (unprg,normal,POP)
+ *   CPU revision    [11:08]
+ *   CPU class bits  [07:00]
+ */
+
+struct omap_id {
+       u16     hawkeye;        /* Silicon type (Hawkeye id) */
+       u8      dev;            /* Device type from production_id reg */
+       u32     type;           /* combined type id copied to system_rev */
+};
+
+/* Register values to detect the OMAP version */
+static struct omap_id omap_ids[] __initdata = {
+       { .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200000 },
+       { .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201000 },
+       { .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202000 },
+       { .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220000 },
+       { .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230000 },
+       { .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300000 },
+};
+
+static u32 __init read_tap_reg(int reg)
+{
+       return __raw_readl(OMAP24XX_TAP_BASE + reg);
+}
+
+void __init omap2_check_revision(void)
+{
+       int i, j;
+       u32 idcode;
+       u32 prod_id;
+       u16 hawkeye;
+       u8  dev_type;
+       u8  rev;
+
+       idcode = read_tap_reg(OMAP_TAP_IDCODE);
+       prod_id = read_tap_reg(OMAP_TAP_PROD_ID);
+       hawkeye = (idcode >> 12) & 0xffff;
+       rev = (idcode >> 28) & 0x0f;
+       dev_type = (prod_id >> 16) & 0x0f;
+
+#ifdef DEBUG
+       printk(KERN_DEBUG "OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n",
+               idcode, rev, hawkeye, (idcode >> 1) & 0x7ff);
+       printk(KERN_DEBUG "OMAP_TAP_DIE_ID_0: 0x%08x\n",
+               read_tap_reg(OMAP_TAP_DIE_ID_0));
+       printk(KERN_DEBUG "OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n",
+               read_tap_reg(OMAP_TAP_DIE_ID_1),
+              (read_tap_reg(OMAP_TAP_DIE_ID_1) >> 28) & 0xf);
+       printk(KERN_DEBUG "OMAP_TAP_DIE_ID_2: 0x%08x\n",
+               read_tap_reg(OMAP_TAP_DIE_ID_2));
+       printk(KERN_DEBUG "OMAP_TAP_DIE_ID_3: 0x%08x\n",
+               read_tap_reg(OMAP_TAP_DIE_ID_3));
+       printk(KERN_DEBUG "OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n",
+               prod_id, dev_type);
+#endif
+
+       /* Check hawkeye ids */
+       for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
+               if (hawkeye == omap_ids[i].hawkeye)
+                       break;
+       }
+
+       if (i == ARRAY_SIZE(omap_ids)) {
+               printk(KERN_ERR "Unknown OMAP CPU id\n");
+               return;
+       }
+
+       for (j = i; j < ARRAY_SIZE(omap_ids); j++) {
+               if (dev_type == omap_ids[j].dev)
+                       break;
+       }
+
+       if (j == ARRAY_SIZE(omap_ids)) {
+               printk(KERN_ERR "Unknown OMAP device type. "
+                               "Handling it as OMAP%04x\n",
+                               omap_ids[i].type >> 16);
+               j = i;
+       }
+       system_rev = omap_ids[j].type;
+
+       system_rev |= rev << 8;
+
+       /* Add the cpu class info (24xx) */
+       system_rev |= 0x24;
+
+       pr_info("OMAP%04x", system_rev >> 16);
+       if ((system_rev >> 8) & 0x0f)
+               printk("%x", (system_rev >> 8) & 0x0f);
+       printk("\n");
+}
+
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
new file mode 100644 (file)
index 0000000..8ea67bf
--- /dev/null
@@ -0,0 +1,53 @@
+/*
+ * linux/arch/arm/mach-omap2/io.c
+ *
+ * OMAP2 I/O mapping code
+ *
+ * Copyright (C) 2005 Nokia Corporation
+ * Author: Juha Yrjölä <juha.yrjola@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include <asm/mach/map.h>
+#include <asm/io.h>
+#include <asm/arch/mux.h>
+
+extern void omap_sram_init(void);
+extern int omap2_clk_init(void);
+extern void omap2_check_revision(void);
+
+/*
+ * The machine specific code may provide the extra mapping besides the
+ * default mapping provided here.
+ */
+static struct map_desc omap2_io_desc[] __initdata = {
+       {
+               .virtual        = L3_24XX_VIRT,
+               .pfn            = __phys_to_pfn(L3_24XX_PHYS),
+               .length         = L3_24XX_SIZE,
+               .type           = MT_DEVICE
+       },
+       {
+               .virtual        = L4_24XX_VIRT,
+               .pfn            = __phys_to_pfn(L4_24XX_PHYS),
+               .length         = L4_24XX_SIZE,
+               .type           = MT_DEVICE
+       }
+};
+
+void __init omap_map_common_io(void)
+{
+       iotable_init(omap2_io_desc, ARRAY_SIZE(omap2_io_desc));
+       omap2_check_revision();
+       omap_sram_init();
+       omap2_mux_init();
+       omap2_clk_init();
+}
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
new file mode 100644 (file)
index 0000000..d7baff6
--- /dev/null
@@ -0,0 +1,149 @@
+/*
+ * linux/arch/arm/mach-omap/omap2/irq.c
+ *
+ * Interrupt handler for OMAP2 boards.
+ *
+ * Copyright (C) 2005 Nokia Corporation
+ * Author: Paul Mundt <paul.mundt@nokia.com>
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/config.h>
+#include <linux/interrupt.h>
+#include <asm/hardware.h>
+#include <asm/mach/irq.h>
+#include <asm/irq.h>
+#include <asm/io.h>
+
+#define INTC_REVISION  0x0000
+#define INTC_SYSCONFIG 0x0010
+#define INTC_SYSSTATUS 0x0014
+#define INTC_CONTROL   0x0048
+#define INTC_MIR_CLEAR0        0x0088
+#define INTC_MIR_SET0  0x008c
+
+/*
+ * OMAP2 has a number of different interrupt controllers, each interrupt
+ * controller is identified as its own "bank". Register definitions are
+ * fairly consistent for each bank, but not all registers are implemented
+ * for each bank.. when in doubt, consult the TRM.
+ */
+static struct omap_irq_bank {
+       unsigned long base_reg;
+       unsigned int nr_irqs;
+} __attribute__ ((aligned(4))) irq_banks[] = {
+       {
+               /* MPU INTC */
+               .base_reg       = OMAP24XX_IC_BASE,
+               .nr_irqs        = 96,
+       }, {
+               /* XXX: DSP INTC */
+
+#if 0
+       /*
+        * Commented out for now until we fix the IVA clocking
+        */
+#ifdef CONFIG_ARCH_OMAP2420
+       }, {
+               /* IVA INTC (2420 only) */
+               .base_reg       = OMAP24XX_IVA_INTC_BASE,
+               .nr_irqs        = 16,   /* Actually 32, but only 16 are used */
+#endif
+#endif
+       }
+};
+
+/* XXX: FIQ and additional INTC support (only MPU at the moment) */
+static void omap_ack_irq(unsigned int irq)
+{
+       omap_writel(0x1, irq_banks[0].base_reg + INTC_CONTROL);
+}
+
+static void omap_mask_irq(unsigned int irq)
+{
+       int offset = (irq >> 5) << 5;
+
+       if (irq >= 64) {
+               irq %= 64;
+       } else if (irq >= 32) {
+               irq %= 32;
+       }
+
+       omap_writel(1 << irq, irq_banks[0].base_reg + INTC_MIR_SET0 + offset);
+}
+
+static void omap_unmask_irq(unsigned int irq)
+{
+       int offset = (irq >> 5) << 5;
+
+       if (irq >= 64) {
+               irq %= 64;
+       } else if (irq >= 32) {
+               irq %= 32;
+       }
+
+       omap_writel(1 << irq, irq_banks[0].base_reg + INTC_MIR_CLEAR0 + offset);
+}
+
+static void omap_mask_ack_irq(unsigned int irq)
+{
+       omap_mask_irq(irq);
+       omap_ack_irq(irq);
+}
+
+static struct irqchip omap_irq_chip = {
+       .ack    = omap_mask_ack_irq,
+       .mask   = omap_mask_irq,
+       .unmask = omap_unmask_irq,
+};
+
+static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank)
+{
+       unsigned long tmp;
+
+       tmp = omap_readl(bank->base_reg + INTC_REVISION) & 0xff;
+       printk(KERN_INFO "IRQ: Found an INTC at 0x%08lx "
+                        "(revision %ld.%ld) with %d interrupts\n",
+                        bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs);
+
+       tmp = omap_readl(bank->base_reg + INTC_SYSCONFIG);
+       tmp |= 1 << 1;  /* soft reset */
+       omap_writel(tmp, bank->base_reg + INTC_SYSCONFIG);
+
+       while (!(omap_readl(bank->base_reg + INTC_SYSSTATUS) & 0x1))
+               /* Wait for reset to complete */;
+}
+
+void __init omap_init_irq(void)
+{
+       unsigned long nr_irqs = 0;
+       unsigned int nr_banks = 0;
+       int i;
+
+       for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
+               struct omap_irq_bank *bank = irq_banks + i;
+
+               /* XXX */
+               if (!bank->base_reg)
+                       continue;
+
+               omap_irq_bank_init_one(bank);
+
+               nr_irqs += bank->nr_irqs;
+               nr_banks++;
+       }
+
+       printk(KERN_INFO "Total of %ld interrupts on %d active controller%s\n",
+              nr_irqs, nr_banks, nr_banks > 1 ? "s" : "");
+
+       for (i = 0; i < nr_irqs; i++) {
+               set_irq_chip(i, &omap_irq_chip);
+               set_irq_handler(i, do_level_IRQ);
+               set_irq_flags(i, IRQF_VALID);
+       }
+}
+
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
new file mode 100644 (file)
index 0000000..ea46548
--- /dev/null
@@ -0,0 +1,65 @@
+/*
+ * linux/arch/arm/mach-omap2/mux.c
+ *
+ * OMAP1 pin multiplexing configurations
+ *
+ * Copyright (C) 2003 - 2005 Nokia Corporation
+ *
+ * Written by Tony Lindgren <tony.lindgren@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <asm/system.h>
+#include <asm/io.h>
+#include <linux/spinlock.h>
+
+#include <asm/arch/mux.h>
+
+#ifdef CONFIG_OMAP_MUX
+
+/* NOTE: See mux.h for the enumeration */
+
+struct pin_config __initdata_or_module omap24xx_pins[] = {
+/*
+ *     description                     mux     mux     pull    pull    debug
+ *                                     offset  mode    ena     type
+ */
+
+/* 24xx I2C */
+MUX_CFG_24XX("M19_24XX_I2C1_SCL",      0x111,  0,      0,      0,      1)
+MUX_CFG_24XX("L15_24XX_I2C1_SDA",      0x112,  0,      0,      0,      1)
+MUX_CFG_24XX("J15_24XX_I2C2_SCL",      0x113,  0,      0,      0,      1)
+MUX_CFG_24XX("H19_24XX_I2C2_SDA",      0x114,  0,      0,      0,      1)
+
+/* Menelaus interrupt */
+MUX_CFG_24XX("W19_24XX_SYS_NIRQ",      0x12c,  0,      1,      1,      1)
+
+/* 24xx GPIO */
+MUX_CFG_24XX("Y20_24XX_GPIO60",                0x12c,  3,      0,      0,      1)
+MUX_CFG_24XX("M15_24XX_GPIO92",                0x10a,  3,      0,      0,      1)
+
+};
+
+int __init omap2_mux_init(void)
+{
+       omap_mux_register(omap24xx_pins, ARRAY_SIZE(omap24xx_pins));
+       return 0;
+}
+
+#endif
diff --git a/arch/arm/mach-omap2/prcm.h b/arch/arm/mach-omap2/prcm.h
new file mode 100644 (file)
index 0000000..2eb89b9
--- /dev/null
@@ -0,0 +1,419 @@
+/*
+ * prcm.h - Access definations for use in OMAP24XX clock and power management
+ *
+ * Copyright (C) 2005 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARM_ARCH_DPM_PRCM_H
+#define __ASM_ARM_ARCH_DPM_PRCM_H
+
+/* SET_PERFORMANCE_LEVEL PARAMETERS */
+#define PRCM_HALF_SPEED 1
+#define PRCM_FULL_SPEED 2
+
+#ifndef __ASSEMBLER__
+
+#define PRCM_REG32(offset)     __REG32(OMAP24XX_PRCM_BASE + (offset))
+
+#define PRCM_REVISION          PRCM_REG32(0x000)
+#define PRCM_SYSCONFIG         PRCM_REG32(0x010)
+#define PRCM_IRQSTATUS_MPU     PRCM_REG32(0x018)
+#define PRCM_IRQENABLE_MPU     PRCM_REG32(0x01C)
+#define PRCM_VOLTCTRL          PRCM_REG32(0x050)
+#define PRCM_VOLTST            PRCM_REG32(0x054)
+#define PRCM_CLKSRC_CTRL       PRCM_REG32(0x060)
+#define PRCM_CLKOUT_CTRL       PRCM_REG32(0x070)
+#define PRCM_CLKEMUL_CTRL      PRCM_REG32(0x078)
+#define PRCM_CLKCFG_CTRL       PRCM_REG32(0x080)
+#define PRCM_CLKCFG_STATUS     PRCM_REG32(0x084)
+#define PRCM_VOLTSETUP         PRCM_REG32(0x090)
+#define PRCM_CLKSSETUP         PRCM_REG32(0x094)
+#define PRCM_POLCTRL           PRCM_REG32(0x098)
+
+/* GENERAL PURPOSE */
+#define GENERAL_PURPOSE1       PRCM_REG32(0x0B0)
+#define GENERAL_PURPOSE2       PRCM_REG32(0x0B4)
+#define GENERAL_PURPOSE3       PRCM_REG32(0x0B8)
+#define GENERAL_PURPOSE4       PRCM_REG32(0x0BC)
+#define GENERAL_PURPOSE5       PRCM_REG32(0x0C0)
+#define GENERAL_PURPOSE6       PRCM_REG32(0x0C4)
+#define GENERAL_PURPOSE7       PRCM_REG32(0x0C8)
+#define GENERAL_PURPOSE8       PRCM_REG32(0x0CC)
+#define GENERAL_PURPOSE9       PRCM_REG32(0x0D0)
+#define GENERAL_PURPOSE10      PRCM_REG32(0x0D4)
+#define GENERAL_PURPOSE11      PRCM_REG32(0x0D8)
+#define GENERAL_PURPOSE12      PRCM_REG32(0x0DC)
+#define GENERAL_PURPOSE13      PRCM_REG32(0x0E0)
+#define GENERAL_PURPOSE14      PRCM_REG32(0x0E4)
+#define GENERAL_PURPOSE15      PRCM_REG32(0x0E8)
+#define GENERAL_PURPOSE16      PRCM_REG32(0x0EC)
+#define GENERAL_PURPOSE17      PRCM_REG32(0x0F0)
+#define GENERAL_PURPOSE18      PRCM_REG32(0x0F4)
+#define GENERAL_PURPOSE19      PRCM_REG32(0x0F8)
+#define GENERAL_PURPOSE20      PRCM_REG32(0x0FC)
+
+/* MPU */
+#define CM_CLKSEL_MPU          PRCM_REG32(0x140)
+#define CM_CLKSTCTRL_MPU       PRCM_REG32(0x148)
+#define RM_RSTST_MPU           PRCM_REG32(0x158)
+#define PM_WKDEP_MPU           PRCM_REG32(0x1C8)
+#define PM_EVGENCTRL_MPU       PRCM_REG32(0x1D4)
+#define PM_EVEGENONTIM_MPU     PRCM_REG32(0x1D8)
+#define PM_EVEGENOFFTIM_MPU    PRCM_REG32(0x1DC)
+#define PM_PWSTCTRL_MPU                PRCM_REG32(0x1E0)
+#define PM_PWSTST_MPU          PRCM_REG32(0x1E4)
+
+/* CORE */
+#define CM_FCLKEN1_CORE                PRCM_REG32(0x200)
+#define CM_FCLKEN2_CORE                PRCM_REG32(0x204)
+#define CM_FCLKEN3_CORE                PRCM_REG32(0x208)
+#define CM_ICLKEN1_CORE                PRCM_REG32(0x210)
+#define CM_ICLKEN2_CORE                PRCM_REG32(0x214)
+#define CM_ICLKEN3_CORE                PRCM_REG32(0x218)
+#define CM_ICLKEN4_CORE                PRCM_REG32(0x21C)
+#define CM_IDLEST1_CORE                PRCM_REG32(0x220)
+#define CM_IDLEST2_CORE                PRCM_REG32(0x224)
+#define CM_IDLEST3_CORE                PRCM_REG32(0x228)
+#define CM_IDLEST4_CORE                PRCM_REG32(0x22C)
+#define CM_AUTOIDLE1_CORE      PRCM_REG32(0x230)
+#define CM_AUTOIDLE2_CORE      PRCM_REG32(0x234)
+#define CM_AUTOIDLE3_CORE      PRCM_REG32(0x238)
+#define CM_AUTOIDLE4_CORE      PRCM_REG32(0x23C)
+#define CM_CLKSEL1_CORE                PRCM_REG32(0x240)
+#define CM_CLKSEL2_CORE                PRCM_REG32(0x244)
+#define CM_CLKSTCTRL_CORE      PRCM_REG32(0x248)
+#define PM_WKEN1_CORE          PRCM_REG32(0x2A0)
+#define PM_WKEN2_CORE          PRCM_REG32(0x2A4)
+#define PM_WKST1_CORE          PRCM_REG32(0x2B0)
+#define PM_WKST2_CORE          PRCM_REG32(0x2B4)
+#define PM_WKDEP_CORE          PRCM_REG32(0x2C8)
+#define PM_PWSTCTRL_CORE       PRCM_REG32(0x2E0)
+#define PM_PWSTST_CORE         PRCM_REG32(0x2E4)
+
+/* GFX */
+#define CM_FCLKEN_GFX          PRCM_REG32(0x300)
+#define CM_ICLKEN_GFX          PRCM_REG32(0x310)
+#define CM_IDLEST_GFX          PRCM_REG32(0x320)
+#define CM_CLKSEL_GFX          PRCM_REG32(0x340)
+#define CM_CLKSTCTRL_GFX       PRCM_REG32(0x348)
+#define RM_RSTCTRL_GFX         PRCM_REG32(0x350)
+#define RM_RSTST_GFX           PRCM_REG32(0x358)
+#define PM_WKDEP_GFX           PRCM_REG32(0x3C8)
+#define PM_PWSTCTRL_GFX                PRCM_REG32(0x3E0)
+#define PM_PWSTST_GFX          PRCM_REG32(0x3E4)
+
+/* WAKE-UP */
+#define CM_FCLKEN_WKUP         PRCM_REG32(0x400)
+#define CM_ICLKEN_WKUP         PRCM_REG32(0x410)
+#define CM_IDLEST_WKUP         PRCM_REG32(0x420)
+#define CM_AUTOIDLE_WKUP       PRCM_REG32(0x430)
+#define CM_CLKSEL_WKUP         PRCM_REG32(0x440)
+#define RM_RSTCTRL_WKUP                PRCM_REG32(0x450)
+#define RM_RSTTIME_WKUP                PRCM_REG32(0x454)
+#define RM_RSTST_WKUP          PRCM_REG32(0x458)
+#define PM_WKEN_WKUP           PRCM_REG32(0x4A0)
+#define PM_WKST_WKUP           PRCM_REG32(0x4B0)
+
+/* CLOCKS */
+#define CM_CLKEN_PLL           PRCM_REG32(0x500)
+#define CM_IDLEST_CKGEN                PRCM_REG32(0x520)
+#define CM_AUTOIDLE_PLL                PRCM_REG32(0x530)
+#define CM_CLKSEL1_PLL         PRCM_REG32(0x540)
+#define CM_CLKSEL2_PLL         PRCM_REG32(0x544)
+
+/* DSP */
+#define CM_FCLKEN_DSP          PRCM_REG32(0x800)
+#define CM_ICLKEN_DSP          PRCM_REG32(0x810)
+#define CM_IDLEST_DSP          PRCM_REG32(0x820)
+#define CM_AUTOIDLE_DSP                PRCM_REG32(0x830)
+#define CM_CLKSEL_DSP          PRCM_REG32(0x840)
+#define CM_CLKSTCTRL_DSP       PRCM_REG32(0x848)
+#define RM_RSTCTRL_DSP         PRCM_REG32(0x850)
+#define RM_RSTST_DSP           PRCM_REG32(0x858)
+#define PM_WKEN_DSP            PRCM_REG32(0x8A0)
+#define PM_WKDEP_DSP           PRCM_REG32(0x8C8)
+#define PM_PWSTCTRL_DSP                PRCM_REG32(0x8E0)
+#define PM_PWSTST_DSP          PRCM_REG32(0x8E4)
+#define PRCM_IRQSTATUS_DSP     PRCM_REG32(0x8F0)
+#define PRCM_IRQENABLE_DSP     PRCM_REG32(0x8F4)
+
+/* IVA */
+#define PRCM_IRQSTATUS_IVA     PRCM_REG32(0x8F8)
+#define PRCM_IRQENABLE_IVA     PRCM_REG32(0x8FC)
+
+/* Modem on 2430 */
+#define CM_FCLKEN_MDM          PRCM_REG32(0xC00)
+#define CM_ICLKEN_MDM          PRCM_REG32(0xC10)
+#define CM_IDLEST_MDM          PRCM_REG32(0xC20)
+#define CM_CLKSEL_MDM          PRCM_REG32(0xC40)
+
+/* FIXME: Move to header for 2430 */
+#define DISP_BASE              (OMAP24XX_L4_IO_BASE+0x50000)
+#define DISP_REG32(offset)     __REG32(DISP_BASE + (offset))
+
+#define GPMC_BASE              (OMAP24XX_GPMC_BASE)
+#define GPMC_REG32(offset)     __REG32(GPMC_BASE + (offset))
+
+#define GPT1_BASE              (OMAP24XX_GPT1)
+#define GPT1_REG32(offset)     __REG32(GPT1_BASE + (offset))
+
+/* Misc sysconfig */
+#define DISPC_SYSCONFIG                DISP_REG32(0x410)
+#define SPI_BASE               (OMAP24XX_L4_IO_BASE+0x98000)
+#define MCSPI1_SYSCONFIG       __REG32(SPI_BASE + 0x10)
+#define MCSPI2_SYSCONFIG       __REG32(SPI_BASE+0x2000 + 0x10)
+
+//#define DSP_MMU_SYSCONFIG    0x5A000010
+#define CAMERA_MMU_SYSCONFIG   __REG32(DISP_BASE+0x2C10)
+//#define IVA_MMU_SYSCONFIG    0x5D000010
+//#define DSP_DMA_SYSCONFIG    0x00FCC02C
+#define CAMERA_DMA_SYSCONFIG   __REG32(DISP_BASE+0x282C)
+#define SYSTEM_DMA_SYSCONFIG   __REG32(DISP_BASE+0x602C)
+#define GPMC_SYSCONFIG         GPMC_REG32(0x010)
+#define MAILBOXES_SYSCONFIG    __REG32(OMAP24XX_L4_IO_BASE+0x94010)
+#define UART1_SYSCONFIG                __REG32(OMAP24XX_L4_IO_BASE+0x6A054)
+#define UART2_SYSCONFIG                __REG32(OMAP24XX_L4_IO_BASE+0x6C054)
+#define UART3_SYSCONFIG                __REG32(OMAP24XX_L4_IO_BASE+0x6E054)
+//#define IVA_SYSCONFIG                0x5C060010
+#define SDRC_SYSCONFIG         __REG32(OMAP24XX_SDRC_BASE+0x10)
+#define SMS_SYSCONFIG          __REG32(OMAP24XX_SMS_BASE+0x10)
+#define SSI_SYSCONFIG          __REG32(DISP_BASE+0x8010)
+//#define VLYNQ_SYSCONFIG      0x67FFFE10
+
+/* rkw - good cannidates for PM_ to start what nm was trying */
+#define OMAP24XX_GPT2          (OMAP24XX_L4_IO_BASE+0x2A000)
+#define OMAP24XX_GPT3          (OMAP24XX_L4_IO_BASE+0x78000)
+#define OMAP24XX_GPT4          (OMAP24XX_L4_IO_BASE+0x7A000)
+#define OMAP24XX_GPT5          (OMAP24XX_L4_IO_BASE+0x7C000)
+#define OMAP24XX_GPT6          (OMAP24XX_L4_IO_BASE+0x7E000)
+#define OMAP24XX_GPT7          (OMAP24XX_L4_IO_BASE+0x80000)
+#define OMAP24XX_GPT8          (OMAP24XX_L4_IO_BASE+0x82000)
+#define OMAP24XX_GPT9          (OMAP24XX_L4_IO_BASE+0x84000)
+#define OMAP24XX_GPT10         (OMAP24XX_L4_IO_BASE+0x86000)
+#define OMAP24XX_GPT11         (OMAP24XX_L4_IO_BASE+0x88000)
+#define OMAP24XX_GPT12         (OMAP24XX_L4_IO_BASE+0x8A000)
+
+#define GPTIMER1_SYSCONFIG     GPT1_REG32(0x010)
+#define GPTIMER2_SYSCONFIG     __REG32(OMAP24XX_GPT2 + 0x10)
+#define GPTIMER3_SYSCONFIG     __REG32(OMAP24XX_GPT3 + 0x10)
+#define GPTIMER4_SYSCONFIG     __REG32(OMAP24XX_GPT4 + 0x10)
+#define GPTIMER5_SYSCONFIG     __REG32(OMAP24XX_GPT5 + 0x10)
+#define GPTIMER6_SYSCONFIG     __REG32(OMAP24XX_GPT6 + 0x10)
+#define GPTIMER7_SYSCONFIG     __REG32(OMAP24XX_GPT7 + 0x10)
+#define GPTIMER8_SYSCONFIG     __REG32(OMAP24XX_GPT8 + 0x10)
+#define GPTIMER9_SYSCONFIG     __REG32(OMAP24XX_GPT9 + 0x10)
+#define GPTIMER10_SYSCONFIG    __REG32(OMAP24XX_GPT10 + 0x10)
+#define GPTIMER11_SYSCONFIG    __REG32(OMAP24XX_GPT11 + 0x10)
+#define GPTIMER12_SYSCONFIG    __REG32(OMAP24XX_GPT12 + 0x10)
+
+#define GPIOX_BASE(X)          (OMAP24XX_GPIO_BASE+(0x2000*((X)-1)))
+
+#define GPIO1_SYSCONFIG                __REG32((GPIOX_BASE(1)+0x10))
+#define GPIO2_SYSCONFIG                __REG32((GPIOX_BASE(2)+0x10))
+#define GPIO3_SYSCONFIG                __REG32((GPIOX_BASE(3)+0x10))
+#define GPIO4_SYSCONFIG                __REG32((GPIOX_BASE(4)+0x10))
+
+/* GP TIMER 1 */
+#define GPTIMER1_TISTAT                GPT1_REG32(0x014)
+#define GPTIMER1_TISR          GPT1_REG32(0x018)
+#define GPTIMER1_TIER          GPT1_REG32(0x01C)
+#define GPTIMER1_TWER          GPT1_REG32(0x020)
+#define GPTIMER1_TCLR          GPT1_REG32(0x024)
+#define GPTIMER1_TCRR          GPT1_REG32(0x028)
+#define GPTIMER1_TLDR          GPT1_REG32(0x02C)
+#define GPTIMER1_TTGR          GPT1_REG32(0x030)
+#define GPTIMER1_TWPS          GPT1_REG32(0x034)
+#define GPTIMER1_TMAR          GPT1_REG32(0x038)
+#define GPTIMER1_TCAR1         GPT1_REG32(0x03C)
+#define GPTIMER1_TSICR         GPT1_REG32(0x040)
+#define GPTIMER1_TCAR2         GPT1_REG32(0x044)
+
+/* rkw -- base fix up please... */
+#define GPTIMER3_TISR          __REG32(OMAP24XX_L4_IO_BASE+0x78018)
+
+/* SDRC */
+#define SDRC_DLLA_CTRL         __REG32(OMAP24XX_SDRC_BASE+0x060)
+#define SDRC_DLLA_STATUS       __REG32(OMAP24XX_SDRC_BASE+0x064)
+#define SDRC_DLLB_CTRL         __REG32(OMAP24XX_SDRC_BASE+0x068)
+#define SDRC_DLLB_STATUS       __REG32(OMAP24XX_SDRC_BASE+0x06C)
+#define SDRC_POWER             __REG32(OMAP24XX_SDRC_BASE+0x070)
+#define SDRC_MR_0              __REG32(OMAP24XX_SDRC_BASE+0x084)
+
+/* GPIO 1 */
+#define GPIO1_BASE             GPIOX_BASE(1)
+#define GPIO1_REG32(offset)    __REG32(GPIO1_BASE + (offset))
+#define GPIO1_IRQENABLE1       GPIO1_REG32(0x01C)
+#define GPIO1_IRQSTATUS1       GPIO1_REG32(0x018)
+#define GPIO1_IRQENABLE2       GPIO1_REG32(0x02C)
+#define GPIO1_IRQSTATUS2       GPIO1_REG32(0x028)
+#define GPIO1_WAKEUPENABLE     GPIO1_REG32(0x020)
+#define GPIO1_RISINGDETECT     GPIO1_REG32(0x048)
+#define GPIO1_DATAIN           GPIO1_REG32(0x038)
+#define GPIO1_OE               GPIO1_REG32(0x034)
+#define GPIO1_DATAOUT          GPIO1_REG32(0x03C)
+
+/* GPIO2 */
+#define GPIO2_BASE             GPIOX_BASE(2)
+#define GPIO2_REG32(offset)    __REG32(GPIO2_BASE + (offset))
+#define GPIO2_IRQENABLE1       GPIO2_REG32(0x01C)
+#define GPIO2_IRQSTATUS1       GPIO2_REG32(0x018)
+#define GPIO2_IRQENABLE2       GPIO2_REG32(0x02C)
+#define GPIO2_IRQSTATUS2       GPIO2_REG32(0x028)
+#define GPIO2_WAKEUPENABLE     GPIO2_REG32(0x020)
+#define GPIO2_RISINGDETECT     GPIO2_REG32(0x048)
+#define GPIO2_DATAIN           GPIO2_REG32(0x038)
+#define GPIO2_OE               GPIO2_REG32(0x034)
+#define GPIO2_DATAOUT          GPIO2_REG32(0x03C)
+
+/* GPIO 3 */
+#define GPIO3_BASE             GPIOX_BASE(3)
+#define GPIO3_REG32(offset)    __REG32(GPIO3_BASE + (offset))
+#define GPIO3_IRQENABLE1       GPIO3_REG32(0x01C)
+#define GPIO3_IRQSTATUS1       GPIO3_REG32(0x018)
+#define GPIO3_IRQENABLE2       GPIO3_REG32(0x02C)
+#define GPIO3_IRQSTATUS2       GPIO3_REG32(0x028)
+#define GPIO3_WAKEUPENABLE     GPIO3_REG32(0x020)
+#define GPIO3_RISINGDETECT     GPIO3_REG32(0x048)
+#define GPIO3_FALLINGDETECT    GPIO3_REG32(0x04C)
+#define GPIO3_DATAIN           GPIO3_REG32(0x038)
+#define GPIO3_OE               GPIO3_REG32(0x034)
+#define GPIO3_DATAOUT          GPIO3_REG32(0x03C)
+#define GPIO3_DEBOUNCENABLE    GPIO3_REG32(0x050)
+#define GPIO3_DEBOUNCINGTIME   GPIO3_REG32(0x054)
+
+/* GPIO 4 */
+#define GPIO4_BASE             GPIOX_BASE(4)
+#define GPIO4_REG32(offset)    __REG32(GPIO4_BASE + (offset))
+#define GPIO4_IRQENABLE1       GPIO4_REG32(0x01C)
+#define GPIO4_IRQSTATUS1       GPIO4_REG32(0x018)
+#define GPIO4_IRQENABLE2       GPIO4_REG32(0x02C)
+#define GPIO4_IRQSTATUS2       GPIO4_REG32(0x028)
+#define GPIO4_WAKEUPENABLE     GPIO4_REG32(0x020)
+#define GPIO4_RISINGDETECT     GPIO4_REG32(0x048)
+#define GPIO4_FALLINGDETECT    GPIO4_REG32(0x04C)
+#define GPIO4_DATAIN           GPIO4_REG32(0x038)
+#define GPIO4_OE               GPIO4_REG32(0x034)
+#define GPIO4_DATAOUT          GPIO4_REG32(0x03C)
+#define GPIO4_DEBOUNCENABLE    GPIO4_REG32(0x050)
+#define GPIO4_DEBOUNCINGTIME   GPIO4_REG32(0x054)
+
+
+/* IO CONFIG */
+#define CONTROL_BASE           (OMAP24XX_CTRL_BASE)
+#define CONTROL_REG32(offset)  __REG32(CONTROL_BASE + (offset))
+
+#define CONTROL_PADCONF_SPI1_NCS2      CONTROL_REG32(0x104)
+#define CONTROL_PADCONF_SYS_XTALOUT    CONTROL_REG32(0x134)
+#define CONTROL_PADCONF_UART1_RX       CONTROL_REG32(0x0C8)
+#define CONTROL_PADCONF_MCBSP1_DX      CONTROL_REG32(0x10C)
+#define CONTROL_PADCONF_GPMC_NCS4      CONTROL_REG32(0x090)
+#define CONTROL_PADCONF_DSS_D5         CONTROL_REG32(0x0B8)
+#define CONTROL_PADCONF_DSS_D9         CONTROL_REG32(0x0BC)
+#define CONTROL_PADCONF_DSS_D13                CONTROL_REG32(0x0C0)
+#define CONTROL_PADCONF_DSS_VSYNC      CONTROL_REG32(0x0CC)
+
+/* CONTROL */
+#define CONTROL_DEVCONF                CONTROL_REG32(0x274)
+
+/* INTERRUPT CONTROLLER */
+#define INTC_BASE              (OMAP24XX_L4_IO_BASE+0xfe000)
+#define INTC_REG32(offset)     __REG32(INTC_BASE + (offset))
+
+#define INTC1_U_BASE           INTC_REG32(0x000)
+#define INTC_MIR0              INTC_REG32(0x084)
+#define INTC_MIR_SET0          INTC_REG32(0x08C)
+#define INTC_MIR_CLEAR0                INTC_REG32(0x088)
+#define INTC_ISR_CLEAR0                INTC_REG32(0x094)
+#define INTC_MIR1              INTC_REG32(0x0A4)
+#define INTC_MIR_SET1          INTC_REG32(0x0AC)
+#define INTC_MIR_CLEAR1                INTC_REG32(0x0A8)
+#define INTC_ISR_CLEAR1                INTC_REG32(0x0B4)
+#define INTC_MIR2              INTC_REG32(0x0C4)
+#define INTC_MIR_SET2          INTC_REG32(0x0CC)
+#define INTC_MIR_CLEAR2                INTC_REG32(0x0C8)
+#define INTC_ISR_CLEAR2                INTC_REG32(0x0D4)
+#define INTC_SIR_IRQ           INTC_REG32(0x040)
+#define INTC_CONTROL           INTC_REG32(0x048)
+#define INTC_ILR11             INTC_REG32(0x12C)
+#define INTC_ILR32             INTC_REG32(0x180)
+#define INTC_ILR37             INTC_REG32(0x194)
+#define INTC_SYSCONFIG         INTC_REG32(0x010)
+
+/* RAM FIREWALL */
+#define RAMFW_BASE             (0x68005000)
+#define RAMFW_REG32(offset)    __REG32(RAMFW_BASE + (offset))
+
+#define RAMFW_REQINFOPERM0     RAMFW_REG32(0x048)
+#define RAMFW_READPERM0                RAMFW_REG32(0x050)
+#define RAMFW_WRITEPERM0       RAMFW_REG32(0x058)
+
+/* GPMC CS1 FPGA ON USER INTERFACE MODULE */
+//#define DEBUG_BOARD_LED_REGISTER 0x04000014
+
+/* GPMC CS0 */
+#define GPMC_CONFIG1_0         GPMC_REG32(0x060)
+#define GPMC_CONFIG2_0         GPMC_REG32(0x064)
+#define GPMC_CONFIG3_0         GPMC_REG32(0x068)
+#define GPMC_CONFIG4_0         GPMC_REG32(0x06C)
+#define GPMC_CONFIG5_0         GPMC_REG32(0x070)
+#define GPMC_CONFIG6_0         GPMC_REG32(0x074)
+#define GPMC_CONFIG7_0         GPMC_REG32(0x078)
+
+/* DSS */
+#define DSS_CONTROL            DISP_REG32(0x040)
+#define DISPC_CONTROL          DISP_REG32(0x440)
+#define DISPC_SYSSTATUS                DISP_REG32(0x414)
+#define DISPC_IRQSTATUS                DISP_REG32(0x418)
+#define DISPC_IRQENABLE                DISP_REG32(0x41C)
+#define DISPC_CONFIG           DISP_REG32(0x444)
+#define DISPC_DEFAULT_COLOR0   DISP_REG32(0x44C)
+#define DISPC_DEFAULT_COLOR1   DISP_REG32(0x450)
+#define DISPC_TRANS_COLOR0     DISP_REG32(0x454)
+#define DISPC_TRANS_COLOR1     DISP_REG32(0x458)
+#define DISPC_LINE_NUMBER      DISP_REG32(0x460)
+#define DISPC_TIMING_H         DISP_REG32(0x464)
+#define DISPC_TIMING_V         DISP_REG32(0x468)
+#define DISPC_POL_FREQ         DISP_REG32(0x46C)
+#define DISPC_DIVISOR          DISP_REG32(0x470)
+#define DISPC_SIZE_DIG         DISP_REG32(0x478)
+#define DISPC_SIZE_LCD         DISP_REG32(0x47C)
+#define DISPC_GFX_BA0          DISP_REG32(0x480)
+#define DISPC_GFX_BA1          DISP_REG32(0x484)
+#define DISPC_GFX_POSITION     DISP_REG32(0x488)
+#define DISPC_GFX_SIZE         DISP_REG32(0x48C)
+#define DISPC_GFX_ATTRIBUTES   DISP_REG32(0x4A0)
+#define DISPC_GFX_FIFO_THRESHOLD       DISP_REG32(0x4A4)
+#define DISPC_GFX_ROW_INC      DISP_REG32(0x4AC)
+#define DISPC_GFX_PIXEL_INC    DISP_REG32(0x4B0)
+#define DISPC_GFX_WINDOW_SKIP  DISP_REG32(0x4B4)
+#define DISPC_GFX_TABLE_BA     DISP_REG32(0x4B8)
+#define DISPC_DATA_CYCLE1      DISP_REG32(0x5D4)
+#define DISPC_DATA_CYCLE2      DISP_REG32(0x5D8)
+#define DISPC_DATA_CYCLE3      DISP_REG32(0x5DC)
+
+/* Wake up define for board */
+#define GPIO97                 (1 << 1)
+#define GPIO88                 (1 << 24)
+
+#endif /* __ASSEMBLER__ */
+
+#endif
+
+
+
+
+
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
new file mode 100644 (file)
index 0000000..f4df04f
--- /dev/null
@@ -0,0 +1,180 @@
+/*
+ * arch/arm/mach-omap/omap2/serial.c
+ *
+ * OMAP2 serial support.
+ *
+ * Copyright (C) 2005 Nokia Corporation
+ * Author: Paul Mundt <paul.mundt@nokia.com>
+ *
+ * Based off of arch/arm/mach-omap/omap1/serial.c
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/serial_8250.h>
+#include <linux/serial_reg.h>
+
+#include <asm/io.h>
+#include <asm/hardware/clock.h>
+
+#include <asm/arch/common.h>
+#include <asm/arch/board.h>
+
+static struct clk * uart1_ick = NULL;
+static struct clk * uart1_fck = NULL;
+static struct clk * uart2_ick = NULL;
+static struct clk * uart2_fck = NULL;
+static struct clk * uart3_ick = NULL;
+static struct clk * uart3_fck = NULL;
+
+static struct plat_serial8250_port serial_platform_data[] = {
+       {
+               .membase        = (char *)IO_ADDRESS(OMAP_UART1_BASE),
+               .mapbase        = (unsigned long)OMAP_UART1_BASE,
+               .irq            = 72,
+               .flags          = UPF_BOOT_AUTOCONF,
+               .iotype         = UPIO_MEM,
+               .regshift       = 2,
+               .uartclk        = OMAP16XX_BASE_BAUD * 16,
+       }, {
+               .membase        = (char *)IO_ADDRESS(OMAP_UART2_BASE),
+               .mapbase        = (unsigned long)OMAP_UART2_BASE,
+               .irq            = 73,
+               .flags          = UPF_BOOT_AUTOCONF,
+               .iotype         = UPIO_MEM,
+               .regshift       = 2,
+               .uartclk        = OMAP16XX_BASE_BAUD * 16,
+       }, {
+               .membase        = (char *)IO_ADDRESS(OMAP_UART3_BASE),
+               .mapbase        = (unsigned long)OMAP_UART3_BASE,
+               .irq            = 74,
+               .flags          = UPF_BOOT_AUTOCONF,
+               .iotype         = UPIO_MEM,
+               .regshift       = 2,
+               .uartclk        = OMAP16XX_BASE_BAUD * 16,
+       }, {
+               .flags          = 0
+       }
+};
+
+static inline unsigned int serial_read_reg(struct plat_serial8250_port *up,
+                                          int offset)
+{
+       offset <<= up->regshift;
+       return (unsigned int)__raw_readb(up->membase + offset);
+}
+
+static inline void serial_write_reg(struct plat_serial8250_port *p, int offset,
+                                   int value)
+{
+       offset <<= p->regshift;
+       __raw_writeb(value, (unsigned long)(p->membase + offset));
+}
+
+/*
+ * Internal UARTs need to be initialized for the 8250 autoconfig to work
+ * properly. Note that the TX watermark initialization may not be needed
+ * once the 8250.c watermark handling code is merged.
+ */
+static inline void __init omap_serial_reset(struct plat_serial8250_port *p)
+{
+       serial_write_reg(p, UART_OMAP_MDR1, 0x07);
+       serial_write_reg(p, UART_OMAP_SCR, 0x08);
+       serial_write_reg(p, UART_OMAP_MDR1, 0x00);
+       serial_write_reg(p, UART_OMAP_SYSC, 0x01);
+}
+
+void __init omap_serial_init()
+{
+       int i;
+       const struct omap_uart_config *info;
+
+       /*
+        * Make sure the serial ports are muxed on at this point.
+        * You have to mux them off in device drivers later on
+        * if not needed.
+        */
+
+       info = omap_get_config(OMAP_TAG_UART,
+                              struct omap_uart_config);
+
+       if (info == NULL)
+               return;
+
+       for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
+               struct plat_serial8250_port *p = serial_platform_data + i;
+
+               if (!(info->enabled_uarts & (1 << i))) {
+                       p->membase = 0;
+                       p->mapbase = 0;
+                       continue;
+               }
+
+               switch (i) {
+               case 0:
+                       uart1_ick = clk_get(NULL, "uart1_ick");
+                       if (IS_ERR(uart1_ick))
+                               printk("Could not get uart1_ick\n");
+                       else {
+                               clk_use(uart1_ick);
+                       }
+
+                       uart1_fck = clk_get(NULL, "uart1_fck");
+                       if (IS_ERR(uart1_fck))
+                               printk("Could not get uart1_fck\n");
+                       else {
+                               clk_use(uart1_fck);
+                       }
+                       break;
+               case 1:
+                       uart2_ick = clk_get(NULL, "uart2_ick");
+                       if (IS_ERR(uart2_ick))
+                               printk("Could not get uart2_ick\n");
+                       else {
+                               clk_use(uart2_ick);
+                       }
+
+                       uart2_fck = clk_get(NULL, "uart2_fck");
+                       if (IS_ERR(uart2_fck))
+                               printk("Could not get uart2_fck\n");
+                       else {
+                               clk_use(uart2_fck);
+                       }
+                       break;
+               case 2:
+                       uart3_ick = clk_get(NULL, "uart3_ick");
+                       if (IS_ERR(uart3_ick))
+                               printk("Could not get uart3_ick\n");
+                       else {
+                               clk_use(uart3_ick);
+                       }
+
+                       uart3_fck = clk_get(NULL, "uart3_fck");
+                       if (IS_ERR(uart3_fck))
+                               printk("Could not get uart3_fck\n");
+                       else {
+                               clk_use(uart3_fck);
+                       }
+                       break;
+               }
+
+               omap_serial_reset(p);
+       }
+}
+
+static struct platform_device serial_device = {
+       .name                   = "serial8250",
+       .id                     = 0,
+       .dev                    = {
+               .platform_data  = serial_platform_data,
+       },
+};
+
+static int __init omap_init(void)
+{
+       return platform_device_register(&serial_device);
+}
+arch_initcall(omap_init);
diff --git a/arch/arm/mach-omap2/sram-fn.S b/arch/arm/mach-omap2/sram-fn.S
new file mode 100644 (file)
index 0000000..2a869e2
--- /dev/null
@@ -0,0 +1,333 @@
+/*
+ * linux/arch/arm/mach-omap1/sram.S
+ *
+ * Omap2 specific functions that need to be run in internal SRAM
+ *
+ * (C) Copyright 2004
+ * Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <linux/config.h>
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <asm/arch/io.h>
+#include <asm/hardware.h>
+
+#include <asm/arch/prcm.h>
+
+#define TIMER_32KSYNCT_CR_V    IO_ADDRESS(OMAP24XX_32KSYNCT_BASE + 0x010)
+
+#define CM_CLKSEL2_PLL_V       IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x544)
+#define PRCM_VOLTCTRL_V                IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x050)
+#define PRCM_CLKCFG_CTRL_V     IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x080)
+#define CM_CLKEN_PLL_V         IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x500)
+#define CM_IDLEST_CKGEN_V      IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x520)
+#define CM_CLKSEL1_PLL_V       IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x540)
+
+#define SDRC_DLLA_CTRL_V       IO_ADDRESS(OMAP24XX_SDRC_BASE + 0x060)
+#define SDRC_RFR_CTRL_V                IO_ADDRESS(OMAP24XX_SDRC_BASE + 0x0a4)
+
+       .text
+
+ENTRY(sram_ddr_init)
+       stmfd   sp!, {r0 - r12, lr}     @ save registers on stack
+
+       mov     r12, r2                 @ capture CS1 vs CS0
+       mov     r8, r3                  @ capture force parameter
+
+       /* frequency shift down */
+       ldr     r2, cm_clksel2_pll      @ get address of dpllout reg
+       mov     r3, #0x1                @ value for 1x operation
+       str     r3, [r2]                @ go to L1-freq operation
+
+       /* voltage shift down */
+       mov r9, #0x1                    @ set up for L1 voltage call
+       bl voltage_shift                @ go drop voltage
+
+       /* dll lock mode */
+       ldr     r11, sdrc_dlla_ctrl     @ addr of dlla ctrl
+       ldr     r10, [r11]              @ get current val
+       cmp     r12, #0x1               @ cs1 base (2422 es2.05/1)
+       addeq   r11, r11, #0x8          @ if cs1 base, move to DLLB
+       mvn     r9, #0x4                @ mask to get clear bit2
+       and     r10, r10, r9            @ clear bit2 for lock mode.
+       orr     r10, r10, #0x8          @ make sure DLL on (es2 bit pos)
+       orr     r10, r10, #0x2          @ 90 degree phase for all below 133Mhz
+       str     r10, [r11]              @ commit to DLLA_CTRL
+       bl      i_dll_wait              @ wait for dll to lock
+
+       /* get dll value */
+       add     r11, r11, #0x4          @ get addr of status reg
+       ldr     r10, [r11]              @ get locked value
+
+       /* voltage shift up */
+       mov r9, #0x0                    @ shift back to L0-voltage
+       bl voltage_shift                @ go raise voltage
+
+       /* frequency shift up */
+       mov     r3, #0x2                @ value for 2x operation
+       str     r3, [r2]                @ go to L0-freq operation
+
+       /* reset entry mode for dllctrl */
+       sub     r11, r11, #0x4          @ move from status to ctrl
+       cmp     r12, #0x1               @ normalize if cs1 based
+       subeq   r11, r11, #0x8          @ possibly back to DLLA
+       cmp     r8, #0x1                @ if forced unlock exit
+       orreq   r1, r1, #0x4            @ make sure exit with unlocked value
+       str     r1, [r11]               @ restore DLLA_CTRL high value
+       add     r11, r11, #0x8          @ move to DLLB_CTRL addr
+       str     r1, [r11]               @ set value DLLB_CTRL
+       bl      i_dll_wait              @ wait for possible lock
+
+       /* set up for return, DDR should be good */
+       str r10, [r0]                   @ write dll_status and return counter
+       ldmfd   sp!, {r0 - r12, pc}     @ restore regs and return
+
+       /* ensure the DLL has relocked */
+i_dll_wait:
+       mov     r4, #0x800              @ delay DLL relock, min 0x400 L3 clocks
+i_dll_delay:
+       subs    r4, r4, #0x1
+       bne     i_dll_delay
+       mov     pc, lr
+
+       /*
+        * shift up or down voltage, use R9 as input to tell level.
+        * wait for it to finish, use 32k sync counter, 1tick=31uS.
+        */
+voltage_shift:
+       ldr     r4, prcm_voltctrl       @ get addr of volt ctrl.
+       ldr     r5, [r4]                @ get value.
+       ldr     r6, prcm_mask_val       @ get value of mask
+       and     r5, r5, r6              @ apply mask to clear bits
+       orr     r5, r5, r9              @ bulld value for L0/L1-volt operation.
+       str     r5, [r4]                @ set up for change.
+       mov     r3, #0x4000             @ get val for force
+       orr     r5, r5, r3              @ build value for force
+       str     r5, [r4]                @ Force transition to L1
+
+       ldr     r3, timer_32ksynct_cr   @ get addr of counter
+       ldr     r5, [r3]                @ get value
+       add     r5, r5, #0x3            @ give it at most 93uS
+volt_delay:
+       ldr     r7, [r3]                @ get timer value
+       cmp     r5, r7                  @ time up?
+       bhi     volt_delay              @ not yet->branch
+       mov     pc, lr                  @ back to caller.
+
+/* relative load constants */
+cm_clksel2_pll:
+       .word CM_CLKSEL2_PLL_V
+sdrc_dlla_ctrl:
+       .word SDRC_DLLA_CTRL_V
+prcm_voltctrl:
+       .word PRCM_VOLTCTRL_V
+prcm_mask_val:
+       .word 0xFFFF3FFC
+timer_32ksynct_cr:
+       .word TIMER_32KSYNCT_CR_V
+ENTRY(sram_ddr_init_sz)
+       .word   . - sram_ddr_init
+
+/*
+ * Reprograms memory timings.
+ * r0 = [PRCM_FULL | PRCM_HALF] r1 = SDRC_DLLA_CTRL value r2 = [DDR | SDR]
+ * PRCM_FULL = 2, PRCM_HALF = 1, DDR = 1, SDR = 0
+ */
+ENTRY(sram_reprogram_sdrc)
+       stmfd   sp!, {r0 - r10, lr}     @ save registers on stack
+       mov     r3, #0x0                @ clear for mrc call
+       mcr     p15, 0, r3, c7, c10, 4  @ memory barrier, finish ARM SDR/DDR
+       nop
+       nop
+       ldr     r6, ddr_sdrc_rfr_ctrl   @ get addr of refresh reg
+       ldr     r5, [r6]                @ get value
+       mov     r5, r5, lsr #8          @ isolate rfr field and drop burst
+
+       cmp     r0, #0x1                @ going to half speed?
+       movne   r9, #0x0                @ if up set flag up for pre up, hi volt
+
+       blne    voltage_shift_c         @ adjust voltage
+
+       cmp     r0, #0x1                @ going to half speed (post branch link)
+       moveq   r5, r5, lsr #1          @ divide by 2 if to half
+       movne   r5, r5, lsl #1          @ mult by 2 if to full
+       mov     r5, r5, lsl #8          @ put rfr field back into place
+       add     r5, r5, #0x1            @ turn on burst of 1
+       ldr     r4, ddr_cm_clksel2_pll  @ get address of out reg
+       ldr     r3, [r4]                @ get curr value
+       orr     r3, r3, #0x3
+       bic     r3, r3, #0x3            @ clear lower bits
+       orr     r3, r3, r0              @ new state value
+       str     r3, [r4]                @ set new state (pll/x, x=1 or 2)
+       nop
+       nop
+
+       moveq   r9, #0x1                @ if speed down, post down, drop volt
+       bleq    voltage_shift_c
+
+       mcr     p15, 0, r3, c7, c10, 4  @ memory barrier
+       str     r5, [r6]                @ set new RFR_1 value
+       add     r6, r6, #0x30           @ get RFR_2 addr
+       str     r5, [r6]                @ set RFR_2
+       nop
+       cmp     r2, #0x1                @ (SDR or DDR) do we need to adjust DLL
+       bne     freq_out                @ leave if SDR, no DLL function
+
+       /* With DDR, we need to take care of the DLL for the frequency change */
+       ldr     r2, ddr_sdrc_dlla_ctrl  @ addr of dlla ctrl
+       str     r1, [r2]                @ write out new SDRC_DLLA_CTRL
+       add     r2, r2, #0x8            @ addr to SDRC_DLLB_CTRL
+       str     r1, [r2]                @ commit to SDRC_DLLB_CTRL
+       mov     r1, #0x2000             @ wait DLL relock, min 0x400 L3 clocks
+dll_wait:
+       subs    r1, r1, #0x1
+       bne     dll_wait
+freq_out:
+       ldmfd   sp!, {r0 - r10, pc}     @ restore regs and return
+
+    /*
+     * shift up or down voltage, use R9 as input to tell level.
+     * wait for it to finish, use 32k sync counter, 1tick=31uS.
+     */
+voltage_shift_c:
+       ldr     r10, ddr_prcm_voltctrl  @ get addr of volt ctrl
+       ldr     r8, [r10]               @ get value
+       ldr     r7, ddr_prcm_mask_val   @ get value of mask
+       and     r8, r8, r7              @ apply mask to clear bits
+       orr     r8, r8, r9              @ bulld value for L0/L1-volt operation.
+       str     r8, [r10]               @ set up for change.
+       mov     r7, #0x4000             @ get val for force
+       orr     r8, r8, r7              @ build value for force
+       str     r8, [r10]               @ Force transition to L1
+
+       ldr     r10, ddr_timer_32ksynct @ get addr of counter
+       ldr     r8, [r10]               @ get value
+       add     r8, r8, #0x2            @ give it at most 62uS (min 31+)
+volt_delay_c:
+       ldr     r7, [r10]               @ get timer value
+       cmp     r8, r7                  @ time up?
+       bhi     volt_delay_c            @ not yet->branch
+       mov     pc, lr                  @ back to caller
+
+ddr_cm_clksel2_pll:
+       .word CM_CLKSEL2_PLL_V
+ddr_sdrc_dlla_ctrl:
+       .word SDRC_DLLA_CTRL_V
+ddr_sdrc_rfr_ctrl:
+       .word SDRC_RFR_CTRL_V
+ddr_prcm_voltctrl:
+       .word PRCM_VOLTCTRL_V
+ddr_prcm_mask_val:
+       .word 0xFFFF3FFC
+ddr_timer_32ksynct:
+       .word TIMER_32KSYNCT_CR_V
+
+ENTRY(sram_reprogram_sdrc_sz)
+       .word   . - sram_reprogram_sdrc
+
+/*
+ * Set dividers and pll. Also recalculate DLL value for DDR and unlock mode.
+ */
+ENTRY(sram_set_prcm)
+       stmfd   sp!, {r0-r12, lr}       @ regs to stack
+       adr     r4, pbegin              @ addr of preload start
+       adr     r8, pend                @ addr of preload end
+       mcrr    p15, 1, r8, r4, c12     @ preload into icache
+pbegin:
+       /* move into fast relock bypass */
+       ldr     r8, pll_ctl             @ get addr
+       ldr     r5, [r8]                @ get val
+       mvn     r6, #0x3                @ clear mask
+       and     r5, r5, r6              @ clear field
+       orr     r7, r5, #0x2            @ fast relock val
+       str     r7, [r8]                @ go to fast relock
+       ldr     r4, pll_stat            @ addr of stat
+block:
+       /* wait for bypass */
+       ldr     r8, [r4]                @ stat value
+       and     r8, r8, #0x3            @ mask for stat
+       cmp     r8, #0x1                @ there yet
+       bne     block                   @ loop if not
+
+       /* set new dpll dividers _after_ in bypass */
+       ldr     r4, pll_div             @ get addr
+       str     r0, [r4]                @ set dpll ctrl val
+
+       ldr     r4, set_config          @ get addr
+       mov     r8, #1                  @ valid cfg msk
+       str     r8, [r4]                @ make dividers take
+
+       mov     r4, #100                @ dead spin a bit
+wait_a_bit:
+       subs    r4, r4, #1              @ dec loop
+       bne     wait_a_bit              @ delay done?
+
+       /* check if staying in bypass */
+       cmp     r2, #0x1                @ stay in bypass?
+       beq     pend                    @ jump over dpll relock
+
+       /* relock DPLL with new vals */
+       ldr     r5, pll_stat            @ get addr
+       ldr     r4, pll_ctl             @ get addr
+       orr     r8, r7, #0x3            @ val for lock dpll
+       str     r8, [r4]                @ set val
+       mov     r0, #1000               @ dead spin a bit
+wait_more:
+       subs    r0, r0, #1              @ dec loop
+       bne     wait_more               @ delay done?
+wait_lock:
+       ldr     r8, [r5]                @ get lock val
+       and     r8, r8, #3              @ isolate field
+       cmp     r8, #2                  @ locked?
+       bne     wait_lock               @ wait if not
+pend:
+       /* update memory timings & briefly lock dll */
+       ldr     r4, sdrc_rfr            @ get addr
+       str     r1, [r4]                @ update refresh timing
+       ldr     r11, dlla_ctrl          @ get addr of DLLA ctrl
+       ldr     r10, [r11]              @ get current val
+       mvn     r9, #0x4                @ mask to get clear bit2
+       and     r10, r10, r9            @ clear bit2 for lock mode
+       orr     r10, r10, #0x8          @ make sure DLL on (es2 bit pos)
+       str     r10, [r11]              @ commit to DLLA_CTRL
+       add     r11, r11, #0x8          @ move to dllb
+       str     r10, [r11]              @ hit DLLB also
+
+       mov     r4, #0x800              @ relock time (min 0x400 L3 clocks)
+wait_dll_lock:
+       subs    r4, r4, #0x1
+       bne     wait_dll_lock
+       nop
+       ldmfd   sp!, {r0-r12, pc}       @ restore regs and return
+
+set_config:
+       .word PRCM_CLKCFG_CTRL_V
+pll_ctl:
+       .word CM_CLKEN_PLL_V
+pll_stat:
+       .word CM_IDLEST_CKGEN_V
+pll_div:
+       .word CM_CLKSEL1_PLL_V
+sdrc_rfr:
+       .word SDRC_RFR_CTRL_V
+dlla_ctrl:
+       .word SDRC_DLLA_CTRL_V
+
+ENTRY(sram_set_prcm_sz)
+       .word   . - sram_set_prcm
diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c
new file mode 100644 (file)
index 0000000..9ec1144
--- /dev/null
@@ -0,0 +1,126 @@
+/*
+ * linux/arch/arm/mach-omap2/timer-gp.c
+ *
+ * OMAP2 GP timer support.
+ *
+ * Copyright (C) 2005 Nokia Corporation
+ * Author: Paul Mundt <paul.mundt@nokia.com>
+ *         Juha Yrjölä <juha.yrjola@nokia.com>
+ *
+ * Some parts based off of TI's 24xx code:
+ *
+ *   Copyright (C) 2004 Texas Instruments, Inc.
+ *
+ * Roughly modelled after the OMAP1 MPU timer code.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/init.h>
+#include <linux/time.h>
+#include <linux/interrupt.h>
+#include <linux/err.h>
+#include <asm/mach/time.h>
+#include <asm/delay.h>
+#include <asm/io.h>
+#include <asm/hardware/clock.h>
+
+#define OMAP2_GP_TIMER1_BASE   0x48028000
+#define OMAP2_GP_TIMER2_BASE   0x4802a000
+#define OMAP2_GP_TIMER3_BASE   0x48078000
+#define OMAP2_GP_TIMER4_BASE   0x4807a000
+
+#define GP_TIMER_TIDR          0x00
+#define GP_TIMER_TISR          0x18
+#define GP_TIMER_TIER          0x1c
+#define GP_TIMER_TCLR          0x24
+#define GP_TIMER_TCRR          0x28
+#define GP_TIMER_TLDR          0x2c
+#define GP_TIMER_TSICR         0x40
+
+#define OS_TIMER_NR            1  /* GP timer 2 */
+
+static unsigned long timer_base[] = {
+       IO_ADDRESS(OMAP2_GP_TIMER1_BASE),
+       IO_ADDRESS(OMAP2_GP_TIMER2_BASE),
+       IO_ADDRESS(OMAP2_GP_TIMER3_BASE),
+       IO_ADDRESS(OMAP2_GP_TIMER4_BASE),
+};
+
+static inline unsigned int timer_read_reg(int nr, unsigned int reg)
+{
+       return __raw_readl(timer_base[nr] + reg);
+}
+
+static inline void timer_write_reg(int nr, unsigned int reg, unsigned int val)
+{
+       __raw_writel(val, timer_base[nr] + reg);
+}
+
+/* Note that we always enable the clock prescale divider bit */
+static inline void omap2_gp_timer_start(int nr, unsigned long load_val)
+{
+       unsigned int tmp;
+
+       tmp = 0xffffffff - load_val;
+
+       timer_write_reg(nr, GP_TIMER_TLDR, tmp);
+       timer_write_reg(nr, GP_TIMER_TCRR, tmp);
+       timer_write_reg(nr, GP_TIMER_TIER, 1 << 1);
+       timer_write_reg(nr, GP_TIMER_TCLR, (1 << 5) | (1 << 1) | 1);
+}
+
+static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id,
+                                           struct pt_regs *regs)
+{
+       write_seqlock(&xtime_lock);
+
+       timer_write_reg(OS_TIMER_NR, GP_TIMER_TISR, 1 << 1);
+       timer_tick(regs);
+
+       write_sequnlock(&xtime_lock);
+
+       return IRQ_HANDLED;
+}
+
+static struct irqaction omap2_gp_timer_irq = {
+       .name           = "gp timer",
+       .flags          = SA_INTERRUPT,
+       .handler        = omap2_gp_timer_interrupt,
+};
+
+static void __init omap2_gp_timer_init(void)
+{
+       struct clk * sys_ck;
+       u32 tick_period = 120000;
+       u32 l;
+
+       /* Reset clock and prescale value */
+       timer_write_reg(OS_TIMER_NR, GP_TIMER_TCLR, 0);
+
+       sys_ck = clk_get(NULL, "sys_ck");
+       if (IS_ERR(sys_ck))
+               printk(KERN_ERR "Could not get sys_ck\n");
+       else {
+               clk_use(sys_ck);
+               tick_period = clk_get_rate(sys_ck) / 100;
+               clk_put(sys_ck);
+       }
+
+       tick_period /= 2;       /* Minimum prescale divider is 2 */
+       tick_period -= 1;
+
+       l = timer_read_reg(OS_TIMER_NR, GP_TIMER_TIDR);
+       printk(KERN_INFO "OMAP2 GP timer (HW version %d.%d)\n",
+              (l >> 4) & 0x0f, l & 0x0f);
+
+       setup_irq(38, &omap2_gp_timer_irq);
+
+       omap2_gp_timer_start(OS_TIMER_NR, tick_period);
+}
+
+struct sys_timer omap_timer = {
+       .init   = omap2_gp_timer_init,
+};
+
index 4e8d193..e84fdde 100644 (file)
@@ -242,7 +242,7 @@ config CPU_XSCALE
 # ARMv6
 config CPU_V6
        bool "Support ARM V6 processor"
-       depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB
+       depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2
        select CPU_32v6
        select CPU_ABRT_EV6
        select CPU_CACHE_V6