x86, apicv: add virtual interrupt delivery support
[linux-3.10.git] / virt / kvm / ioapic.c
1 /*
2  *  Copyright (C) 2001  MandrakeSoft S.A.
3  *  Copyright 2010 Red Hat, Inc. and/or its affiliates.
4  *
5  *    MandrakeSoft S.A.
6  *    43, rue d'Aboukir
7  *    75002 Paris - France
8  *    http://www.linux-mandrake.com/
9  *    http://www.mandrakesoft.com/
10  *
11  *  This library is free software; you can redistribute it and/or
12  *  modify it under the terms of the GNU Lesser General Public
13  *  License as published by the Free Software Foundation; either
14  *  version 2 of the License, or (at your option) any later version.
15  *
16  *  This library is distributed in the hope that it will be useful,
17  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
18  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
19  *  Lesser General Public License for more details.
20  *
21  *  You should have received a copy of the GNU Lesser General Public
22  *  License along with this library; if not, write to the Free Software
23  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
24  *
25  *  Yunhong Jiang <yunhong.jiang@intel.com>
26  *  Yaozu (Eddie) Dong <eddie.dong@intel.com>
27  *  Based on Xen 3.1 code.
28  */
29
30 #include <linux/kvm_host.h>
31 #include <linux/kvm.h>
32 #include <linux/mm.h>
33 #include <linux/highmem.h>
34 #include <linux/smp.h>
35 #include <linux/hrtimer.h>
36 #include <linux/io.h>
37 #include <linux/slab.h>
38 #include <linux/export.h>
39 #include <asm/processor.h>
40 #include <asm/page.h>
41 #include <asm/current.h>
42 #include <trace/events/kvm.h>
43
44 #include "ioapic.h"
45 #include "lapic.h"
46 #include "irq.h"
47
48 #if 0
49 #define ioapic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg)
50 #else
51 #define ioapic_debug(fmt, arg...)
52 #endif
53 static int ioapic_deliver(struct kvm_ioapic *vioapic, int irq);
54
55 static unsigned long ioapic_read_indirect(struct kvm_ioapic *ioapic,
56                                           unsigned long addr,
57                                           unsigned long length)
58 {
59         unsigned long result = 0;
60
61         switch (ioapic->ioregsel) {
62         case IOAPIC_REG_VERSION:
63                 result = ((((IOAPIC_NUM_PINS - 1) & 0xff) << 16)
64                           | (IOAPIC_VERSION_ID & 0xff));
65                 break;
66
67         case IOAPIC_REG_APIC_ID:
68         case IOAPIC_REG_ARB_ID:
69                 result = ((ioapic->id & 0xf) << 24);
70                 break;
71
72         default:
73                 {
74                         u32 redir_index = (ioapic->ioregsel - 0x10) >> 1;
75                         u64 redir_content;
76
77                         ASSERT(redir_index < IOAPIC_NUM_PINS);
78
79                         redir_content = ioapic->redirtbl[redir_index].bits;
80                         result = (ioapic->ioregsel & 0x1) ?
81                             (redir_content >> 32) & 0xffffffff :
82                             redir_content & 0xffffffff;
83                         break;
84                 }
85         }
86
87         return result;
88 }
89
90 static int ioapic_service(struct kvm_ioapic *ioapic, unsigned int idx)
91 {
92         union kvm_ioapic_redirect_entry *pent;
93         int injected = -1;
94
95         pent = &ioapic->redirtbl[idx];
96
97         if (!pent->fields.mask) {
98                 injected = ioapic_deliver(ioapic, idx);
99                 if (injected && pent->fields.trig_mode == IOAPIC_LEVEL_TRIG)
100                         pent->fields.remote_irr = 1;
101         }
102
103         return injected;
104 }
105
106 static void update_handled_vectors(struct kvm_ioapic *ioapic)
107 {
108         DECLARE_BITMAP(handled_vectors, 256);
109         int i;
110
111         memset(handled_vectors, 0, sizeof(handled_vectors));
112         for (i = 0; i < IOAPIC_NUM_PINS; ++i)
113                 __set_bit(ioapic->redirtbl[i].fields.vector, handled_vectors);
114         memcpy(ioapic->handled_vectors, handled_vectors,
115                sizeof(handled_vectors));
116         smp_wmb();
117 }
118
119 void kvm_ioapic_calculate_eoi_exitmap(struct kvm_vcpu *vcpu,
120                                         u64 *eoi_exit_bitmap)
121 {
122         struct kvm_ioapic *ioapic = vcpu->kvm->arch.vioapic;
123         union kvm_ioapic_redirect_entry *e;
124         struct kvm_lapic_irq irqe;
125         int index;
126
127         spin_lock(&ioapic->lock);
128         /* traverse ioapic entry to set eoi exit bitmap*/
129         for (index = 0; index < IOAPIC_NUM_PINS; index++) {
130                 e = &ioapic->redirtbl[index];
131                 if (!e->fields.mask &&
132                         (e->fields.trig_mode == IOAPIC_LEVEL_TRIG ||
133                          kvm_irq_has_notifier(ioapic->kvm, KVM_IRQCHIP_IOAPIC,
134                                  index))) {
135                         irqe.dest_id = e->fields.dest_id;
136                         irqe.vector = e->fields.vector;
137                         irqe.dest_mode = e->fields.dest_mode;
138                         irqe.delivery_mode = e->fields.delivery_mode << 8;
139                         kvm_calculate_eoi_exitmap(vcpu, &irqe, eoi_exit_bitmap);
140                 }
141         }
142         spin_unlock(&ioapic->lock);
143 }
144 EXPORT_SYMBOL_GPL(kvm_ioapic_calculate_eoi_exitmap);
145
146 void kvm_ioapic_make_eoibitmap_request(struct kvm *kvm)
147 {
148         struct kvm_ioapic *ioapic = kvm->arch.vioapic;
149
150         if (!kvm_apic_vid_enabled(kvm) || !ioapic)
151                 return;
152         kvm_make_update_eoibitmap_request(kvm);
153 }
154
155 static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val)
156 {
157         unsigned index;
158         bool mask_before, mask_after;
159         union kvm_ioapic_redirect_entry *e;
160
161         switch (ioapic->ioregsel) {
162         case IOAPIC_REG_VERSION:
163                 /* Writes are ignored. */
164                 break;
165
166         case IOAPIC_REG_APIC_ID:
167                 ioapic->id = (val >> 24) & 0xf;
168                 break;
169
170         case IOAPIC_REG_ARB_ID:
171                 break;
172
173         default:
174                 index = (ioapic->ioregsel - 0x10) >> 1;
175
176                 ioapic_debug("change redir index %x val %x\n", index, val);
177                 if (index >= IOAPIC_NUM_PINS)
178                         return;
179                 e = &ioapic->redirtbl[index];
180                 mask_before = e->fields.mask;
181                 if (ioapic->ioregsel & 1) {
182                         e->bits &= 0xffffffff;
183                         e->bits |= (u64) val << 32;
184                 } else {
185                         e->bits &= ~0xffffffffULL;
186                         e->bits |= (u32) val;
187                         e->fields.remote_irr = 0;
188                 }
189                 update_handled_vectors(ioapic);
190                 mask_after = e->fields.mask;
191                 if (mask_before != mask_after)
192                         kvm_fire_mask_notifiers(ioapic->kvm, KVM_IRQCHIP_IOAPIC, index, mask_after);
193                 if (e->fields.trig_mode == IOAPIC_LEVEL_TRIG
194                     && ioapic->irr & (1 << index))
195                         ioapic_service(ioapic, index);
196                 kvm_ioapic_make_eoibitmap_request(ioapic->kvm);
197                 break;
198         }
199 }
200
201 static int ioapic_deliver(struct kvm_ioapic *ioapic, int irq)
202 {
203         union kvm_ioapic_redirect_entry *entry = &ioapic->redirtbl[irq];
204         struct kvm_lapic_irq irqe;
205
206         ioapic_debug("dest=%x dest_mode=%x delivery_mode=%x "
207                      "vector=%x trig_mode=%x\n",
208                      entry->fields.dest_id, entry->fields.dest_mode,
209                      entry->fields.delivery_mode, entry->fields.vector,
210                      entry->fields.trig_mode);
211
212         irqe.dest_id = entry->fields.dest_id;
213         irqe.vector = entry->fields.vector;
214         irqe.dest_mode = entry->fields.dest_mode;
215         irqe.trig_mode = entry->fields.trig_mode;
216         irqe.delivery_mode = entry->fields.delivery_mode << 8;
217         irqe.level = 1;
218         irqe.shorthand = 0;
219
220         return kvm_irq_delivery_to_apic(ioapic->kvm, NULL, &irqe);
221 }
222
223 int kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int irq_source_id,
224                        int level)
225 {
226         u32 old_irr;
227         u32 mask = 1 << irq;
228         union kvm_ioapic_redirect_entry entry;
229         int ret, irq_level;
230
231         BUG_ON(irq < 0 || irq >= IOAPIC_NUM_PINS);
232
233         spin_lock(&ioapic->lock);
234         old_irr = ioapic->irr;
235         irq_level = __kvm_irq_line_state(&ioapic->irq_states[irq],
236                                          irq_source_id, level);
237         entry = ioapic->redirtbl[irq];
238         irq_level ^= entry.fields.polarity;
239         if (!irq_level) {
240                 ioapic->irr &= ~mask;
241                 ret = 1;
242         } else {
243                 int edge = (entry.fields.trig_mode == IOAPIC_EDGE_TRIG);
244                 ioapic->irr |= mask;
245                 if ((edge && old_irr != ioapic->irr) ||
246                     (!edge && !entry.fields.remote_irr))
247                         ret = ioapic_service(ioapic, irq);
248                 else
249                         ret = 0; /* report coalesced interrupt */
250         }
251         trace_kvm_ioapic_set_irq(entry.bits, irq, ret == 0);
252         spin_unlock(&ioapic->lock);
253
254         return ret;
255 }
256
257 void kvm_ioapic_clear_all(struct kvm_ioapic *ioapic, int irq_source_id)
258 {
259         int i;
260
261         spin_lock(&ioapic->lock);
262         for (i = 0; i < KVM_IOAPIC_NUM_PINS; i++)
263                 __clear_bit(irq_source_id, &ioapic->irq_states[i]);
264         spin_unlock(&ioapic->lock);
265 }
266
267 static void __kvm_ioapic_update_eoi(struct kvm_ioapic *ioapic, int vector,
268                                      int trigger_mode)
269 {
270         int i;
271
272         for (i = 0; i < IOAPIC_NUM_PINS; i++) {
273                 union kvm_ioapic_redirect_entry *ent = &ioapic->redirtbl[i];
274
275                 if (ent->fields.vector != vector)
276                         continue;
277
278                 /*
279                  * We are dropping lock while calling ack notifiers because ack
280                  * notifier callbacks for assigned devices call into IOAPIC
281                  * recursively. Since remote_irr is cleared only after call
282                  * to notifiers if the same vector will be delivered while lock
283                  * is dropped it will be put into irr and will be delivered
284                  * after ack notifier returns.
285                  */
286                 spin_unlock(&ioapic->lock);
287                 kvm_notify_acked_irq(ioapic->kvm, KVM_IRQCHIP_IOAPIC, i);
288                 spin_lock(&ioapic->lock);
289
290                 if (trigger_mode != IOAPIC_LEVEL_TRIG)
291                         continue;
292
293                 ASSERT(ent->fields.trig_mode == IOAPIC_LEVEL_TRIG);
294                 ent->fields.remote_irr = 0;
295                 if (!ent->fields.mask && (ioapic->irr & (1 << i)))
296                         ioapic_service(ioapic, i);
297         }
298 }
299
300 bool kvm_ioapic_handles_vector(struct kvm *kvm, int vector)
301 {
302         struct kvm_ioapic *ioapic = kvm->arch.vioapic;
303         smp_rmb();
304         return test_bit(vector, ioapic->handled_vectors);
305 }
306
307 void kvm_ioapic_update_eoi(struct kvm *kvm, int vector, int trigger_mode)
308 {
309         struct kvm_ioapic *ioapic = kvm->arch.vioapic;
310
311         spin_lock(&ioapic->lock);
312         __kvm_ioapic_update_eoi(ioapic, vector, trigger_mode);
313         spin_unlock(&ioapic->lock);
314 }
315
316 static inline struct kvm_ioapic *to_ioapic(struct kvm_io_device *dev)
317 {
318         return container_of(dev, struct kvm_ioapic, dev);
319 }
320
321 static inline int ioapic_in_range(struct kvm_ioapic *ioapic, gpa_t addr)
322 {
323         return ((addr >= ioapic->base_address &&
324                  (addr < ioapic->base_address + IOAPIC_MEM_LENGTH)));
325 }
326
327 static int ioapic_mmio_read(struct kvm_io_device *this, gpa_t addr, int len,
328                             void *val)
329 {
330         struct kvm_ioapic *ioapic = to_ioapic(this);
331         u32 result;
332         if (!ioapic_in_range(ioapic, addr))
333                 return -EOPNOTSUPP;
334
335         ioapic_debug("addr %lx\n", (unsigned long)addr);
336         ASSERT(!(addr & 0xf));  /* check alignment */
337
338         addr &= 0xff;
339         spin_lock(&ioapic->lock);
340         switch (addr) {
341         case IOAPIC_REG_SELECT:
342                 result = ioapic->ioregsel;
343                 break;
344
345         case IOAPIC_REG_WINDOW:
346                 result = ioapic_read_indirect(ioapic, addr, len);
347                 break;
348
349         default:
350                 result = 0;
351                 break;
352         }
353         spin_unlock(&ioapic->lock);
354
355         switch (len) {
356         case 8:
357                 *(u64 *) val = result;
358                 break;
359         case 1:
360         case 2:
361         case 4:
362                 memcpy(val, (char *)&result, len);
363                 break;
364         default:
365                 printk(KERN_WARNING "ioapic: wrong length %d\n", len);
366         }
367         return 0;
368 }
369
370 static int ioapic_mmio_write(struct kvm_io_device *this, gpa_t addr, int len,
371                              const void *val)
372 {
373         struct kvm_ioapic *ioapic = to_ioapic(this);
374         u32 data;
375         if (!ioapic_in_range(ioapic, addr))
376                 return -EOPNOTSUPP;
377
378         ioapic_debug("ioapic_mmio_write addr=%p len=%d val=%p\n",
379                      (void*)addr, len, val);
380         ASSERT(!(addr & 0xf));  /* check alignment */
381
382         switch (len) {
383         case 8:
384         case 4:
385                 data = *(u32 *) val;
386                 break;
387         case 2:
388                 data = *(u16 *) val;
389                 break;
390         case 1:
391                 data = *(u8  *) val;
392                 break;
393         default:
394                 printk(KERN_WARNING "ioapic: Unsupported size %d\n", len);
395                 return 0;
396         }
397
398         addr &= 0xff;
399         spin_lock(&ioapic->lock);
400         switch (addr) {
401         case IOAPIC_REG_SELECT:
402                 ioapic->ioregsel = data & 0xFF; /* 8-bit register */
403                 break;
404
405         case IOAPIC_REG_WINDOW:
406                 ioapic_write_indirect(ioapic, data);
407                 break;
408 #ifdef  CONFIG_IA64
409         case IOAPIC_REG_EOI:
410                 __kvm_ioapic_update_eoi(ioapic, data, IOAPIC_LEVEL_TRIG);
411                 break;
412 #endif
413
414         default:
415                 break;
416         }
417         spin_unlock(&ioapic->lock);
418         return 0;
419 }
420
421 void kvm_ioapic_reset(struct kvm_ioapic *ioapic)
422 {
423         int i;
424
425         for (i = 0; i < IOAPIC_NUM_PINS; i++)
426                 ioapic->redirtbl[i].fields.mask = 1;
427         ioapic->base_address = IOAPIC_DEFAULT_BASE_ADDRESS;
428         ioapic->ioregsel = 0;
429         ioapic->irr = 0;
430         ioapic->id = 0;
431         update_handled_vectors(ioapic);
432 }
433
434 static const struct kvm_io_device_ops ioapic_mmio_ops = {
435         .read     = ioapic_mmio_read,
436         .write    = ioapic_mmio_write,
437 };
438
439 int kvm_ioapic_init(struct kvm *kvm)
440 {
441         struct kvm_ioapic *ioapic;
442         int ret;
443
444         ioapic = kzalloc(sizeof(struct kvm_ioapic), GFP_KERNEL);
445         if (!ioapic)
446                 return -ENOMEM;
447         spin_lock_init(&ioapic->lock);
448         kvm->arch.vioapic = ioapic;
449         kvm_ioapic_reset(ioapic);
450         kvm_iodevice_init(&ioapic->dev, &ioapic_mmio_ops);
451         ioapic->kvm = kvm;
452         mutex_lock(&kvm->slots_lock);
453         ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, ioapic->base_address,
454                                       IOAPIC_MEM_LENGTH, &ioapic->dev);
455         mutex_unlock(&kvm->slots_lock);
456         if (ret < 0) {
457                 kvm->arch.vioapic = NULL;
458                 kfree(ioapic);
459         }
460
461         return ret;
462 }
463
464 void kvm_ioapic_destroy(struct kvm *kvm)
465 {
466         struct kvm_ioapic *ioapic = kvm->arch.vioapic;
467
468         if (ioapic) {
469                 kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS, &ioapic->dev);
470                 kvm->arch.vioapic = NULL;
471                 kfree(ioapic);
472         }
473 }
474
475 int kvm_get_ioapic(struct kvm *kvm, struct kvm_ioapic_state *state)
476 {
477         struct kvm_ioapic *ioapic = ioapic_irqchip(kvm);
478         if (!ioapic)
479                 return -EINVAL;
480
481         spin_lock(&ioapic->lock);
482         memcpy(state, ioapic, sizeof(struct kvm_ioapic_state));
483         spin_unlock(&ioapic->lock);
484         return 0;
485 }
486
487 int kvm_set_ioapic(struct kvm *kvm, struct kvm_ioapic_state *state)
488 {
489         struct kvm_ioapic *ioapic = ioapic_irqchip(kvm);
490         if (!ioapic)
491                 return -EINVAL;
492
493         spin_lock(&ioapic->lock);
494         memcpy(ioapic, state, sizeof(struct kvm_ioapic_state));
495         update_handled_vectors(ioapic);
496         kvm_ioapic_make_eoibitmap_request(kvm);
497         spin_unlock(&ioapic->lock);
498         return 0;
499 }