[ARM] 3146/1: OMAP 3b/5: Add omap24xx clock framework
[linux-3.10.git] / include / asm-arm / arch-omap / pm.h
1 /*
2  * linux/include/asm/arch-omap/pm.h
3  *
4  * Header file for OMAP Power Management Routines
5  *
6  * Author: MontaVista Software, Inc.
7  *         support@mvista.com
8  *
9  * Copyright 2002 MontaVista Software Inc.
10  *
11  * Cleanup 2004 for Linux 2.6 by Dirk Behme <dirk.behme@de.bosch.com>
12  *
13  * This program is free software; you can redistribute it and/or modify it
14  * under the terms of the GNU General Public License as published by the
15  * Free Software Foundation; either version 2 of the License, or (at your
16  * option) any later version.
17  *
18  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
19  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
20  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
21  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
24  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
25  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28  *
29  * You should have received a copy of the GNU General Public License along
30  * with this program; if not, write to the Free Software Foundation, Inc.,
31  * 675 Mass Ave, Cambridge, MA 02139, USA.
32  */
33
34 #ifndef __ASM_ARCH_OMAP_PM_H
35 #define __ASM_ARCH_OMAP_PM_H
36
37 /*
38  * ----------------------------------------------------------------------------
39  * Register and offset definitions to be used in PM assembler code
40  * ----------------------------------------------------------------------------
41  */
42 #define CLKGEN_REG_ASM_BASE             io_p2v(0xfffece00)
43 #define ARM_IDLECT1_ASM_OFFSET          0x04
44 #define ARM_IDLECT2_ASM_OFFSET          0x08
45
46 #define TCMIF_ASM_BASE                  io_p2v(0xfffecc00)
47 #define EMIFS_CONFIG_ASM_OFFSET         0x0c
48 #define EMIFF_SDRAM_CONFIG_ASM_OFFSET   0x20
49
50 /*
51  * ----------------------------------------------------------------------------
52  * Powermanagement bitmasks
53  * ----------------------------------------------------------------------------
54  */
55 #define IDLE_WAIT_CYCLES                0x00000fff
56 #define PERIPHERAL_ENABLE               0x2
57
58 #define SELF_REFRESH_MODE               0x0c000001
59 #define IDLE_EMIFS_REQUEST              0xc
60 #define MODEM_32K_EN                    0x1
61 #define PER_EN                          0x1
62
63 #define CPU_SUSPEND_SIZE                200
64 #define ULPD_LOW_PWR_EN                 0x0001
65 #define ULPD_DEEP_SLEEP_TRANSITION_EN   0x0010
66 #define ULPD_SETUP_ANALOG_CELL_3_VAL    0
67 #define ULPD_POWER_CTRL_REG_VAL         0x0219
68
69 #define DSP_IDLE_DELAY                  10
70 #define DSP_IDLE                        0x0040
71 #define DSP_RST                         0x0004
72 #define DSP_ENABLE                      0x0002
73 #define SUFFICIENT_DSP_RESET_TIME       1000
74 #define DEFAULT_MPUI_CONFIG             0x05cf
75 #define ENABLE_XORCLK                   0x2
76 #define DSP_CLOCK_ENABLE                0x2000
77 #define DSP_IDLE_MODE                   0x2
78 #define TC_IDLE_REQUEST                 (0x0000000c)
79
80 #define IRQ_LEVEL2                      (1<<0)
81 #define IRQ_KEYBOARD                    (1<<1)
82 #define IRQ_UART2                       (1<<15)
83
84 #define PDE_BIT                         0x08
85 #define PWD_EN_BIT                      0x04
86 #define EN_PERCK_BIT                    0x04
87
88 #define OMAP1510_DEEP_SLEEP_REQUEST     0x0ec7
89 #define OMAP1510_BIG_SLEEP_REQUEST      0x0cc5
90 #define OMAP1510_IDLE_LOOP_REQUEST      0x0c00
91 #define OMAP1510_IDLE_CLOCK_DOMAINS     0x2
92
93 /* Both big sleep and deep sleep use same values. Difference is in ULPD. */
94 #define OMAP1610_IDLECT1_SLEEP_VAL      0x13c7
95 #define OMAP1610_IDLECT2_SLEEP_VAL      0x09c7
96 #define OMAP1610_IDLECT3_VAL            0x3f
97 #define OMAP1610_IDLECT3_SLEEP_ORMASK   0x2c
98 #define OMAP1610_IDLECT3                0xfffece24
99 #define OMAP1610_IDLE_LOOP_REQUEST      0x0400
100
101 #if     !defined(CONFIG_ARCH_OMAP1510) && \
102         !defined(CONFIG_ARCH_OMAP16XX) && \
103         !defined(CONFIG_ARCH_OMAP24XX)
104 #error "Power management for this processor not implemented yet"
105 #endif
106
107 #ifndef __ASSEMBLER__
108 extern void omap_pm_idle(void);
109 extern void omap_pm_suspend(void);
110 extern void omap1510_cpu_suspend(unsigned short, unsigned short);
111 extern void omap1610_cpu_suspend(unsigned short, unsigned short);
112 extern void omap1510_idle_loop_suspend(void);
113 extern void omap1610_idle_loop_suspend(void);
114
115 #ifdef CONFIG_OMAP_SERIAL_WAKE
116 extern void omap_serial_wake_trigger(int enable);
117 #else
118 #define omap_serial_wake_trigger(x)     {}
119 #endif  /* CONFIG_OMAP_SERIAL_WAKE */
120
121 extern unsigned int omap1510_cpu_suspend_sz;
122 extern unsigned int omap1510_idle_loop_suspend_sz;
123 extern unsigned int omap1610_cpu_suspend_sz;
124 extern unsigned int omap1610_idle_loop_suspend_sz;
125
126 #define ARM_SAVE(x) arm_sleep_save[ARM_SLEEP_SAVE_##x] = omap_readl(x)
127 #define ARM_RESTORE(x) omap_writel((arm_sleep_save[ARM_SLEEP_SAVE_##x]), (x))
128 #define ARM_SHOW(x) arm_sleep_save[ARM_SLEEP_SAVE_##x]
129
130 #define ULPD_SAVE(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x] = omap_readw(x)
131 #define ULPD_RESTORE(x) omap_writew((ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]), (x))
132 #define ULPD_SHOW(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]
133
134 #define MPUI1510_SAVE(x) mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x] = omap_readl(x)
135 #define MPUI1510_RESTORE(x) omap_writel((mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x]), (x))
136 #define MPUI1510_SHOW(x) mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x]
137
138 #define MPUI1610_SAVE(x) mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x] = omap_readl(x)
139 #define MPUI1610_RESTORE(x) omap_writel((mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x]), (x))
140 #define MPUI1610_SHOW(x) mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x]
141
142 /*
143  * List of global OMAP registers to preserve.
144  * More ones like CP and general purpose register values are preserved
145  * with the stack pointer in sleep.S.
146  */
147
148 enum arm_save_state {
149         ARM_SLEEP_SAVE_START = 0,
150         /*
151          * MPU control registers 32 bits
152          */
153         ARM_SLEEP_SAVE_ARM_CKCTL,
154         ARM_SLEEP_SAVE_ARM_IDLECT1,
155         ARM_SLEEP_SAVE_ARM_IDLECT2,
156         ARM_SLEEP_SAVE_ARM_IDLECT3,
157         ARM_SLEEP_SAVE_ARM_EWUPCT,
158         ARM_SLEEP_SAVE_ARM_RSTCT1,
159         ARM_SLEEP_SAVE_ARM_RSTCT2,
160         ARM_SLEEP_SAVE_ARM_SYSST,
161         ARM_SLEEP_SAVE_SIZE
162 };
163
164 enum ulpd_save_state {
165         ULPD_SLEEP_SAVE_START = 0,
166         /*
167          * ULPD registers 16 bits
168          */
169         ULPD_SLEEP_SAVE_ULPD_IT_STATUS,
170         ULPD_SLEEP_SAVE_ULPD_CLOCK_CTRL,
171         ULPD_SLEEP_SAVE_ULPD_SOFT_REQ,
172         ULPD_SLEEP_SAVE_ULPD_STATUS_REQ,
173         ULPD_SLEEP_SAVE_ULPD_DPLL_CTRL,
174         ULPD_SLEEP_SAVE_ULPD_POWER_CTRL,
175         ULPD_SLEEP_SAVE_SIZE
176 };
177
178 enum mpui1510_save_state {
179         MPUI1510_SLEEP_SAVE_START = 0,
180         /*
181          * MPUI registers 32 bits
182          */
183         MPUI1510_SLEEP_SAVE_MPUI_CTRL,
184         MPUI1510_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG,
185         MPUI1510_SLEEP_SAVE_MPUI_DSP_API_CONFIG,
186         MPUI1510_SLEEP_SAVE_MPUI_DSP_STATUS,
187         MPUI1510_SLEEP_SAVE_EMIFF_SDRAM_CONFIG,
188         MPUI1510_SLEEP_SAVE_EMIFS_CONFIG,
189         MPUI1510_SLEEP_SAVE_OMAP_IH1_MIR,
190         MPUI1510_SLEEP_SAVE_OMAP_IH2_MIR,
191 #if defined(CONFIG_ARCH_OMAP1510)
192         MPUI1510_SLEEP_SAVE_SIZE
193 #else
194         MPUI1510_SLEEP_SAVE_SIZE = 0
195 #endif
196 };
197
198 enum mpui1610_save_state {
199         MPUI1610_SLEEP_SAVE_START = 0,
200         /*
201          * MPUI registers 32 bits
202          */
203         MPUI1610_SLEEP_SAVE_MPUI_CTRL,
204         MPUI1610_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG,
205         MPUI1610_SLEEP_SAVE_MPUI_DSP_API_CONFIG,
206         MPUI1610_SLEEP_SAVE_MPUI_DSP_STATUS,
207         MPUI1610_SLEEP_SAVE_EMIFF_SDRAM_CONFIG,
208         MPUI1610_SLEEP_SAVE_EMIFS_CONFIG,
209         MPUI1610_SLEEP_SAVE_OMAP_IH1_MIR,
210         MPUI1610_SLEEP_SAVE_OMAP_IH2_0_MIR,
211         MPUI1610_SLEEP_SAVE_OMAP_IH2_1_MIR,
212         MPUI1610_SLEEP_SAVE_OMAP_IH2_2_MIR,
213         MPUI1610_SLEEP_SAVE_OMAP_IH2_3_MIR,
214 #if defined(CONFIG_ARCH_OMAP16XX)
215         MPUI1610_SLEEP_SAVE_SIZE
216 #else
217         MPUI1610_SLEEP_SAVE_SIZE = 0
218 #endif
219 };
220
221 #endif /* ASSEMBLER */
222 #endif /* __ASM_ARCH_OMAP_PM_H */