[ARM] 3143/1: OMAP 4/5: Update omap include files
[linux-3.10.git] / include / asm-arm / arch-omap / pm.h
1 /*
2  * linux/include/asm/arch-omap/pm.h
3  *
4  * Header file for OMAP Power Management Routines
5  *
6  * Author: MontaVista Software, Inc.
7  *         support@mvista.com
8  *
9  * Copyright 2002 MontaVista Software Inc.
10  *
11  * Cleanup 2004 for Linux 2.6 by Dirk Behme <dirk.behme@de.bosch.com>
12  *
13  * This program is free software; you can redistribute it and/or modify it
14  * under the terms of the GNU General Public License as published by the
15  * Free Software Foundation; either version 2 of the License, or (at your
16  * option) any later version.
17  *
18  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
19  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
20  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
21  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
24  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
25  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28  *
29  * You should have received a copy of the GNU General Public License along
30  * with this program; if not, write to the Free Software Foundation, Inc.,
31  * 675 Mass Ave, Cambridge, MA 02139, USA.
32  */
33
34 #ifndef __ASM_ARCH_OMAP_PM_H
35 #define __ASM_ARCH_OMAP_PM_H
36
37 /*
38  * ----------------------------------------------------------------------------
39  * Register and offset definitions to be used in PM assembler code
40  * ----------------------------------------------------------------------------
41  */
42 #define CLKGEN_REG_ASM_BASE             io_p2v(0xfffece00)
43 #define ARM_IDLECT1_ASM_OFFSET          0x04
44 #define ARM_IDLECT2_ASM_OFFSET          0x08
45
46 #define TCMIF_ASM_BASE                  io_p2v(0xfffecc00)
47 #define EMIFS_CONFIG_ASM_OFFSET         0x0c
48 #define EMIFF_SDRAM_CONFIG_ASM_OFFSET   0x20
49
50 /*
51  * ----------------------------------------------------------------------------
52  * Powermanagement bitmasks
53  * ----------------------------------------------------------------------------
54  */
55 #define IDLE_WAIT_CYCLES                0x00000fff
56 #define PERIPHERAL_ENABLE               0x2
57
58 #define SELF_REFRESH_MODE               0x0c000001
59 #define IDLE_EMIFS_REQUEST              0xc
60 #define MODEM_32K_EN                    0x1
61 #define PER_EN                          0x1
62
63 #define CPU_SUSPEND_SIZE                200
64 #define ULPD_LOW_PWR_EN                 0x0001
65 #define ULPD_DEEP_SLEEP_TRANSITION_EN   0x0010
66 #define ULPD_SETUP_ANALOG_CELL_3_VAL    0
67 #define ULPD_POWER_CTRL_REG_VAL         0x0219
68
69 #define DSP_IDLE_DELAY                  10
70 #define DSP_IDLE                        0x0040
71 #define DSP_RST                         0x0004
72 #define DSP_ENABLE                      0x0002
73 #define SUFFICIENT_DSP_RESET_TIME       1000
74 #define DEFAULT_MPUI_CONFIG             0x05cf
75 #define ENABLE_XORCLK                   0x2
76 #define DSP_CLOCK_ENABLE                0x2000
77 #define DSP_IDLE_MODE                   0x2
78 #define TC_IDLE_REQUEST                 (0x0000000c)
79
80 #define IRQ_LEVEL2                      (1<<0)
81 #define IRQ_KEYBOARD                    (1<<1)
82 #define IRQ_UART2                       (1<<15)
83
84 #define PDE_BIT                         0x08
85 #define PWD_EN_BIT                      0x04
86 #define EN_PERCK_BIT                    0x04
87
88 #define OMAP1510_DEEP_SLEEP_REQUEST     0x0ec7
89 #define OMAP1510_BIG_SLEEP_REQUEST      0x0cc5
90 #define OMAP1510_IDLE_LOOP_REQUEST      0x0c00
91 #define OMAP1510_IDLE_CLOCK_DOMAINS     0x2
92
93 /* Both big sleep and deep sleep use same values. Difference is in ULPD. */
94 #define OMAP1610_IDLECT1_SLEEP_VAL      0x13c7
95 #define OMAP1610_IDLECT2_SLEEP_VAL      0x09c7
96 #define OMAP1610_IDLECT3_VAL            0x3f
97 #define OMAP1610_IDLECT3_SLEEP_ORMASK   0x2c
98 #define OMAP1610_IDLECT3                0xfffece24
99 #define OMAP1610_IDLE_LOOP_REQUEST      0x0400
100
101 #define OMAP730_IDLECT1_SLEEP_VAL       0x16c7
102 #define OMAP730_IDLECT2_SLEEP_VAL       0x09c7
103 #define OMAP730_IDLECT3_VAL             0x3f
104 #define OMAP730_IDLECT3         0xfffece24
105 #define OMAP730_IDLE_LOOP_REQUEST       0x0C00
106
107 #if     !defined(CONFIG_ARCH_OMAP730) && \
108         !defined(CONFIG_ARCH_OMAP15XX) && \
109         !defined(CONFIG_ARCH_OMAP16XX) && \
110         !defined(CONFIG_ARCH_OMAP24XX)
111 #error "Power management for this processor not implemented yet"
112 #endif
113
114 #ifndef __ASSEMBLER__
115 extern void omap_pm_idle(void);
116 extern void omap_pm_suspend(void);
117 extern void omap730_cpu_suspend(unsigned short, unsigned short);
118 extern void omap1510_cpu_suspend(unsigned short, unsigned short);
119 extern void omap1610_cpu_suspend(unsigned short, unsigned short);
120 extern void omap730_idle_loop_suspend(void);
121 extern void omap1510_idle_loop_suspend(void);
122 extern void omap1610_idle_loop_suspend(void);
123
124 #ifdef CONFIG_OMAP_SERIAL_WAKE
125 extern void omap_serial_wake_trigger(int enable);
126 #else
127 #define omap_serial_wake_trigger(x)     {}
128 #endif  /* CONFIG_OMAP_SERIAL_WAKE */
129
130 extern unsigned int omap730_cpu_suspend_sz;
131 extern unsigned int omap730_idle_loop_suspend_sz;
132 extern unsigned int omap1510_cpu_suspend_sz;
133 extern unsigned int omap1510_idle_loop_suspend_sz;
134 extern unsigned int omap1610_cpu_suspend_sz;
135 extern unsigned int omap1610_idle_loop_suspend_sz;
136
137 #define ARM_SAVE(x) arm_sleep_save[ARM_SLEEP_SAVE_##x] = omap_readl(x)
138 #define ARM_RESTORE(x) omap_writel((arm_sleep_save[ARM_SLEEP_SAVE_##x]), (x))
139 #define ARM_SHOW(x) arm_sleep_save[ARM_SLEEP_SAVE_##x]
140
141 #define ULPD_SAVE(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x] = omap_readw(x)
142 #define ULPD_RESTORE(x) omap_writew((ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]), (x))
143 #define ULPD_SHOW(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]
144
145 #define MPUI730_SAVE(x) mpui730_sleep_save[MPUI730_SLEEP_SAVE_##x] = omap_readl(x)
146 #define MPUI730_RESTORE(x) omap_writel((mpui730_sleep_save[MPUI730_SLEEP_SAVE_##x]), (x))
147 #define MPUI730_SHOW(x) mpui730_sleep_save[MPUI730_SLEEP_SAVE_##x]
148
149 #define MPUI1510_SAVE(x) mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x] = omap_readl(x)
150 #define MPUI1510_RESTORE(x) omap_writel((mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x]), (x))
151 #define MPUI1510_SHOW(x) mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x]
152
153 #define MPUI1610_SAVE(x) mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x] = omap_readl(x)
154 #define MPUI1610_RESTORE(x) omap_writel((mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x]), (x))
155 #define MPUI1610_SHOW(x) mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x]
156
157 /*
158  * List of global OMAP registers to preserve.
159  * More ones like CP and general purpose register values are preserved
160  * with the stack pointer in sleep.S.
161  */
162
163 enum arm_save_state {
164         ARM_SLEEP_SAVE_START = 0,
165         /*
166          * MPU control registers 32 bits
167          */
168         ARM_SLEEP_SAVE_ARM_CKCTL,
169         ARM_SLEEP_SAVE_ARM_IDLECT1,
170         ARM_SLEEP_SAVE_ARM_IDLECT2,
171         ARM_SLEEP_SAVE_ARM_IDLECT3,
172         ARM_SLEEP_SAVE_ARM_EWUPCT,
173         ARM_SLEEP_SAVE_ARM_RSTCT1,
174         ARM_SLEEP_SAVE_ARM_RSTCT2,
175         ARM_SLEEP_SAVE_ARM_SYSST,
176         ARM_SLEEP_SAVE_SIZE
177 };
178
179 enum ulpd_save_state {
180         ULPD_SLEEP_SAVE_START = 0,
181         /*
182          * ULPD registers 16 bits
183          */
184         ULPD_SLEEP_SAVE_ULPD_IT_STATUS,
185         ULPD_SLEEP_SAVE_ULPD_CLOCK_CTRL,
186         ULPD_SLEEP_SAVE_ULPD_SOFT_REQ,
187         ULPD_SLEEP_SAVE_ULPD_STATUS_REQ,
188         ULPD_SLEEP_SAVE_ULPD_DPLL_CTRL,
189         ULPD_SLEEP_SAVE_ULPD_POWER_CTRL,
190         ULPD_SLEEP_SAVE_SIZE
191 };
192
193 enum mpui1510_save_state {
194         MPUI1510_SLEEP_SAVE_START = 0,
195         /*
196          * MPUI registers 32 bits
197          */
198         MPUI1510_SLEEP_SAVE_MPUI_CTRL,
199         MPUI1510_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG,
200         MPUI1510_SLEEP_SAVE_MPUI_DSP_API_CONFIG,
201         MPUI1510_SLEEP_SAVE_MPUI_DSP_STATUS,
202         MPUI1510_SLEEP_SAVE_EMIFF_SDRAM_CONFIG,
203         MPUI1510_SLEEP_SAVE_EMIFS_CONFIG,
204         MPUI1510_SLEEP_SAVE_OMAP_IH1_MIR,
205         MPUI1510_SLEEP_SAVE_OMAP_IH2_MIR,
206 #if defined(CONFIG_ARCH_OMAP15XX)
207         MPUI1510_SLEEP_SAVE_SIZE
208 #else
209         MPUI1510_SLEEP_SAVE_SIZE = 0
210 #endif
211 };
212
213 enum mpui730_save_state {
214         MPUI730_SLEEP_SAVE_START = 0,
215         /*
216          * MPUI registers 32 bits
217          */
218         MPUI730_SLEEP_SAVE_MPUI_CTRL,
219         MPUI730_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG,
220         MPUI730_SLEEP_SAVE_MPUI_DSP_API_CONFIG,
221         MPUI730_SLEEP_SAVE_MPUI_DSP_STATUS,
222         MPUI730_SLEEP_SAVE_EMIFF_SDRAM_CONFIG,
223         MPUI730_SLEEP_SAVE_EMIFS_CONFIG,
224         MPUI730_SLEEP_SAVE_OMAP_IH1_MIR,
225         MPUI730_SLEEP_SAVE_OMAP_IH2_0_MIR,
226         MPUI730_SLEEP_SAVE_OMAP_IH2_1_MIR,
227 #if defined(CONFIG_ARCH_OMAP730)
228         MPUI730_SLEEP_SAVE_SIZE
229 #else
230         MPUI730_SLEEP_SAVE_SIZE = 0
231 #endif
232 };
233
234 enum mpui1610_save_state {
235         MPUI1610_SLEEP_SAVE_START = 0,
236         /*
237          * MPUI registers 32 bits
238          */
239         MPUI1610_SLEEP_SAVE_MPUI_CTRL,
240         MPUI1610_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG,
241         MPUI1610_SLEEP_SAVE_MPUI_DSP_API_CONFIG,
242         MPUI1610_SLEEP_SAVE_MPUI_DSP_STATUS,
243         MPUI1610_SLEEP_SAVE_EMIFF_SDRAM_CONFIG,
244         MPUI1610_SLEEP_SAVE_EMIFS_CONFIG,
245         MPUI1610_SLEEP_SAVE_OMAP_IH1_MIR,
246         MPUI1610_SLEEP_SAVE_OMAP_IH2_0_MIR,
247         MPUI1610_SLEEP_SAVE_OMAP_IH2_1_MIR,
248         MPUI1610_SLEEP_SAVE_OMAP_IH2_2_MIR,
249         MPUI1610_SLEEP_SAVE_OMAP_IH2_3_MIR,
250 #if defined(CONFIG_ARCH_OMAP16XX)
251         MPUI1610_SLEEP_SAVE_SIZE
252 #else
253         MPUI1610_SLEEP_SAVE_SIZE = 0
254 #endif
255 };
256
257 #endif /* ASSEMBLER */
258 #endif /* __ASM_ARCH_OMAP_PM_H */