13415a9aab06431540e6e045a0d7988c7c711154
[linux-3.10.git] / include / asm-arm / arch-omap / mux.h
1 /*
2  * linux/include/asm-arm/arch-omap/mux.h
3  *
4  * Table of the Omap register configurations for the FUNC_MUX and
5  * PULL_DWN combinations.
6  *
7  * Copyright (C) 2003 - 2005 Nokia Corporation
8  *
9  * Written by Tony Lindgren <tony.lindgren@nokia.com>
10  *
11  * This program is free software; you can redistribute it and/or modify
12  * it under the terms of the GNU General Public License as published by
13  * the Free Software Foundation; either version 2 of the License, or
14  * (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software
23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24  *
25  * NOTE: Please use the following naming style for new pin entries.
26  *       For example, W8_1610_MMC2_DAT0, where:
27  *       - W8        = ball
28  *       - 1610      = 1510 or 1610, none if common for both 1510 and 1610
29  *       - MMC2_DAT0 = function
30  *
31  * Change log:
32  *   Added entry for the I2C interface. (02Feb 2004)
33  *   Copyright (C) 2004 Texas Instruments
34  *
35  *   Added entry for the keypad and uwire CS1. (09Mar 2004)
36  *   Copyright (C) 2004 Texas Instruments
37  *
38  */
39
40 #ifndef __ASM_ARCH_MUX_H
41 #define __ASM_ARCH_MUX_H
42
43 #define PU_PD_SEL_NA            0       /* No pu_pd reg available */
44 #define PULL_DWN_CTRL_NA        0       /* No pull-down control needed */
45
46 #ifdef  CONFIG_OMAP_MUX_DEBUG
47 #define MUX_REG(reg, mode_offset, mode) .mux_reg_name = "FUNC_MUX_CTRL_"#reg, \
48                                         .mux_reg = FUNC_MUX_CTRL_##reg, \
49                                         .mask_offset = mode_offset, \
50                                         .mask = mode,
51
52 #define PULL_REG(reg, bit, status)      .pull_name = "PULL_DWN_CTRL_"#reg, \
53                                         .pull_reg = PULL_DWN_CTRL_##reg, \
54                                         .pull_bit = bit, \
55                                         .pull_val = status,
56
57 #define PU_PD_REG(reg, status)          .pu_pd_name = "PU_PD_SEL_"#reg, \
58                                         .pu_pd_reg = PU_PD_SEL_##reg, \
59                                         .pu_pd_val = status,
60
61 #define MUX_REG_730(reg, mode_offset, mode) .mux_reg_name = "OMAP730_IO_CONF_"#reg, \
62                                         .mux_reg = OMAP730_IO_CONF_##reg, \
63                                         .mask_offset = mode_offset, \
64                                         .mask = mode,
65
66 #define PULL_REG_730(reg, bit, status)  .pull_name = "OMAP730_IO_CONF_"#reg, \
67                                         .pull_reg = OMAP730_IO_CONF_##reg, \
68                                         .pull_bit = bit, \
69                                         .pull_val = status,
70
71 #else
72
73 #define MUX_REG(reg, mode_offset, mode) .mux_reg = FUNC_MUX_CTRL_##reg, \
74                                         .mask_offset = mode_offset, \
75                                         .mask = mode,
76
77 #define PULL_REG(reg, bit, status)      .pull_reg = PULL_DWN_CTRL_##reg, \
78                                         .pull_bit = bit, \
79                                         .pull_val = status,
80
81 #define PU_PD_REG(reg, status)          .pu_pd_reg = PU_PD_SEL_##reg, \
82                                         .pu_pd_val = status,
83
84 #define MUX_REG_730(reg, mode_offset, mode) \
85                                         .mux_reg = OMAP730_IO_CONF_##reg, \
86                                         .mask_offset = mode_offset, \
87                                         .mask = mode,
88
89 #define PULL_REG_730(reg, bit, status)  .pull_reg = OMAP730_IO_CONF_##reg, \
90                                         .pull_bit = bit, \
91                                         .pull_val = status,
92
93 #endif /* CONFIG_OMAP_MUX_DEBUG */
94
95 #define MUX_CFG(desc, mux_reg, mode_offset, mode,       \
96                 pull_reg, pull_bit, pull_status,        \
97                 pu_pd_reg, pu_pd_status, debug_status)  \
98 {                                                       \
99         .name =  desc,                                  \
100         .debug = debug_status,                          \
101         MUX_REG(mux_reg, mode_offset, mode)             \
102         PULL_REG(pull_reg, pull_bit, pull_status)       \
103         PU_PD_REG(pu_pd_reg, pu_pd_status)              \
104 },
105
106
107 /*
108  * OMAP730 has a slightly different config for the pin mux.
109  * - config regs are the OMAP730_IO_CONF_x regs (see omap730.h) regs and
110  *   not the FUNC_MUX_CTRL_x regs from hardware.h
111  * - for pull-up/down, only has one enable bit which is is in the same register
112  *   as mux config
113  */
114 #define MUX_CFG_730(desc, mux_reg, mode_offset, mode,   \
115                    pull_reg, pull_bit, pull_status,     \
116                    pu_pd_reg, pu_pd_status, debug_status)\
117 {                                                       \
118         .name =  desc,                                  \
119         .debug = debug_status,                          \
120         MUX_REG_730(mux_reg, mode_offset, mode)         \
121         PULL_REG_730(mux_reg, pull_bit, pull_status)    \
122         PU_PD_REG(pu_pd_reg, pu_pd_status)              \
123 },
124
125 #define MUX_CFG_24XX(desc, reg_offset, mode,                    \
126                                 pull_en, pull_mode, dbg)        \
127 {                                                               \
128         .name           = desc,                                 \
129         .debug          = dbg,                                  \
130         .mux_reg        = reg_offset,                           \
131         .mask           = mode,                                 \
132         .pull_val       = pull_en,                              \
133         .pu_pd_val      = pull_mode,                            \
134 },
135
136
137 #define PULL_DISABLED   0
138 #define PULL_ENABLED    1
139
140 #define PULL_DOWN       0
141 #define PULL_UP         1
142
143 struct pin_config {
144         char *name;
145         unsigned char busy;
146         unsigned char debug;
147
148         const char *mux_reg_name;
149         const unsigned int mux_reg;
150         const unsigned char mask_offset;
151         const unsigned char mask;
152
153         const char *pull_name;
154         const unsigned int pull_reg;
155         const unsigned char pull_val;
156         const unsigned char pull_bit;
157
158         const char *pu_pd_name;
159         const unsigned int pu_pd_reg;
160         const unsigned char pu_pd_val;
161 };
162
163 enum omap730_index {
164         /* OMAP 730 keyboard */
165         E2_730_KBR0,
166         J7_730_KBR1,
167         E1_730_KBR2,
168         F3_730_KBR3,
169         D2_730_KBR4,
170         C2_730_KBC0,
171         D3_730_KBC1,
172         E4_730_KBC2,
173         F4_730_KBC3,
174         E3_730_KBC4,
175 };
176
177 enum omap1xxx_index {
178         /* UART1 (BT_UART_GATING)*/
179         UART1_TX = 0,
180         UART1_RTS,
181
182         /* UART2 (COM_UART_GATING)*/
183         UART2_TX,
184         UART2_RX,
185         UART2_CTS,
186         UART2_RTS,
187
188         /* UART3 (GIGA_UART_GATING) */
189         UART3_TX,
190         UART3_RX,
191         UART3_CTS,
192         UART3_RTS,
193         UART3_CLKREQ,
194         UART3_BCLK,     /* 12MHz clock out */
195         Y15_1610_UART3_RTS,
196
197         /* PWT & PWL */
198         PWT,
199         PWL,
200
201         /* USB master generic */
202         R18_USB_VBUS,
203         R18_1510_USB_GPIO0,
204         W4_USB_PUEN,
205         W4_USB_CLKO,
206         W4_USB_HIGHZ,
207         W4_GPIO58,
208
209         /* USB1 master */
210         USB1_SUSP,
211         USB1_SEO,
212         W13_1610_USB1_SE0,
213         USB1_TXEN,
214         USB1_TXD,
215         USB1_VP,
216         USB1_VM,
217         USB1_RCV,
218         USB1_SPEED,
219         R13_1610_USB1_SPEED,
220         R13_1710_USB1_SE0,
221
222         /* USB2 master */
223         USB2_SUSP,
224         USB2_VP,
225         USB2_TXEN,
226         USB2_VM,
227         USB2_RCV,
228         USB2_SEO,
229         USB2_TXD,
230
231         /* OMAP-1510 GPIO */
232         R18_1510_GPIO0,
233         R19_1510_GPIO1,
234         M14_1510_GPIO2,
235
236         /* OMAP1610 GPIO */
237         P18_1610_GPIO3,
238         Y15_1610_GPIO17,
239
240         /* OMAP-1710 GPIO */
241         R18_1710_GPIO0,
242         V2_1710_GPIO10,
243         N21_1710_GPIO14,
244         W15_1710_GPIO40,
245
246         /* MPUIO */
247         MPUIO2,
248         N15_1610_MPUIO2,
249         MPUIO4,
250         MPUIO5,
251         T20_1610_MPUIO5,
252         W11_1610_MPUIO6,
253         V10_1610_MPUIO7,
254         W11_1610_MPUIO9,
255         V10_1610_MPUIO10,
256         W10_1610_MPUIO11,
257         E20_1610_MPUIO13,
258         U20_1610_MPUIO14,
259         E19_1610_MPUIO15,
260
261         /* MCBSP2 */
262         MCBSP2_CLKR,
263         MCBSP2_CLKX,
264         MCBSP2_DR,
265         MCBSP2_DX,
266         MCBSP2_FSR,
267         MCBSP2_FSX,
268
269         /* MCBSP3 */
270         MCBSP3_CLKX,
271
272         /* Misc ballouts */
273         BALLOUT_V8_ARMIO3,
274         N20_HDQ,
275
276         /* OMAP-1610 MMC2 */
277         W8_1610_MMC2_DAT0,
278         V8_1610_MMC2_DAT1,
279         W15_1610_MMC2_DAT2,
280         R10_1610_MMC2_DAT3,
281         Y10_1610_MMC2_CLK,
282         Y8_1610_MMC2_CMD,
283         V9_1610_MMC2_CMDDIR,
284         V5_1610_MMC2_DATDIR0,
285         W19_1610_MMC2_DATDIR1,
286         R18_1610_MMC2_CLKIN,
287
288         /* OMAP-1610 External Trace Interface */
289         M19_1610_ETM_PSTAT0,
290         L15_1610_ETM_PSTAT1,
291         L18_1610_ETM_PSTAT2,
292         L19_1610_ETM_D0,
293         J19_1610_ETM_D6,
294         J18_1610_ETM_D7,
295
296         /* OMAP16XX GPIO */
297         P20_1610_GPIO4,
298         V9_1610_GPIO7,
299         W8_1610_GPIO9,
300         N20_1610_GPIO11,
301         N19_1610_GPIO13,
302         P10_1610_GPIO22,
303         V5_1610_GPIO24,
304         AA20_1610_GPIO_41,
305         W19_1610_GPIO48,
306         M7_1610_GPIO62,
307         V14_16XX_GPIO37,
308         R9_16XX_GPIO18,
309         L14_16XX_GPIO49,
310
311         /* OMAP-1610 uWire */
312         V19_1610_UWIRE_SCLK,
313         U18_1610_UWIRE_SDI,
314         W21_1610_UWIRE_SDO,
315         N14_1610_UWIRE_CS0,
316         P15_1610_UWIRE_CS3,
317         N15_1610_UWIRE_CS1,
318
319         /* OMAP-1610 Flash */
320         L3_1610_FLASH_CS2B_OE,
321         M8_1610_FLASH_CS2B_WE,
322
323         /* First MMC */
324         MMC_CMD,
325         MMC_DAT1,
326         MMC_DAT2,
327         MMC_DAT0,
328         MMC_CLK,
329         MMC_DAT3,
330
331         /* OMAP-1710 MMC CMDDIR and DATDIR0 */
332         M15_1710_MMC_CLKI,
333         P19_1710_MMC_CMDDIR,
334         P20_1710_MMC_DATDIR0,
335
336         /* OMAP-1610 USB0 alternate pin configuration */
337         W9_USB0_TXEN,
338         AA9_USB0_VP,
339         Y5_USB0_RCV,
340         R9_USB0_VM,
341         V6_USB0_TXD,
342         W5_USB0_SE0,
343         V9_USB0_SPEED,
344         V9_USB0_SUSP,
345
346         /* USB2 */
347         W9_USB2_TXEN,
348         AA9_USB2_VP,
349         Y5_USB2_RCV,
350         R9_USB2_VM,
351         V6_USB2_TXD,
352         W5_USB2_SE0,
353
354         /* 16XX UART */
355         R13_1610_UART1_TX,
356         V14_16XX_UART1_RX,
357         R14_1610_UART1_CTS,
358         AA15_1610_UART1_RTS,
359         R9_16XX_UART2_RX,
360         L14_16XX_UART3_RX,
361
362         /* I2C OMAP-1610 */
363         I2C_SCL,
364         I2C_SDA,
365
366         /* Keypad */
367         F18_1610_KBC0,
368         D20_1610_KBC1,
369         D19_1610_KBC2,
370         E18_1610_KBC3,
371         C21_1610_KBC4,
372         G18_1610_KBR0,
373         F19_1610_KBR1,
374         H14_1610_KBR2,
375         E20_1610_KBR3,
376         E19_1610_KBR4,
377         N19_1610_KBR5,
378
379         /* Power management */
380         T20_1610_LOW_PWR,
381
382         /* MCLK Settings */
383         V5_1710_MCLK_ON,
384         V5_1710_MCLK_OFF,
385         R10_1610_MCLK_ON,
386         R10_1610_MCLK_OFF,
387
388         /* CompactFlash controller */
389         P11_1610_CF_CD2,
390         R11_1610_CF_IOIS16,
391         V10_1610_CF_IREQ,
392         W10_1610_CF_RESET,
393         W11_1610_CF_CD1,
394 };
395
396 enum omap24xx_index {
397         /* 24xx I2C */
398         M19_24XX_I2C1_SCL,
399         L15_24XX_I2C1_SDA,
400         J15_24XX_I2C2_SCL,
401         H19_24XX_I2C2_SDA,
402
403         /* 24xx Menelaus interrupt */
404         W19_24XX_SYS_NIRQ,
405
406         /* 24xx GPIO */
407         Y20_24XX_GPIO60,
408         M15_24XX_GPIO92,
409 };
410
411 #ifdef  CONFIG_OMAP_MUX
412 /* setup pin muxing in Linux */
413 extern int omap1_mux_init(void);
414 extern int omap2_mux_init(void);
415 extern int omap_mux_register(struct pin_config * pins, unsigned long size);
416 extern int omap_cfg_reg(unsigned long reg_cfg);
417 #else
418 /* boot loader does it all (no warnings from CONFIG_OMAP_MUX_WARNINGS) */
419 static inline int omap1_mux_init(void) { return 0; }
420 static inline int omap2_mux_init(void) { return 0; }
421 static inline int omap_cfg_reg(unsigned long reg_cfg) { return 0; }
422 #endif
423
424 #endif