Merge branches 'dma-omap', 'dma-pl08x' and 'dma-sa11x0' into dmaengine
[linux-3.10.git] / drivers / spi / spi-omap2-mcspi.c
1 /*
2  * OMAP2 McSPI controller driver
3  *
4  * Copyright (C) 2005, 2006 Nokia Corporation
5  * Author:      Samuel Ortiz <samuel.ortiz@nokia.com> and
6  *              Juha Yrj�l� <juha.yrjola@nokia.com>
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21  *
22  */
23
24 #include <linux/kernel.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
27 #include <linux/module.h>
28 #include <linux/device.h>
29 #include <linux/delay.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/dmaengine.h>
32 #include <linux/omap-dma.h>
33 #include <linux/platform_device.h>
34 #include <linux/err.h>
35 #include <linux/clk.h>
36 #include <linux/io.h>
37 #include <linux/slab.h>
38 #include <linux/pm_runtime.h>
39 #include <linux/of.h>
40 #include <linux/of_device.h>
41
42 #include <linux/spi/spi.h>
43
44 #include <plat/clock.h>
45 #include <plat/mcspi.h>
46
47 #define OMAP2_MCSPI_MAX_FREQ            48000000
48 #define SPI_AUTOSUSPEND_TIMEOUT         2000
49
50 #define OMAP2_MCSPI_REVISION            0x00
51 #define OMAP2_MCSPI_SYSSTATUS           0x14
52 #define OMAP2_MCSPI_IRQSTATUS           0x18
53 #define OMAP2_MCSPI_IRQENABLE           0x1c
54 #define OMAP2_MCSPI_WAKEUPENABLE        0x20
55 #define OMAP2_MCSPI_SYST                0x24
56 #define OMAP2_MCSPI_MODULCTRL           0x28
57
58 /* per-channel banks, 0x14 bytes each, first is: */
59 #define OMAP2_MCSPI_CHCONF0             0x2c
60 #define OMAP2_MCSPI_CHSTAT0             0x30
61 #define OMAP2_MCSPI_CHCTRL0             0x34
62 #define OMAP2_MCSPI_TX0                 0x38
63 #define OMAP2_MCSPI_RX0                 0x3c
64
65 /* per-register bitmasks: */
66
67 #define OMAP2_MCSPI_MODULCTRL_SINGLE    BIT(0)
68 #define OMAP2_MCSPI_MODULCTRL_MS        BIT(2)
69 #define OMAP2_MCSPI_MODULCTRL_STEST     BIT(3)
70
71 #define OMAP2_MCSPI_CHCONF_PHA          BIT(0)
72 #define OMAP2_MCSPI_CHCONF_POL          BIT(1)
73 #define OMAP2_MCSPI_CHCONF_CLKD_MASK    (0x0f << 2)
74 #define OMAP2_MCSPI_CHCONF_EPOL         BIT(6)
75 #define OMAP2_MCSPI_CHCONF_WL_MASK      (0x1f << 7)
76 #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY  BIT(12)
77 #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY  BIT(13)
78 #define OMAP2_MCSPI_CHCONF_TRM_MASK     (0x03 << 12)
79 #define OMAP2_MCSPI_CHCONF_DMAW         BIT(14)
80 #define OMAP2_MCSPI_CHCONF_DMAR         BIT(15)
81 #define OMAP2_MCSPI_CHCONF_DPE0         BIT(16)
82 #define OMAP2_MCSPI_CHCONF_DPE1         BIT(17)
83 #define OMAP2_MCSPI_CHCONF_IS           BIT(18)
84 #define OMAP2_MCSPI_CHCONF_TURBO        BIT(19)
85 #define OMAP2_MCSPI_CHCONF_FORCE        BIT(20)
86
87 #define OMAP2_MCSPI_CHSTAT_RXS          BIT(0)
88 #define OMAP2_MCSPI_CHSTAT_TXS          BIT(1)
89 #define OMAP2_MCSPI_CHSTAT_EOT          BIT(2)
90
91 #define OMAP2_MCSPI_CHCTRL_EN           BIT(0)
92
93 #define OMAP2_MCSPI_WAKEUPENABLE_WKEN   BIT(0)
94
95 /* We have 2 DMA channels per CS, one for RX and one for TX */
96 struct omap2_mcspi_dma {
97         struct dma_chan *dma_tx;
98         struct dma_chan *dma_rx;
99
100         int dma_tx_sync_dev;
101         int dma_rx_sync_dev;
102
103         struct completion dma_tx_completion;
104         struct completion dma_rx_completion;
105 };
106
107 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
108  * cache operations; better heuristics consider wordsize and bitrate.
109  */
110 #define DMA_MIN_BYTES                   160
111
112
113 /*
114  * Used for context save and restore, structure members to be updated whenever
115  * corresponding registers are modified.
116  */
117 struct omap2_mcspi_regs {
118         u32 modulctrl;
119         u32 wakeupenable;
120         struct list_head cs;
121 };
122
123 struct omap2_mcspi {
124         struct spi_master       *master;
125         /* Virtual base address of the controller */
126         void __iomem            *base;
127         unsigned long           phys;
128         /* SPI1 has 4 channels, while SPI2 has 2 */
129         struct omap2_mcspi_dma  *dma_channels;
130         struct device           *dev;
131         struct omap2_mcspi_regs ctx;
132 };
133
134 struct omap2_mcspi_cs {
135         void __iomem            *base;
136         unsigned long           phys;
137         int                     word_len;
138         struct list_head        node;
139         /* Context save and restore shadow register */
140         u32                     chconf0;
141 };
142
143 #define MOD_REG_BIT(val, mask, set) do { \
144         if (set) \
145                 val |= mask; \
146         else \
147                 val &= ~mask; \
148 } while (0)
149
150 static inline void mcspi_write_reg(struct spi_master *master,
151                 int idx, u32 val)
152 {
153         struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
154
155         __raw_writel(val, mcspi->base + idx);
156 }
157
158 static inline u32 mcspi_read_reg(struct spi_master *master, int idx)
159 {
160         struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
161
162         return __raw_readl(mcspi->base + idx);
163 }
164
165 static inline void mcspi_write_cs_reg(const struct spi_device *spi,
166                 int idx, u32 val)
167 {
168         struct omap2_mcspi_cs   *cs = spi->controller_state;
169
170         __raw_writel(val, cs->base +  idx);
171 }
172
173 static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx)
174 {
175         struct omap2_mcspi_cs   *cs = spi->controller_state;
176
177         return __raw_readl(cs->base + idx);
178 }
179
180 static inline u32 mcspi_cached_chconf0(const struct spi_device *spi)
181 {
182         struct omap2_mcspi_cs *cs = spi->controller_state;
183
184         return cs->chconf0;
185 }
186
187 static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val)
188 {
189         struct omap2_mcspi_cs *cs = spi->controller_state;
190
191         cs->chconf0 = val;
192         mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val);
193         mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
194 }
195
196 static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
197                 int is_read, int enable)
198 {
199         u32 l, rw;
200
201         l = mcspi_cached_chconf0(spi);
202
203         if (is_read) /* 1 is read, 0 write */
204                 rw = OMAP2_MCSPI_CHCONF_DMAR;
205         else
206                 rw = OMAP2_MCSPI_CHCONF_DMAW;
207
208         MOD_REG_BIT(l, rw, enable);
209         mcspi_write_chconf0(spi, l);
210 }
211
212 static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
213 {
214         u32 l;
215
216         l = enable ? OMAP2_MCSPI_CHCTRL_EN : 0;
217         mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, l);
218         /* Flash post-writes */
219         mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0);
220 }
221
222 static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active)
223 {
224         u32 l;
225
226         l = mcspi_cached_chconf0(spi);
227         MOD_REG_BIT(l, OMAP2_MCSPI_CHCONF_FORCE, cs_active);
228         mcspi_write_chconf0(spi, l);
229 }
230
231 static void omap2_mcspi_set_master_mode(struct spi_master *master)
232 {
233         struct omap2_mcspi      *mcspi = spi_master_get_devdata(master);
234         struct omap2_mcspi_regs *ctx = &mcspi->ctx;
235         u32 l;
236
237         /*
238          * Setup when switching from (reset default) slave mode
239          * to single-channel master mode
240          */
241         l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
242         MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_STEST, 0);
243         MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_MS, 0);
244         MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_SINGLE, 1);
245         mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
246
247         ctx->modulctrl = l;
248 }
249
250 static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi)
251 {
252         struct spi_master       *spi_cntrl = mcspi->master;
253         struct omap2_mcspi_regs *ctx = &mcspi->ctx;
254         struct omap2_mcspi_cs   *cs;
255
256         /* McSPI: context restore */
257         mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl);
258         mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable);
259
260         list_for_each_entry(cs, &ctx->cs, node)
261                 __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
262 }
263 static void omap2_mcspi_disable_clocks(struct omap2_mcspi *mcspi)
264 {
265         pm_runtime_mark_last_busy(mcspi->dev);
266         pm_runtime_put_autosuspend(mcspi->dev);
267 }
268
269 static int omap2_mcspi_enable_clocks(struct omap2_mcspi *mcspi)
270 {
271         return pm_runtime_get_sync(mcspi->dev);
272 }
273
274 static int omap2_prepare_transfer(struct spi_master *master)
275 {
276         struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
277
278         pm_runtime_get_sync(mcspi->dev);
279         return 0;
280 }
281
282 static int omap2_unprepare_transfer(struct spi_master *master)
283 {
284         struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
285
286         pm_runtime_mark_last_busy(mcspi->dev);
287         pm_runtime_put_autosuspend(mcspi->dev);
288         return 0;
289 }
290
291 static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
292 {
293         unsigned long timeout;
294
295         timeout = jiffies + msecs_to_jiffies(1000);
296         while (!(__raw_readl(reg) & bit)) {
297                 if (time_after(jiffies, timeout))
298                         return -1;
299                 cpu_relax();
300         }
301         return 0;
302 }
303
304 static void omap2_mcspi_rx_callback(void *data)
305 {
306         struct spi_device *spi = data;
307         struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
308         struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
309
310         complete(&mcspi_dma->dma_rx_completion);
311
312         /* We must disable the DMA RX request */
313         omap2_mcspi_set_dma_req(spi, 1, 0);
314 }
315
316 static void omap2_mcspi_tx_callback(void *data)
317 {
318         struct spi_device *spi = data;
319         struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
320         struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
321
322         complete(&mcspi_dma->dma_tx_completion);
323
324         /* We must disable the DMA TX request */
325         omap2_mcspi_set_dma_req(spi, 0, 0);
326 }
327
328 static unsigned
329 omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
330 {
331         struct omap2_mcspi      *mcspi;
332         struct omap2_mcspi_cs   *cs = spi->controller_state;
333         struct omap2_mcspi_dma  *mcspi_dma;
334         unsigned int            count;
335         int                     word_len, element_count;
336         int                     elements = 0;
337         u32                     l;
338         u8                      * rx;
339         const u8                * tx;
340         void __iomem            *chstat_reg;
341         struct dma_slave_config cfg;
342         enum dma_slave_buswidth width;
343         unsigned es;
344
345         mcspi = spi_master_get_devdata(spi->master);
346         mcspi_dma = &mcspi->dma_channels[spi->chip_select];
347         l = mcspi_cached_chconf0(spi);
348
349         chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0;
350
351         if (cs->word_len <= 8) {
352                 width = DMA_SLAVE_BUSWIDTH_1_BYTE;
353                 es = 1;
354         } else if (cs->word_len <= 16) {
355                 width = DMA_SLAVE_BUSWIDTH_2_BYTES;
356                 es = 2;
357         } else {
358                 width = DMA_SLAVE_BUSWIDTH_4_BYTES;
359                 es = 4;
360         }
361
362         memset(&cfg, 0, sizeof(cfg));
363         cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0;
364         cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0;
365         cfg.src_addr_width = width;
366         cfg.dst_addr_width = width;
367         cfg.src_maxburst = 1;
368         cfg.dst_maxburst = 1;
369
370         if (xfer->tx_buf && mcspi_dma->dma_tx) {
371                 struct dma_async_tx_descriptor *tx;
372                 struct scatterlist sg;
373
374                 dmaengine_slave_config(mcspi_dma->dma_tx, &cfg);
375
376                 sg_init_table(&sg, 1);
377                 sg_dma_address(&sg) = xfer->tx_dma;
378                 sg_dma_len(&sg) = xfer->len;
379
380                 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, &sg, 1,
381                         DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
382                 if (tx) {
383                         tx->callback = omap2_mcspi_tx_callback;
384                         tx->callback_param = spi;
385                         dmaengine_submit(tx);
386                 } else {
387                         /* FIXME: fall back to PIO? */
388                 }
389         }
390
391         if (xfer->rx_buf && mcspi_dma->dma_rx) {
392                 struct dma_async_tx_descriptor *tx;
393                 struct scatterlist sg;
394                 size_t len = xfer->len - es;
395
396                 dmaengine_slave_config(mcspi_dma->dma_rx, &cfg);
397
398                 if (l & OMAP2_MCSPI_CHCONF_TURBO)
399                         len -= es;
400
401                 sg_init_table(&sg, 1);
402                 sg_dma_address(&sg) = xfer->rx_dma;
403                 sg_dma_len(&sg) = len;
404
405                 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx, &sg, 1,
406                         DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
407                 if (tx) {
408                         tx->callback = omap2_mcspi_rx_callback;
409                         tx->callback_param = spi;
410                         dmaengine_submit(tx);
411                 } else {
412                         /* FIXME: fall back to PIO? */
413                 }
414         }
415
416         count = xfer->len;
417         word_len = cs->word_len;
418
419         rx = xfer->rx_buf;
420         tx = xfer->tx_buf;
421
422         if (word_len <= 8) {
423                 element_count = count;
424         } else if (word_len <= 16) {
425                 element_count = count >> 1;
426         } else /* word_len <= 32 */ {
427                 element_count = count >> 2;
428         }
429
430         if (tx != NULL) {
431                 dma_async_issue_pending(mcspi_dma->dma_tx);
432                 omap2_mcspi_set_dma_req(spi, 0, 1);
433         }
434
435         if (rx != NULL) {
436                 dma_async_issue_pending(mcspi_dma->dma_rx);
437                 omap2_mcspi_set_dma_req(spi, 1, 1);
438         }
439
440         if (tx != NULL) {
441                 wait_for_completion(&mcspi_dma->dma_tx_completion);
442                 dma_unmap_single(&spi->dev, xfer->tx_dma, count, DMA_TO_DEVICE);
443
444                 /* for TX_ONLY mode, be sure all words have shifted out */
445                 if (rx == NULL) {
446                         if (mcspi_wait_for_reg_bit(chstat_reg,
447                                                 OMAP2_MCSPI_CHSTAT_TXS) < 0)
448                                 dev_err(&spi->dev, "TXS timed out\n");
449                         else if (mcspi_wait_for_reg_bit(chstat_reg,
450                                                 OMAP2_MCSPI_CHSTAT_EOT) < 0)
451                                 dev_err(&spi->dev, "EOT timed out\n");
452                 }
453         }
454
455         if (rx != NULL) {
456                 wait_for_completion(&mcspi_dma->dma_rx_completion);
457                 dma_unmap_single(&spi->dev, xfer->rx_dma, count, DMA_FROM_DEVICE);
458                 omap2_mcspi_set_enable(spi, 0);
459
460                 elements = element_count - 1;
461
462                 if (l & OMAP2_MCSPI_CHCONF_TURBO) {
463                         elements--;
464
465                         if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
466                                    & OMAP2_MCSPI_CHSTAT_RXS)) {
467                                 u32 w;
468
469                                 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
470                                 if (word_len <= 8)
471                                         ((u8 *)xfer->rx_buf)[elements++] = w;
472                                 else if (word_len <= 16)
473                                         ((u16 *)xfer->rx_buf)[elements++] = w;
474                                 else /* word_len <= 32 */
475                                         ((u32 *)xfer->rx_buf)[elements++] = w;
476                         } else {
477                                 dev_err(&spi->dev,
478                                         "DMA RX penultimate word empty");
479                                 count -= (word_len <= 8)  ? 2 :
480                                         (word_len <= 16) ? 4 :
481                                         /* word_len <= 32 */ 8;
482                                 omap2_mcspi_set_enable(spi, 1);
483                                 return count;
484                         }
485                 }
486
487                 if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
488                                 & OMAP2_MCSPI_CHSTAT_RXS)) {
489                         u32 w;
490
491                         w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
492                         if (word_len <= 8)
493                                 ((u8 *)xfer->rx_buf)[elements] = w;
494                         else if (word_len <= 16)
495                                 ((u16 *)xfer->rx_buf)[elements] = w;
496                         else /* word_len <= 32 */
497                                 ((u32 *)xfer->rx_buf)[elements] = w;
498                 } else {
499                         dev_err(&spi->dev, "DMA RX last word empty");
500                         count -= (word_len <= 8)  ? 1 :
501                                  (word_len <= 16) ? 2 :
502                                /* word_len <= 32 */ 4;
503                 }
504                 omap2_mcspi_set_enable(spi, 1);
505         }
506         return count;
507 }
508
509 static unsigned
510 omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
511 {
512         struct omap2_mcspi      *mcspi;
513         struct omap2_mcspi_cs   *cs = spi->controller_state;
514         unsigned int            count, c;
515         u32                     l;
516         void __iomem            *base = cs->base;
517         void __iomem            *tx_reg;
518         void __iomem            *rx_reg;
519         void __iomem            *chstat_reg;
520         int                     word_len;
521
522         mcspi = spi_master_get_devdata(spi->master);
523         count = xfer->len;
524         c = count;
525         word_len = cs->word_len;
526
527         l = mcspi_cached_chconf0(spi);
528
529         /* We store the pre-calculated register addresses on stack to speed
530          * up the transfer loop. */
531         tx_reg          = base + OMAP2_MCSPI_TX0;
532         rx_reg          = base + OMAP2_MCSPI_RX0;
533         chstat_reg      = base + OMAP2_MCSPI_CHSTAT0;
534
535         if (c < (word_len>>3))
536                 return 0;
537
538         if (word_len <= 8) {
539                 u8              *rx;
540                 const u8        *tx;
541
542                 rx = xfer->rx_buf;
543                 tx = xfer->tx_buf;
544
545                 do {
546                         c -= 1;
547                         if (tx != NULL) {
548                                 if (mcspi_wait_for_reg_bit(chstat_reg,
549                                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
550                                         dev_err(&spi->dev, "TXS timed out\n");
551                                         goto out;
552                                 }
553                                 dev_vdbg(&spi->dev, "write-%d %02x\n",
554                                                 word_len, *tx);
555                                 __raw_writel(*tx++, tx_reg);
556                         }
557                         if (rx != NULL) {
558                                 if (mcspi_wait_for_reg_bit(chstat_reg,
559                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
560                                         dev_err(&spi->dev, "RXS timed out\n");
561                                         goto out;
562                                 }
563
564                                 if (c == 1 && tx == NULL &&
565                                     (l & OMAP2_MCSPI_CHCONF_TURBO)) {
566                                         omap2_mcspi_set_enable(spi, 0);
567                                         *rx++ = __raw_readl(rx_reg);
568                                         dev_vdbg(&spi->dev, "read-%d %02x\n",
569                                                     word_len, *(rx - 1));
570                                         if (mcspi_wait_for_reg_bit(chstat_reg,
571                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
572                                                 dev_err(&spi->dev,
573                                                         "RXS timed out\n");
574                                                 goto out;
575                                         }
576                                         c = 0;
577                                 } else if (c == 0 && tx == NULL) {
578                                         omap2_mcspi_set_enable(spi, 0);
579                                 }
580
581                                 *rx++ = __raw_readl(rx_reg);
582                                 dev_vdbg(&spi->dev, "read-%d %02x\n",
583                                                 word_len, *(rx - 1));
584                         }
585                 } while (c);
586         } else if (word_len <= 16) {
587                 u16             *rx;
588                 const u16       *tx;
589
590                 rx = xfer->rx_buf;
591                 tx = xfer->tx_buf;
592                 do {
593                         c -= 2;
594                         if (tx != NULL) {
595                                 if (mcspi_wait_for_reg_bit(chstat_reg,
596                                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
597                                         dev_err(&spi->dev, "TXS timed out\n");
598                                         goto out;
599                                 }
600                                 dev_vdbg(&spi->dev, "write-%d %04x\n",
601                                                 word_len, *tx);
602                                 __raw_writel(*tx++, tx_reg);
603                         }
604                         if (rx != NULL) {
605                                 if (mcspi_wait_for_reg_bit(chstat_reg,
606                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
607                                         dev_err(&spi->dev, "RXS timed out\n");
608                                         goto out;
609                                 }
610
611                                 if (c == 2 && tx == NULL &&
612                                     (l & OMAP2_MCSPI_CHCONF_TURBO)) {
613                                         omap2_mcspi_set_enable(spi, 0);
614                                         *rx++ = __raw_readl(rx_reg);
615                                         dev_vdbg(&spi->dev, "read-%d %04x\n",
616                                                     word_len, *(rx - 1));
617                                         if (mcspi_wait_for_reg_bit(chstat_reg,
618                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
619                                                 dev_err(&spi->dev,
620                                                         "RXS timed out\n");
621                                                 goto out;
622                                         }
623                                         c = 0;
624                                 } else if (c == 0 && tx == NULL) {
625                                         omap2_mcspi_set_enable(spi, 0);
626                                 }
627
628                                 *rx++ = __raw_readl(rx_reg);
629                                 dev_vdbg(&spi->dev, "read-%d %04x\n",
630                                                 word_len, *(rx - 1));
631                         }
632                 } while (c >= 2);
633         } else if (word_len <= 32) {
634                 u32             *rx;
635                 const u32       *tx;
636
637                 rx = xfer->rx_buf;
638                 tx = xfer->tx_buf;
639                 do {
640                         c -= 4;
641                         if (tx != NULL) {
642                                 if (mcspi_wait_for_reg_bit(chstat_reg,
643                                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
644                                         dev_err(&spi->dev, "TXS timed out\n");
645                                         goto out;
646                                 }
647                                 dev_vdbg(&spi->dev, "write-%d %08x\n",
648                                                 word_len, *tx);
649                                 __raw_writel(*tx++, tx_reg);
650                         }
651                         if (rx != NULL) {
652                                 if (mcspi_wait_for_reg_bit(chstat_reg,
653                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
654                                         dev_err(&spi->dev, "RXS timed out\n");
655                                         goto out;
656                                 }
657
658                                 if (c == 4 && tx == NULL &&
659                                     (l & OMAP2_MCSPI_CHCONF_TURBO)) {
660                                         omap2_mcspi_set_enable(spi, 0);
661                                         *rx++ = __raw_readl(rx_reg);
662                                         dev_vdbg(&spi->dev, "read-%d %08x\n",
663                                                     word_len, *(rx - 1));
664                                         if (mcspi_wait_for_reg_bit(chstat_reg,
665                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
666                                                 dev_err(&spi->dev,
667                                                         "RXS timed out\n");
668                                                 goto out;
669                                         }
670                                         c = 0;
671                                 } else if (c == 0 && tx == NULL) {
672                                         omap2_mcspi_set_enable(spi, 0);
673                                 }
674
675                                 *rx++ = __raw_readl(rx_reg);
676                                 dev_vdbg(&spi->dev, "read-%d %08x\n",
677                                                 word_len, *(rx - 1));
678                         }
679                 } while (c >= 4);
680         }
681
682         /* for TX_ONLY mode, be sure all words have shifted out */
683         if (xfer->rx_buf == NULL) {
684                 if (mcspi_wait_for_reg_bit(chstat_reg,
685                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
686                         dev_err(&spi->dev, "TXS timed out\n");
687                 } else if (mcspi_wait_for_reg_bit(chstat_reg,
688                                 OMAP2_MCSPI_CHSTAT_EOT) < 0)
689                         dev_err(&spi->dev, "EOT timed out\n");
690
691                 /* disable chan to purge rx datas received in TX_ONLY transfer,
692                  * otherwise these rx datas will affect the direct following
693                  * RX_ONLY transfer.
694                  */
695                 omap2_mcspi_set_enable(spi, 0);
696         }
697 out:
698         omap2_mcspi_set_enable(spi, 1);
699         return count - c;
700 }
701
702 static u32 omap2_mcspi_calc_divisor(u32 speed_hz)
703 {
704         u32 div;
705
706         for (div = 0; div < 15; div++)
707                 if (speed_hz >= (OMAP2_MCSPI_MAX_FREQ >> div))
708                         return div;
709
710         return 15;
711 }
712
713 /* called only when no transfer is active to this device */
714 static int omap2_mcspi_setup_transfer(struct spi_device *spi,
715                 struct spi_transfer *t)
716 {
717         struct omap2_mcspi_cs *cs = spi->controller_state;
718         struct omap2_mcspi *mcspi;
719         struct spi_master *spi_cntrl;
720         u32 l = 0, div = 0;
721         u8 word_len = spi->bits_per_word;
722         u32 speed_hz = spi->max_speed_hz;
723
724         mcspi = spi_master_get_devdata(spi->master);
725         spi_cntrl = mcspi->master;
726
727         if (t != NULL && t->bits_per_word)
728                 word_len = t->bits_per_word;
729
730         cs->word_len = word_len;
731
732         if (t && t->speed_hz)
733                 speed_hz = t->speed_hz;
734
735         speed_hz = min_t(u32, speed_hz, OMAP2_MCSPI_MAX_FREQ);
736         div = omap2_mcspi_calc_divisor(speed_hz);
737
738         l = mcspi_cached_chconf0(spi);
739
740         /* standard 4-wire master mode:  SCK, MOSI/out, MISO/in, nCS
741          * REVISIT: this controller could support SPI_3WIRE mode.
742          */
743         l &= ~(OMAP2_MCSPI_CHCONF_IS|OMAP2_MCSPI_CHCONF_DPE1);
744         l |= OMAP2_MCSPI_CHCONF_DPE0;
745
746         /* wordlength */
747         l &= ~OMAP2_MCSPI_CHCONF_WL_MASK;
748         l |= (word_len - 1) << 7;
749
750         /* set chipselect polarity; manage with FORCE */
751         if (!(spi->mode & SPI_CS_HIGH))
752                 l |= OMAP2_MCSPI_CHCONF_EPOL;   /* active-low; normal */
753         else
754                 l &= ~OMAP2_MCSPI_CHCONF_EPOL;
755
756         /* set clock divisor */
757         l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK;
758         l |= div << 2;
759
760         /* set SPI mode 0..3 */
761         if (spi->mode & SPI_CPOL)
762                 l |= OMAP2_MCSPI_CHCONF_POL;
763         else
764                 l &= ~OMAP2_MCSPI_CHCONF_POL;
765         if (spi->mode & SPI_CPHA)
766                 l |= OMAP2_MCSPI_CHCONF_PHA;
767         else
768                 l &= ~OMAP2_MCSPI_CHCONF_PHA;
769
770         mcspi_write_chconf0(spi, l);
771
772         dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n",
773                         OMAP2_MCSPI_MAX_FREQ >> div,
774                         (spi->mode & SPI_CPHA) ? "trailing" : "leading",
775                         (spi->mode & SPI_CPOL) ? "inverted" : "normal");
776
777         return 0;
778 }
779
780 static int omap2_mcspi_request_dma(struct spi_device *spi)
781 {
782         struct spi_master       *master = spi->master;
783         struct omap2_mcspi      *mcspi;
784         struct omap2_mcspi_dma  *mcspi_dma;
785         dma_cap_mask_t mask;
786         unsigned sig;
787
788         mcspi = spi_master_get_devdata(master);
789         mcspi_dma = mcspi->dma_channels + spi->chip_select;
790
791         init_completion(&mcspi_dma->dma_rx_completion);
792         init_completion(&mcspi_dma->dma_tx_completion);
793
794         dma_cap_zero(mask);
795         dma_cap_set(DMA_SLAVE, mask);
796         sig = mcspi_dma->dma_rx_sync_dev;
797         mcspi_dma->dma_rx = dma_request_channel(mask, omap_dma_filter_fn, &sig);
798         if (!mcspi_dma->dma_rx) {
799                 dev_err(&spi->dev, "no RX DMA engine channel for McSPI\n");
800                 return -EAGAIN;
801         }
802
803         sig = mcspi_dma->dma_tx_sync_dev;
804         mcspi_dma->dma_tx = dma_request_channel(mask, omap_dma_filter_fn, &sig);
805         if (!mcspi_dma->dma_tx) {
806                 dev_err(&spi->dev, "no TX DMA engine channel for McSPI\n");
807                 dma_release_channel(mcspi_dma->dma_rx);
808                 mcspi_dma->dma_rx = NULL;
809                 return -EAGAIN;
810         }
811
812         return 0;
813 }
814
815 static int omap2_mcspi_setup(struct spi_device *spi)
816 {
817         int                     ret;
818         struct omap2_mcspi      *mcspi = spi_master_get_devdata(spi->master);
819         struct omap2_mcspi_regs *ctx = &mcspi->ctx;
820         struct omap2_mcspi_dma  *mcspi_dma;
821         struct omap2_mcspi_cs   *cs = spi->controller_state;
822
823         if (spi->bits_per_word < 4 || spi->bits_per_word > 32) {
824                 dev_dbg(&spi->dev, "setup: unsupported %d bit words\n",
825                         spi->bits_per_word);
826                 return -EINVAL;
827         }
828
829         mcspi_dma = &mcspi->dma_channels[spi->chip_select];
830
831         if (!cs) {
832                 cs = kzalloc(sizeof *cs, GFP_KERNEL);
833                 if (!cs)
834                         return -ENOMEM;
835                 cs->base = mcspi->base + spi->chip_select * 0x14;
836                 cs->phys = mcspi->phys + spi->chip_select * 0x14;
837                 cs->chconf0 = 0;
838                 spi->controller_state = cs;
839                 /* Link this to context save list */
840                 list_add_tail(&cs->node, &ctx->cs);
841         }
842
843         if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx) {
844                 ret = omap2_mcspi_request_dma(spi);
845                 if (ret < 0)
846                         return ret;
847         }
848
849         ret = omap2_mcspi_enable_clocks(mcspi);
850         if (ret < 0)
851                 return ret;
852
853         ret = omap2_mcspi_setup_transfer(spi, NULL);
854         omap2_mcspi_disable_clocks(mcspi);
855
856         return ret;
857 }
858
859 static void omap2_mcspi_cleanup(struct spi_device *spi)
860 {
861         struct omap2_mcspi      *mcspi;
862         struct omap2_mcspi_dma  *mcspi_dma;
863         struct omap2_mcspi_cs   *cs;
864
865         mcspi = spi_master_get_devdata(spi->master);
866
867         if (spi->controller_state) {
868                 /* Unlink controller state from context save list */
869                 cs = spi->controller_state;
870                 list_del(&cs->node);
871
872                 kfree(cs);
873         }
874
875         if (spi->chip_select < spi->master->num_chipselect) {
876                 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
877
878                 if (mcspi_dma->dma_rx) {
879                         dma_release_channel(mcspi_dma->dma_rx);
880                         mcspi_dma->dma_rx = NULL;
881                 }
882                 if (mcspi_dma->dma_tx) {
883                         dma_release_channel(mcspi_dma->dma_tx);
884                         mcspi_dma->dma_tx = NULL;
885                 }
886         }
887 }
888
889 static void omap2_mcspi_work(struct omap2_mcspi *mcspi, struct spi_message *m)
890 {
891
892         /* We only enable one channel at a time -- the one whose message is
893          * -- although this controller would gladly
894          * arbitrate among multiple channels.  This corresponds to "single
895          * channel" master mode.  As a side effect, we need to manage the
896          * chipselect with the FORCE bit ... CS != channel enable.
897          */
898
899         struct spi_device               *spi;
900         struct spi_transfer             *t = NULL;
901         int                             cs_active = 0;
902         struct omap2_mcspi_cs           *cs;
903         struct omap2_mcspi_device_config *cd;
904         int                             par_override = 0;
905         int                             status = 0;
906         u32                             chconf;
907
908         spi = m->spi;
909         cs = spi->controller_state;
910         cd = spi->controller_data;
911
912         omap2_mcspi_set_enable(spi, 1);
913         list_for_each_entry(t, &m->transfers, transfer_list) {
914                 if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
915                         status = -EINVAL;
916                         break;
917                 }
918                 if (par_override || t->speed_hz || t->bits_per_word) {
919                         par_override = 1;
920                         status = omap2_mcspi_setup_transfer(spi, t);
921                         if (status < 0)
922                                 break;
923                         if (!t->speed_hz && !t->bits_per_word)
924                                 par_override = 0;
925                 }
926
927                 if (!cs_active) {
928                         omap2_mcspi_force_cs(spi, 1);
929                         cs_active = 1;
930                 }
931
932                 chconf = mcspi_cached_chconf0(spi);
933                 chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
934                 chconf &= ~OMAP2_MCSPI_CHCONF_TURBO;
935
936                 if (t->tx_buf == NULL)
937                         chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY;
938                 else if (t->rx_buf == NULL)
939                         chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY;
940
941                 if (cd && cd->turbo_mode && t->tx_buf == NULL) {
942                         /* Turbo mode is for more than one word */
943                         if (t->len > ((cs->word_len + 7) >> 3))
944                                 chconf |= OMAP2_MCSPI_CHCONF_TURBO;
945                 }
946
947                 mcspi_write_chconf0(spi, chconf);
948
949                 if (t->len) {
950                         unsigned        count;
951
952                         /* RX_ONLY mode needs dummy data in TX reg */
953                         if (t->tx_buf == NULL)
954                                 __raw_writel(0, cs->base
955                                                 + OMAP2_MCSPI_TX0);
956
957                         if (m->is_dma_mapped || t->len >= DMA_MIN_BYTES)
958                                 count = omap2_mcspi_txrx_dma(spi, t);
959                         else
960                                 count = omap2_mcspi_txrx_pio(spi, t);
961                         m->actual_length += count;
962
963                         if (count != t->len) {
964                                 status = -EIO;
965                                 break;
966                         }
967                 }
968
969                 if (t->delay_usecs)
970                         udelay(t->delay_usecs);
971
972                 /* ignore the "leave it on after last xfer" hint */
973                 if (t->cs_change) {
974                         omap2_mcspi_force_cs(spi, 0);
975                         cs_active = 0;
976                 }
977         }
978         /* Restore defaults if they were overriden */
979         if (par_override) {
980                 par_override = 0;
981                 status = omap2_mcspi_setup_transfer(spi, NULL);
982         }
983
984         if (cs_active)
985                 omap2_mcspi_force_cs(spi, 0);
986
987         omap2_mcspi_set_enable(spi, 0);
988
989         m->status = status;
990
991 }
992
993 static int omap2_mcspi_transfer_one_message(struct spi_master *master,
994                                                 struct spi_message *m)
995 {
996         struct omap2_mcspi      *mcspi;
997         struct spi_transfer     *t;
998
999         mcspi = spi_master_get_devdata(master);
1000         m->actual_length = 0;
1001         m->status = 0;
1002
1003         /* reject invalid messages and transfers */
1004         if (list_empty(&m->transfers))
1005                 return -EINVAL;
1006         list_for_each_entry(t, &m->transfers, transfer_list) {
1007                 const void      *tx_buf = t->tx_buf;
1008                 void            *rx_buf = t->rx_buf;
1009                 unsigned        len = t->len;
1010
1011                 if (t->speed_hz > OMAP2_MCSPI_MAX_FREQ
1012                                 || (len && !(rx_buf || tx_buf))
1013                                 || (t->bits_per_word &&
1014                                         (  t->bits_per_word < 4
1015                                         || t->bits_per_word > 32))) {
1016                         dev_dbg(mcspi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n",
1017                                         t->speed_hz,
1018                                         len,
1019                                         tx_buf ? "tx" : "",
1020                                         rx_buf ? "rx" : "",
1021                                         t->bits_per_word);
1022                         return -EINVAL;
1023                 }
1024                 if (t->speed_hz && t->speed_hz < (OMAP2_MCSPI_MAX_FREQ >> 15)) {
1025                         dev_dbg(mcspi->dev, "speed_hz %d below minimum %d Hz\n",
1026                                 t->speed_hz,
1027                                 OMAP2_MCSPI_MAX_FREQ >> 15);
1028                         return -EINVAL;
1029                 }
1030
1031                 if (m->is_dma_mapped || len < DMA_MIN_BYTES)
1032                         continue;
1033
1034                 if (tx_buf != NULL) {
1035                         t->tx_dma = dma_map_single(mcspi->dev, (void *) tx_buf,
1036                                         len, DMA_TO_DEVICE);
1037                         if (dma_mapping_error(mcspi->dev, t->tx_dma)) {
1038                                 dev_dbg(mcspi->dev, "dma %cX %d bytes error\n",
1039                                                 'T', len);
1040                                 return -EINVAL;
1041                         }
1042                 }
1043                 if (rx_buf != NULL) {
1044                         t->rx_dma = dma_map_single(mcspi->dev, rx_buf, t->len,
1045                                         DMA_FROM_DEVICE);
1046                         if (dma_mapping_error(mcspi->dev, t->rx_dma)) {
1047                                 dev_dbg(mcspi->dev, "dma %cX %d bytes error\n",
1048                                                 'R', len);
1049                                 if (tx_buf != NULL)
1050                                         dma_unmap_single(mcspi->dev, t->tx_dma,
1051                                                         len, DMA_TO_DEVICE);
1052                                 return -EINVAL;
1053                         }
1054                 }
1055         }
1056
1057         omap2_mcspi_work(mcspi, m);
1058         spi_finalize_current_message(master);
1059         return 0;
1060 }
1061
1062 static int __init omap2_mcspi_master_setup(struct omap2_mcspi *mcspi)
1063 {
1064         struct spi_master       *master = mcspi->master;
1065         struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1066         int                     ret = 0;
1067
1068         ret = omap2_mcspi_enable_clocks(mcspi);
1069         if (ret < 0)
1070                 return ret;
1071
1072         mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE,
1073                                 OMAP2_MCSPI_WAKEUPENABLE_WKEN);
1074         ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN;
1075
1076         omap2_mcspi_set_master_mode(master);
1077         omap2_mcspi_disable_clocks(mcspi);
1078         return 0;
1079 }
1080
1081 static int omap_mcspi_runtime_resume(struct device *dev)
1082 {
1083         struct omap2_mcspi      *mcspi;
1084         struct spi_master       *master;
1085
1086         master = dev_get_drvdata(dev);
1087         mcspi = spi_master_get_devdata(master);
1088         omap2_mcspi_restore_ctx(mcspi);
1089
1090         return 0;
1091 }
1092
1093 static struct omap2_mcspi_platform_config omap2_pdata = {
1094         .regs_offset = 0,
1095 };
1096
1097 static struct omap2_mcspi_platform_config omap4_pdata = {
1098         .regs_offset = OMAP4_MCSPI_REG_OFFSET,
1099 };
1100
1101 static const struct of_device_id omap_mcspi_of_match[] = {
1102         {
1103                 .compatible = "ti,omap2-mcspi",
1104                 .data = &omap2_pdata,
1105         },
1106         {
1107                 .compatible = "ti,omap4-mcspi",
1108                 .data = &omap4_pdata,
1109         },
1110         { },
1111 };
1112 MODULE_DEVICE_TABLE(of, omap_mcspi_of_match);
1113
1114 static int __devinit omap2_mcspi_probe(struct platform_device *pdev)
1115 {
1116         struct spi_master       *master;
1117         struct omap2_mcspi_platform_config *pdata;
1118         struct omap2_mcspi      *mcspi;
1119         struct resource         *r;
1120         int                     status = 0, i;
1121         u32                     regs_offset = 0;
1122         static int              bus_num = 1;
1123         struct device_node      *node = pdev->dev.of_node;
1124         const struct of_device_id *match;
1125
1126         master = spi_alloc_master(&pdev->dev, sizeof *mcspi);
1127         if (master == NULL) {
1128                 dev_dbg(&pdev->dev, "master allocation failed\n");
1129                 return -ENOMEM;
1130         }
1131
1132         /* the spi->mode bits understood by this driver: */
1133         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1134
1135         master->setup = omap2_mcspi_setup;
1136         master->prepare_transfer_hardware = omap2_prepare_transfer;
1137         master->unprepare_transfer_hardware = omap2_unprepare_transfer;
1138         master->transfer_one_message = omap2_mcspi_transfer_one_message;
1139         master->cleanup = omap2_mcspi_cleanup;
1140         master->dev.of_node = node;
1141
1142         match = of_match_device(omap_mcspi_of_match, &pdev->dev);
1143         if (match) {
1144                 u32 num_cs = 1; /* default number of chipselect */
1145                 pdata = match->data;
1146
1147                 of_property_read_u32(node, "ti,spi-num-cs", &num_cs);
1148                 master->num_chipselect = num_cs;
1149                 master->bus_num = bus_num++;
1150         } else {
1151                 pdata = pdev->dev.platform_data;
1152                 master->num_chipselect = pdata->num_cs;
1153                 if (pdev->id != -1)
1154                         master->bus_num = pdev->id;
1155         }
1156         regs_offset = pdata->regs_offset;
1157
1158         dev_set_drvdata(&pdev->dev, master);
1159
1160         mcspi = spi_master_get_devdata(master);
1161         mcspi->master = master;
1162
1163         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1164         if (r == NULL) {
1165                 status = -ENODEV;
1166                 goto free_master;
1167         }
1168
1169         r->start += regs_offset;
1170         r->end += regs_offset;
1171         mcspi->phys = r->start;
1172
1173         mcspi->base = devm_request_and_ioremap(&pdev->dev, r);
1174         if (!mcspi->base) {
1175                 dev_dbg(&pdev->dev, "can't ioremap MCSPI\n");
1176                 status = -ENOMEM;
1177                 goto free_master;
1178         }
1179
1180         mcspi->dev = &pdev->dev;
1181
1182         INIT_LIST_HEAD(&mcspi->ctx.cs);
1183
1184         mcspi->dma_channels = kcalloc(master->num_chipselect,
1185                         sizeof(struct omap2_mcspi_dma),
1186                         GFP_KERNEL);
1187
1188         if (mcspi->dma_channels == NULL)
1189                 goto free_master;
1190
1191         for (i = 0; i < master->num_chipselect; i++) {
1192                 char dma_ch_name[14];
1193                 struct resource *dma_res;
1194
1195                 sprintf(dma_ch_name, "rx%d", i);
1196                 dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA,
1197                                                         dma_ch_name);
1198                 if (!dma_res) {
1199                         dev_dbg(&pdev->dev, "cannot get DMA RX channel\n");
1200                         status = -ENODEV;
1201                         break;
1202                 }
1203
1204                 mcspi->dma_channels[i].dma_rx_sync_dev = dma_res->start;
1205                 sprintf(dma_ch_name, "tx%d", i);
1206                 dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA,
1207                                                         dma_ch_name);
1208                 if (!dma_res) {
1209                         dev_dbg(&pdev->dev, "cannot get DMA TX channel\n");
1210                         status = -ENODEV;
1211                         break;
1212                 }
1213
1214                 mcspi->dma_channels[i].dma_tx_sync_dev = dma_res->start;
1215         }
1216
1217         if (status < 0)
1218                 goto dma_chnl_free;
1219
1220         pm_runtime_use_autosuspend(&pdev->dev);
1221         pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
1222         pm_runtime_enable(&pdev->dev);
1223
1224         if (status || omap2_mcspi_master_setup(mcspi) < 0)
1225                 goto disable_pm;
1226
1227         status = spi_register_master(master);
1228         if (status < 0)
1229                 goto err_spi_register;
1230
1231         return status;
1232
1233 err_spi_register:
1234         spi_master_put(master);
1235 disable_pm:
1236         pm_runtime_disable(&pdev->dev);
1237 dma_chnl_free:
1238         kfree(mcspi->dma_channels);
1239 free_master:
1240         kfree(master);
1241         platform_set_drvdata(pdev, NULL);
1242         return status;
1243 }
1244
1245 static int __devexit omap2_mcspi_remove(struct platform_device *pdev)
1246 {
1247         struct spi_master       *master;
1248         struct omap2_mcspi      *mcspi;
1249         struct omap2_mcspi_dma  *dma_channels;
1250
1251         master = dev_get_drvdata(&pdev->dev);
1252         mcspi = spi_master_get_devdata(master);
1253         dma_channels = mcspi->dma_channels;
1254
1255         omap2_mcspi_disable_clocks(mcspi);
1256         pm_runtime_disable(&pdev->dev);
1257
1258         spi_unregister_master(master);
1259         kfree(dma_channels);
1260         platform_set_drvdata(pdev, NULL);
1261
1262         return 0;
1263 }
1264
1265 /* work with hotplug and coldplug */
1266 MODULE_ALIAS("platform:omap2_mcspi");
1267
1268 #ifdef  CONFIG_SUSPEND
1269 /*
1270  * When SPI wake up from off-mode, CS is in activate state. If it was in
1271  * unactive state when driver was suspend, then force it to unactive state at
1272  * wake up.
1273  */
1274 static int omap2_mcspi_resume(struct device *dev)
1275 {
1276         struct spi_master       *master = dev_get_drvdata(dev);
1277         struct omap2_mcspi      *mcspi = spi_master_get_devdata(master);
1278         struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1279         struct omap2_mcspi_cs   *cs;
1280
1281         omap2_mcspi_enable_clocks(mcspi);
1282         list_for_each_entry(cs, &ctx->cs, node) {
1283                 if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) {
1284                         /*
1285                          * We need to toggle CS state for OMAP take this
1286                          * change in account.
1287                          */
1288                         MOD_REG_BIT(cs->chconf0, OMAP2_MCSPI_CHCONF_FORCE, 1);
1289                         __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
1290                         MOD_REG_BIT(cs->chconf0, OMAP2_MCSPI_CHCONF_FORCE, 0);
1291                         __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
1292                 }
1293         }
1294         omap2_mcspi_disable_clocks(mcspi);
1295         return 0;
1296 }
1297 #else
1298 #define omap2_mcspi_resume      NULL
1299 #endif
1300
1301 static const struct dev_pm_ops omap2_mcspi_pm_ops = {
1302         .resume = omap2_mcspi_resume,
1303         .runtime_resume = omap_mcspi_runtime_resume,
1304 };
1305
1306 static struct platform_driver omap2_mcspi_driver = {
1307         .driver = {
1308                 .name =         "omap2_mcspi",
1309                 .owner =        THIS_MODULE,
1310                 .pm =           &omap2_mcspi_pm_ops,
1311                 .of_match_table = omap_mcspi_of_match,
1312         },
1313         .probe =        omap2_mcspi_probe,
1314         .remove =       __devexit_p(omap2_mcspi_remove),
1315 };
1316
1317 module_platform_driver(omap2_mcspi_driver);
1318 MODULE_LICENSE("GPL");