Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial
[linux-3.10.git] / drivers / net / wireless / iwlwifi / iwl-io.c
1 /******************************************************************************
2  *
3  * Copyright(c) 2003 - 2012 Intel Corporation. All rights reserved.
4  *
5  * Portions of this file are derived from the ipw3945 project.
6  *
7  * This program is free software; you can redistribute it and/or modify it
8  * under the terms of version 2 of the GNU General Public License as
9  * published by the Free Software Foundation.
10  *
11  * This program is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along with
17  * this program; if not, write to the Free Software Foundation, Inc.,
18  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
19  *
20  * The full GNU General Public License is included in this distribution in the
21  * file called LICENSE.
22  *
23  * Contact Information:
24  *  Intel Linux Wireless <ilw@linux.intel.com>
25  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26  *
27  *****************************************************************************/
28 #include <linux/delay.h>
29 #include <linux/device.h>
30 #include <linux/export.h>
31
32 #include "iwl-io.h"
33 #include "iwl-csr.h"
34 #include "iwl-debug.h"
35
36 #define IWL_POLL_INTERVAL 10    /* microseconds */
37
38 static inline void __iwl_set_bit(struct iwl_trans *trans, u32 reg, u32 mask)
39 {
40         iwl_write32(trans, reg, iwl_read32(trans, reg) | mask);
41 }
42
43 static inline void __iwl_clear_bit(struct iwl_trans *trans, u32 reg, u32 mask)
44 {
45         iwl_write32(trans, reg, iwl_read32(trans, reg) & ~mask);
46 }
47
48 void iwl_set_bit(struct iwl_trans *trans, u32 reg, u32 mask)
49 {
50         unsigned long flags;
51
52         spin_lock_irqsave(&trans->reg_lock, flags);
53         __iwl_set_bit(trans, reg, mask);
54         spin_unlock_irqrestore(&trans->reg_lock, flags);
55 }
56 EXPORT_SYMBOL_GPL(iwl_set_bit);
57
58 void iwl_clear_bit(struct iwl_trans *trans, u32 reg, u32 mask)
59 {
60         unsigned long flags;
61
62         spin_lock_irqsave(&trans->reg_lock, flags);
63         __iwl_clear_bit(trans, reg, mask);
64         spin_unlock_irqrestore(&trans->reg_lock, flags);
65 }
66 EXPORT_SYMBOL_GPL(iwl_clear_bit);
67
68 void iwl_set_bits_mask(struct iwl_trans *trans, u32 reg, u32 mask, u32 value)
69 {
70         unsigned long flags;
71         u32 v;
72
73 #ifdef CONFIG_IWLWIFI_DEBUG
74         WARN_ON_ONCE(value & ~mask);
75 #endif
76
77         spin_lock_irqsave(&trans->reg_lock, flags);
78         v = iwl_read32(trans, reg);
79         v &= ~mask;
80         v |= value;
81         iwl_write32(trans, reg, v);
82         spin_unlock_irqrestore(&trans->reg_lock, flags);
83 }
84 EXPORT_SYMBOL_GPL(iwl_set_bits_mask);
85
86 int iwl_poll_bit(struct iwl_trans *trans, u32 addr,
87                  u32 bits, u32 mask, int timeout)
88 {
89         int t = 0;
90
91         do {
92                 if ((iwl_read32(trans, addr) & mask) == (bits & mask))
93                         return t;
94                 udelay(IWL_POLL_INTERVAL);
95                 t += IWL_POLL_INTERVAL;
96         } while (t < timeout);
97
98         return -ETIMEDOUT;
99 }
100 EXPORT_SYMBOL_GPL(iwl_poll_bit);
101
102 int iwl_grab_nic_access_silent(struct iwl_trans *trans)
103 {
104         int ret;
105
106         lockdep_assert_held(&trans->reg_lock);
107
108         /* this bit wakes up the NIC */
109         __iwl_set_bit(trans, CSR_GP_CNTRL,
110                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
111
112         /*
113          * These bits say the device is running, and should keep running for
114          * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
115          * but they do not indicate that embedded SRAM is restored yet;
116          * 3945 and 4965 have volatile SRAM, and must save/restore contents
117          * to/from host DRAM when sleeping/waking for power-saving.
118          * Each direction takes approximately 1/4 millisecond; with this
119          * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
120          * series of register accesses are expected (e.g. reading Event Log),
121          * to keep device from sleeping.
122          *
123          * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
124          * SRAM is okay/restored.  We don't check that here because this call
125          * is just for hardware register access; but GP1 MAC_SLEEP check is a
126          * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
127          *
128          * 5000 series and later (including 1000 series) have non-volatile SRAM,
129          * and do not save/restore SRAM when power cycling.
130          */
131         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
132                            CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
133                            (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
134                             CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
135         if (ret < 0) {
136                 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
137                 return -EIO;
138         }
139
140         return 0;
141 }
142 EXPORT_SYMBOL_GPL(iwl_grab_nic_access_silent);
143
144 bool iwl_grab_nic_access(struct iwl_trans *trans)
145 {
146         int ret = iwl_grab_nic_access_silent(trans);
147         if (unlikely(ret)) {
148                 u32 val = iwl_read32(trans, CSR_GP_CNTRL);
149                 WARN_ONCE(1, "Timeout waiting for hardware access "
150                              "(CSR_GP_CNTRL 0x%08x)\n", val);
151                 return false;
152         }
153
154         return true;
155 }
156 EXPORT_SYMBOL_GPL(iwl_grab_nic_access);
157
158 void iwl_release_nic_access(struct iwl_trans *trans)
159 {
160         lockdep_assert_held(&trans->reg_lock);
161         __iwl_clear_bit(trans, CSR_GP_CNTRL,
162                         CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
163         /*
164          * Above we read the CSR_GP_CNTRL register, which will flush
165          * any previous writes, but we need the write that clears the
166          * MAC_ACCESS_REQ bit to be performed before any other writes
167          * scheduled on different CPUs (after we drop reg_lock).
168          */
169         mmiowb();
170 }
171 EXPORT_SYMBOL_GPL(iwl_release_nic_access);
172
173 u32 iwl_read_direct32(struct iwl_trans *trans, u32 reg)
174 {
175         u32 value;
176         unsigned long flags;
177
178         spin_lock_irqsave(&trans->reg_lock, flags);
179         iwl_grab_nic_access(trans);
180         value = iwl_read32(trans, reg);
181         iwl_release_nic_access(trans);
182         spin_unlock_irqrestore(&trans->reg_lock, flags);
183
184         return value;
185 }
186 EXPORT_SYMBOL_GPL(iwl_read_direct32);
187
188 void iwl_write_direct32(struct iwl_trans *trans, u32 reg, u32 value)
189 {
190         unsigned long flags;
191
192         spin_lock_irqsave(&trans->reg_lock, flags);
193         if (likely(iwl_grab_nic_access(trans))) {
194                 iwl_write32(trans, reg, value);
195                 iwl_release_nic_access(trans);
196         }
197         spin_unlock_irqrestore(&trans->reg_lock, flags);
198 }
199 EXPORT_SYMBOL_GPL(iwl_write_direct32);
200
201 int iwl_poll_direct_bit(struct iwl_trans *trans, u32 addr, u32 mask,
202                         int timeout)
203 {
204         int t = 0;
205
206         do {
207                 if ((iwl_read_direct32(trans, addr) & mask) == mask)
208                         return t;
209                 udelay(IWL_POLL_INTERVAL);
210                 t += IWL_POLL_INTERVAL;
211         } while (t < timeout);
212
213         return -ETIMEDOUT;
214 }
215 EXPORT_SYMBOL_GPL(iwl_poll_direct_bit);
216
217 static inline u32 __iwl_read_prph(struct iwl_trans *trans, u32 reg)
218 {
219         iwl_write32(trans, HBUS_TARG_PRPH_RADDR, reg | (3 << 24));
220         return iwl_read32(trans, HBUS_TARG_PRPH_RDAT);
221 }
222
223 static inline void __iwl_write_prph(struct iwl_trans *trans, u32 addr, u32 val)
224 {
225         iwl_write32(trans, HBUS_TARG_PRPH_WADDR,
226                     ((addr & 0x0000FFFF) | (3 << 24)));
227         iwl_write32(trans, HBUS_TARG_PRPH_WDAT, val);
228 }
229
230 u32 iwl_read_prph(struct iwl_trans *trans, u32 reg)
231 {
232         unsigned long flags;
233         u32 val;
234
235         spin_lock_irqsave(&trans->reg_lock, flags);
236         iwl_grab_nic_access(trans);
237         val = __iwl_read_prph(trans, reg);
238         iwl_release_nic_access(trans);
239         spin_unlock_irqrestore(&trans->reg_lock, flags);
240         return val;
241 }
242 EXPORT_SYMBOL_GPL(iwl_read_prph);
243
244 void iwl_write_prph(struct iwl_trans *trans, u32 addr, u32 val)
245 {
246         unsigned long flags;
247
248         spin_lock_irqsave(&trans->reg_lock, flags);
249         if (likely(iwl_grab_nic_access(trans))) {
250                 __iwl_write_prph(trans, addr, val);
251                 iwl_release_nic_access(trans);
252         }
253         spin_unlock_irqrestore(&trans->reg_lock, flags);
254 }
255 EXPORT_SYMBOL_GPL(iwl_write_prph);
256
257 void iwl_set_bits_prph(struct iwl_trans *trans, u32 reg, u32 mask)
258 {
259         unsigned long flags;
260
261         spin_lock_irqsave(&trans->reg_lock, flags);
262         if (likely(iwl_grab_nic_access(trans))) {
263                 __iwl_write_prph(trans, reg,
264                                  __iwl_read_prph(trans, reg) | mask);
265                 iwl_release_nic_access(trans);
266         }
267         spin_unlock_irqrestore(&trans->reg_lock, flags);
268 }
269 EXPORT_SYMBOL_GPL(iwl_set_bits_prph);
270
271 void iwl_set_bits_mask_prph(struct iwl_trans *trans, u32 reg,
272                             u32 bits, u32 mask)
273 {
274         unsigned long flags;
275
276         spin_lock_irqsave(&trans->reg_lock, flags);
277         if (likely(iwl_grab_nic_access(trans))) {
278                 __iwl_write_prph(trans, reg,
279                                  (__iwl_read_prph(trans, reg) & mask) | bits);
280                 iwl_release_nic_access(trans);
281         }
282         spin_unlock_irqrestore(&trans->reg_lock, flags);
283 }
284 EXPORT_SYMBOL_GPL(iwl_set_bits_mask_prph);
285
286 void iwl_clear_bits_prph(struct iwl_trans *trans, u32 reg, u32 mask)
287 {
288         unsigned long flags;
289         u32 val;
290
291         spin_lock_irqsave(&trans->reg_lock, flags);
292         if (likely(iwl_grab_nic_access(trans))) {
293                 val = __iwl_read_prph(trans, reg);
294                 __iwl_write_prph(trans, reg, (val & ~mask));
295                 iwl_release_nic_access(trans);
296         }
297         spin_unlock_irqrestore(&trans->reg_lock, flags);
298 }
299 EXPORT_SYMBOL_GPL(iwl_clear_bits_prph);
300
301 void _iwl_read_targ_mem_dwords(struct iwl_trans *trans, u32 addr,
302                                void *buf, int dwords)
303 {
304         unsigned long flags;
305         int offs;
306         u32 *vals = buf;
307
308         spin_lock_irqsave(&trans->reg_lock, flags);
309         if (likely(iwl_grab_nic_access(trans))) {
310                 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
311                 for (offs = 0; offs < dwords; offs++)
312                         vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
313                 iwl_release_nic_access(trans);
314         }
315         spin_unlock_irqrestore(&trans->reg_lock, flags);
316 }
317 EXPORT_SYMBOL_GPL(_iwl_read_targ_mem_dwords);
318
319 u32 iwl_read_targ_mem(struct iwl_trans *trans, u32 addr)
320 {
321         u32 value;
322
323         _iwl_read_targ_mem_dwords(trans, addr, &value, 1);
324
325         return value;
326 }
327 EXPORT_SYMBOL_GPL(iwl_read_targ_mem);
328
329 int _iwl_write_targ_mem_dwords(struct iwl_trans *trans, u32 addr,
330                                void *buf, int dwords)
331 {
332         unsigned long flags;
333         int offs, result = 0;
334         u32 *vals = buf;
335
336         spin_lock_irqsave(&trans->reg_lock, flags);
337         if (likely(iwl_grab_nic_access(trans))) {
338                 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
339                 for (offs = 0; offs < dwords; offs++)
340                         iwl_write32(trans, HBUS_TARG_MEM_WDAT, vals[offs]);
341                 iwl_release_nic_access(trans);
342         } else
343                 result = -EBUSY;
344         spin_unlock_irqrestore(&trans->reg_lock, flags);
345
346         return result;
347 }
348 EXPORT_SYMBOL_GPL(_iwl_write_targ_mem_dwords);
349
350 int iwl_write_targ_mem(struct iwl_trans *trans, u32 addr, u32 val)
351 {
352         return _iwl_write_targ_mem_dwords(trans, addr, &val, 1);
353 }
354 EXPORT_SYMBOL_GPL(iwl_write_targ_mem);